2019-05-15 20:41:58 +08:00
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# RUN: llc %s -run-pass machine-scheduler -o - | FileCheck %s
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# CHECK-LABEL: bb.0.
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# CHECK: t2LDRi12
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# CHECK-NEXT: t2LDRi12
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# CHECK-NEXT: t2ADDri
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# CHECK-NEXT: t2ADDri
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--- |
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv7em-arm-none-eabi"
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; Function Attrs: norecurse nounwind optsize readonly
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define dso_local i32 @test(i32* nocapture readonly %a, i32* nocapture readonly %b) local_unnamed_addr #0 {
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entry:
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%0 = load i32, i32* %a, align 4
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%add = add nsw i32 %0, 10
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%1 = load i32, i32* %b, align 4
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%add1 = add nsw i32 %1, 20
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%mul = mul nsw i32 %add1, %add
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ret i32 %mul
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}
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attributes #0 = { "target-cpu"="cortex-m4" }
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...
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---
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name: test
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[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67433
llvm-svn: 371608
2019-09-11 19:16:48 +08:00
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alignment: 2
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2019-05-15 20:41:58 +08:00
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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- { id: 2, class: gprnopc, preferred-register: '' }
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- { id: 3, class: rgpr, preferred-register: '' }
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- { id: 4, class: gprnopc, preferred-register: '' }
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- { id: 5, class: rgpr, preferred-register: '' }
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- { id: 6, class: rgpr, preferred-register: '' }
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liveins:
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- { reg: '$r0', virtual-reg: '%0' }
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- { reg: '$r1', virtual-reg: '%1' }
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body: |
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bb.0.entry:
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liveins: $r0, $r1
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%1:gpr = COPY $r1
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%0:gpr = COPY $r0
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%2:gprnopc = t2LDRi12 %0, 0, 14, $noreg :: (load 4 from %ir.a)
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%3:rgpr = nsw t2ADDri %2, 10, 14, $noreg, $noreg
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%4:gprnopc = t2LDRi12 %1, 0, 14, $noreg :: (load 4 from %ir.b)
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%5:rgpr = nsw t2ADDri %4, 20, 14, $noreg, $noreg
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%6:rgpr = nsw t2MUL %5, %3, 14, $noreg
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$r0 = COPY %6
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tBX_RET 14, $noreg, implicit $r0
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...
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