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llvm-project/llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir

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[AMDGPU] gfx1010 premlane instructions Differential Revision: https://reviews.llvm.org/D63202 llvm-svn: 363185
2019-06-13 01:52:51 +08:00
# RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass si-insert-skips,post-RA-hazard-rec -o - %s | FileCheck -check-prefix=GCN %s
# GCN-LABEL: name: hazard_vcmpx_permlane16
# GCN: V_CMPX_LE_F32_nosdst_e32
# GCN: S_ADD_U32
# GCN-NEXT: $vgpr1 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
# GCN-NEXT: V_PERMLANE16_B32
---
name: hazard_vcmpx_permlane16
body: |
bb.0:
successors: %bb.1
$vgpr0 = V_MOV_B32_e32 0, implicit $exec
SI_KILL_F32_COND_IMM_TERMINATOR $vgpr0, 0, 3, implicit-def $exec, implicit-def $vcc, implicit-def $scc, implicit $exec
S_BRANCH %bb.1
bb.1:
$vgpr1 = IMPLICIT_DEF
$vgpr2 = IMPLICIT_DEF
$sgpr0 = IMPLICIT_DEF
$sgpr1 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
$vgpr1 = V_PERMLANE16_B32 0, killed $vgpr1, 0, killed $sgpr1, 0, killed $sgpr0, $vgpr1, 0, implicit $exec
S_ENDPGM 0
...
# GCN-LABEL: name: hazard_vcmpx_permlanex16
# GCN: V_CMPX_LE_F32_nosdst_e32
# GCN: $vgpr1 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
# GCN-NEXT: V_PERMLANEX16_B32
---
name: hazard_vcmpx_permlanex16
body: |
bb.0:
successors: %bb.1
$vgpr0 = V_MOV_B32_e32 0, implicit $exec
SI_KILL_F32_COND_IMM_TERMINATOR $vgpr0, 0, 3, implicit-def $exec, implicit-def $vcc, implicit-def $scc, implicit $exec
S_BRANCH %bb.1
bb.1:
$vgpr1 = IMPLICIT_DEF
$vgpr2 = IMPLICIT_DEF
$sgpr0 = IMPLICIT_DEF
$sgpr1 = IMPLICIT_DEF
$vgpr1 = V_PERMLANEX16_B32 0, killed $vgpr1, 0, killed $sgpr1, 0, killed $sgpr0, $vgpr1, 0, implicit $exec
S_ENDPGM 0
...
# GCN-LABEL: name: hazard_vcmpx_permlane16_v_nop
# GCN: V_CMPX_LE_F32_nosdst_e32
# GCN: V_NOP
# GCN-NEXT: $vgpr1 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
# GCN-NEXT: V_PERMLANE16_B32
---
name: hazard_vcmpx_permlane16_v_nop
body: |
bb.0:
successors: %bb.1
$vgpr0 = V_MOV_B32_e32 0, implicit $exec
SI_KILL_F32_COND_IMM_TERMINATOR $vgpr0, 0, 3, implicit-def $exec, implicit-def $vcc, implicit-def $scc, implicit $exec
S_BRANCH %bb.1
bb.1:
$vgpr1 = IMPLICIT_DEF
$vgpr2 = IMPLICIT_DEF
$sgpr0 = IMPLICIT_DEF
$sgpr1 = IMPLICIT_DEF
V_NOP_e32 implicit $exec
$vgpr1 = V_PERMLANE16_B32 0, killed $vgpr1, 0, killed $sgpr1, 0, killed $sgpr0, $vgpr1, 0, implicit $exec
S_ENDPGM 0
...
# GCN-LABEL: name: hazard_vcmpx_permlane16_far
# GCN: V_CMPX_LE_F32_nosdst_e32
# GCN: $vgpr1 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
# GCN-NEXT: V_PERMLANE16_B32
---
name: hazard_vcmpx_permlane16_far
body: |
bb.0:
successors: %bb.1
$vgpr0 = V_MOV_B32_e32 0, implicit $exec
SI_KILL_F32_COND_IMM_TERMINATOR $vgpr0, 0, 3, implicit-def $exec, implicit-def $vcc, implicit-def $scc, implicit $exec
S_BRANCH %bb.1
bb.1:
$vgpr1 = IMPLICIT_DEF
$vgpr2 = IMPLICIT_DEF
$sgpr0 = IMPLICIT_DEF
$sgpr1 = IMPLICIT_DEF
V_NOP_e32 implicit $exec
V_NOP_e32 implicit $exec
V_NOP_e32 implicit $exec
V_NOP_e32 implicit $exec
V_NOP_e32 implicit $exec
V_NOP_e32 implicit $exec
V_NOP_e32 implicit $exec
V_NOP_e32 implicit $exec
V_NOP_e32 implicit $exec
$vgpr1 = V_PERMLANE16_B32 0, killed $vgpr1, 0, killed $sgpr1, 0, killed $sgpr0, $vgpr1, 0, implicit $exec
S_ENDPGM 0
...
# GCN-LABEL: name: hazard_vcmpx_permlane16_no_hazard
# GCN: V_CMPX_LE_F32_nosdst_e32
# GCN: V_ADD_F32
# GCN-NEXT: V_PERMLANE16_B32
---
name: hazard_vcmpx_permlane16_no_hazard
body: |
bb.0:
successors: %bb.1
$vgpr0 = V_MOV_B32_e32 0, implicit $exec
SI_KILL_F32_COND_IMM_TERMINATOR $vgpr0, 0, 3, implicit-def $exec, implicit-def $vcc, implicit-def $scc, implicit $exec
S_BRANCH %bb.1
bb.1:
$vgpr1 = IMPLICIT_DEF
$sgpr0 = IMPLICIT_DEF
$sgpr1 = IMPLICIT_DEF
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
$vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
[AMDGPU] gfx1010 premlane instructions Differential Revision: https://reviews.llvm.org/D63202 llvm-svn: 363185
2019-06-13 01:52:51 +08:00
$vgpr1 = V_PERMLANE16_B32 0, killed $vgpr1, 0, killed $sgpr1, 0, killed $sgpr0, $vgpr1, 0, implicit $exec
S_ENDPGM 0
...
# GCN-LABEL: name: hazard_vcmpx_permlane16_undef_src
# GCN: V_CMPX_LE_F32_nosdst_e32
# GCN: S_ADD_U32
# GCN-NEXT: dead $vgpr1 = V_MOV_B32_e32 undef $vgpr1, implicit $exec
# GCN-NEXT: V_PERMLANE16_B32
---
name: hazard_vcmpx_permlane16_undef_src
body: |
bb.0:
successors: %bb.1
$vgpr0 = V_MOV_B32_e32 0, implicit $exec
SI_KILL_F32_COND_IMM_TERMINATOR $vgpr0, 0, 3, implicit-def $exec, implicit-def $vcc, implicit-def $scc, implicit $exec
S_BRANCH %bb.1
bb.1:
$vgpr2 = IMPLICIT_DEF
$sgpr0 = IMPLICIT_DEF
$sgpr1 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
$vgpr1 = V_PERMLANE16_B32 0, undef $vgpr1, 0, killed $sgpr1, 0, killed $sgpr0, undef $vgpr1, 0, implicit $exec
S_ENDPGM 0
...