[InstCombine] Add tests to show missing fold opportunity for "icmp and shift" (nfc).
Summary:
For icmp pred (and (sh X, Y), C), 0
When C is signbit, expect to fold (X << Y) & signbit ==/!= 0 into (X << Y) >=/< 0,
rather than (X & (signbit >> Y)) != 0.
When C+1 is power of 2, expect to fold (X << Y) & ~C ==/!= 0 into (X << Y) </>= C+1,
rather than (X & (~C >> Y)) == 0.
For icmp pred (and X, (sh signbit, Y)), 0
Expect to fold (X & (signbit l>> Y)) ==/!= 0 into (X << Y) >=/< 0
Expect to fold (X & (signbit << Y)) ==/!= 0 into (X l>> Y) >=/< 0
Reviewers: lebedev.ri, efriedma, spatel, craig.topper
Reviewed By: lebedev.ri
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63025
llvm-svn: 363479
2019-06-15 08:33:41 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt %s -instcombine -S | FileCheck %s
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; For pattern ((X << Y) & ~C) ==/!= 0; when C+1 is power of 2
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; it may be optimal to fold into (X << Y) </>= C+1
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; rather than X & (~C l>> Y) ==/!= 0
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; Scalar tests
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define i1 @scalar_i8_shl_and_negC_eq(i8 %x, i8 %y) {
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; CHECK-LABEL: @scalar_i8_shl_and_negC_eq(
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2019-06-25 08:09:10 +08:00
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; CHECK-NEXT: [[SHL:%.*]] = shl i8 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[SHL]], 4
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[InstCombine] Add tests to show missing fold opportunity for "icmp and shift" (nfc).
Summary:
For icmp pred (and (sh X, Y), C), 0
When C is signbit, expect to fold (X << Y) & signbit ==/!= 0 into (X << Y) >=/< 0,
rather than (X & (signbit >> Y)) != 0.
When C+1 is power of 2, expect to fold (X << Y) & ~C ==/!= 0 into (X << Y) </>= C+1,
rather than (X & (~C >> Y)) == 0.
For icmp pred (and X, (sh signbit, Y)), 0
Expect to fold (X & (signbit l>> Y)) ==/!= 0 into (X << Y) >=/< 0
Expect to fold (X & (signbit << Y)) ==/!= 0 into (X l>> Y) >=/< 0
Reviewers: lebedev.ri, efriedma, spatel, craig.topper
Reviewed By: lebedev.ri
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63025
llvm-svn: 363479
2019-06-15 08:33:41 +08:00
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; CHECK-NEXT: ret i1 [[R]]
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;
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%shl = shl i8 %x, %y
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%and = and i8 %shl, 252 ; ~3
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%r = icmp eq i8 %and, 0
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ret i1 %r
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}
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define i1 @scalar_i16_shl_and_negC_eq(i16 %x, i16 %y) {
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; CHECK-LABEL: @scalar_i16_shl_and_negC_eq(
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2019-06-25 08:09:10 +08:00
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; CHECK-NEXT: [[SHL:%.*]] = shl i16 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = icmp ult i16 [[SHL]], 128
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[InstCombine] Add tests to show missing fold opportunity for "icmp and shift" (nfc).
Summary:
For icmp pred (and (sh X, Y), C), 0
When C is signbit, expect to fold (X << Y) & signbit ==/!= 0 into (X << Y) >=/< 0,
rather than (X & (signbit >> Y)) != 0.
When C+1 is power of 2, expect to fold (X << Y) & ~C ==/!= 0 into (X << Y) </>= C+1,
rather than (X & (~C >> Y)) == 0.
For icmp pred (and X, (sh signbit, Y)), 0
Expect to fold (X & (signbit l>> Y)) ==/!= 0 into (X << Y) >=/< 0
Expect to fold (X & (signbit << Y)) ==/!= 0 into (X l>> Y) >=/< 0
Reviewers: lebedev.ri, efriedma, spatel, craig.topper
Reviewed By: lebedev.ri
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63025
llvm-svn: 363479
2019-06-15 08:33:41 +08:00
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; CHECK-NEXT: ret i1 [[R]]
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;
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%shl = shl i16 %x, %y
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%and = and i16 %shl, 65408 ; ~127
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%r = icmp eq i16 %and, 0
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ret i1 %r
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}
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define i1 @scalar_i32_shl_and_negC_eq(i32 %x, i32 %y) {
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; CHECK-LABEL: @scalar_i32_shl_and_negC_eq(
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2019-06-25 08:09:10 +08:00
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; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = icmp ult i32 [[SHL]], 262144
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[InstCombine] Add tests to show missing fold opportunity for "icmp and shift" (nfc).
Summary:
For icmp pred (and (sh X, Y), C), 0
When C is signbit, expect to fold (X << Y) & signbit ==/!= 0 into (X << Y) >=/< 0,
rather than (X & (signbit >> Y)) != 0.
When C+1 is power of 2, expect to fold (X << Y) & ~C ==/!= 0 into (X << Y) </>= C+1,
rather than (X & (~C >> Y)) == 0.
For icmp pred (and X, (sh signbit, Y)), 0
Expect to fold (X & (signbit l>> Y)) ==/!= 0 into (X << Y) >=/< 0
Expect to fold (X & (signbit << Y)) ==/!= 0 into (X l>> Y) >=/< 0
Reviewers: lebedev.ri, efriedma, spatel, craig.topper
Reviewed By: lebedev.ri
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63025
llvm-svn: 363479
2019-06-15 08:33:41 +08:00
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; CHECK-NEXT: ret i1 [[R]]
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;
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%shl = shl i32 %x, %y
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%and = and i32 %shl, 4294705152 ; ~262143
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%r = icmp eq i32 %and, 0
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ret i1 %r
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}
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define i1 @scalar_i64_shl_and_negC_eq(i64 %x, i64 %y) {
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; CHECK-LABEL: @scalar_i64_shl_and_negC_eq(
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2019-06-25 08:09:10 +08:00
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; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = icmp ult i64 [[SHL]], 8589934592
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[InstCombine] Add tests to show missing fold opportunity for "icmp and shift" (nfc).
Summary:
For icmp pred (and (sh X, Y), C), 0
When C is signbit, expect to fold (X << Y) & signbit ==/!= 0 into (X << Y) >=/< 0,
rather than (X & (signbit >> Y)) != 0.
When C+1 is power of 2, expect to fold (X << Y) & ~C ==/!= 0 into (X << Y) </>= C+1,
rather than (X & (~C >> Y)) == 0.
For icmp pred (and X, (sh signbit, Y)), 0
Expect to fold (X & (signbit l>> Y)) ==/!= 0 into (X << Y) >=/< 0
Expect to fold (X & (signbit << Y)) ==/!= 0 into (X l>> Y) >=/< 0
Reviewers: lebedev.ri, efriedma, spatel, craig.topper
Reviewed By: lebedev.ri
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63025
llvm-svn: 363479
2019-06-15 08:33:41 +08:00
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; CHECK-NEXT: ret i1 [[R]]
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;
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%shl = shl i64 %x, %y
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%and = and i64 %shl, 18446744065119617024 ; ~8589934591
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%r = icmp eq i64 %and, 0
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ret i1 %r
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}
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define i1 @scalar_i32_shl_and_negC_ne(i32 %x, i32 %y) {
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; CHECK-LABEL: @scalar_i32_shl_and_negC_ne(
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2019-06-25 08:09:10 +08:00
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; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = icmp ugt i32 [[SHL]], 262143
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[InstCombine] Add tests to show missing fold opportunity for "icmp and shift" (nfc).
Summary:
For icmp pred (and (sh X, Y), C), 0
When C is signbit, expect to fold (X << Y) & signbit ==/!= 0 into (X << Y) >=/< 0,
rather than (X & (signbit >> Y)) != 0.
When C+1 is power of 2, expect to fold (X << Y) & ~C ==/!= 0 into (X << Y) </>= C+1,
rather than (X & (~C >> Y)) == 0.
For icmp pred (and X, (sh signbit, Y)), 0
Expect to fold (X & (signbit l>> Y)) ==/!= 0 into (X << Y) >=/< 0
Expect to fold (X & (signbit << Y)) ==/!= 0 into (X l>> Y) >=/< 0
Reviewers: lebedev.ri, efriedma, spatel, craig.topper
Reviewed By: lebedev.ri
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63025
llvm-svn: 363479
2019-06-15 08:33:41 +08:00
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; CHECK-NEXT: ret i1 [[R]]
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;
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%shl = shl i32 %x, %y
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%and = and i32 %shl, 4294705152 ; ~262143
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%r = icmp ne i32 %and, 0 ; check 'ne' predicate
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ret i1 %r
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}
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; Vector tests
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define <4 x i1> @vec_4xi32_shl_and_negC_eq(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: @vec_4xi32_shl_and_negC_eq(
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2019-06-25 08:09:10 +08:00
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; CHECK-NEXT: [[SHL:%.*]] = shl <4 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = icmp ult <4 x i32> [[SHL]], <i32 8, i32 8, i32 8, i32 8>
|
[InstCombine] Add tests to show missing fold opportunity for "icmp and shift" (nfc).
Summary:
For icmp pred (and (sh X, Y), C), 0
When C is signbit, expect to fold (X << Y) & signbit ==/!= 0 into (X << Y) >=/< 0,
rather than (X & (signbit >> Y)) != 0.
When C+1 is power of 2, expect to fold (X << Y) & ~C ==/!= 0 into (X << Y) </>= C+1,
rather than (X & (~C >> Y)) == 0.
For icmp pred (and X, (sh signbit, Y)), 0
Expect to fold (X & (signbit l>> Y)) ==/!= 0 into (X << Y) >=/< 0
Expect to fold (X & (signbit << Y)) ==/!= 0 into (X l>> Y) >=/< 0
Reviewers: lebedev.ri, efriedma, spatel, craig.topper
Reviewed By: lebedev.ri
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63025
llvm-svn: 363479
2019-06-15 08:33:41 +08:00
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; CHECK-NEXT: ret <4 x i1> [[R]]
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;
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%shl = shl <4 x i32> %x, %y
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%and = and <4 x i32> %shl, <i32 4294967288, i32 4294967288, i32 4294967288, i32 4294967288> ; ~7
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%r = icmp eq <4 x i32> %and, <i32 0, i32 0, i32 0, i32 0>
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ret <4 x i1> %r
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}
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define <4 x i1> @vec_shl_and_negC_eq_undef1(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: @vec_shl_and_negC_eq_undef1(
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; CHECK-NEXT: [[SHL:%.*]] = shl <4 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHL]], <i32 -8, i32 undef, i32 -8, i32 -8>
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; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i32> [[AND]], zeroinitializer
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; CHECK-NEXT: ret <4 x i1> [[R]]
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;
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%shl = shl <4 x i32> %x, %y
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%and = and <4 x i32> %shl, <i32 4294967288, i32 undef, i32 4294967288, i32 4294967288> ; ~7
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%r = icmp eq <4 x i32> %and, <i32 0, i32 0, i32 0, i32 0>
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ret <4 x i1> %r
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}
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define <4 x i1> @vec_shl_and_negC_eq_undef2(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: @vec_shl_and_negC_eq_undef2(
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; CHECK-NEXT: [[SHL:%.*]] = shl <4 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHL]], <i32 -8, i32 -8, i32 -8, i32 -8>
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; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i32> [[AND]], <i32 0, i32 0, i32 0, i32 undef>
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; CHECK-NEXT: ret <4 x i1> [[R]]
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;
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%shl = shl <4 x i32> %x, %y
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%and = and <4 x i32> %shl, <i32 4294967288, i32 4294967288, i32 4294967288, i32 4294967288> ; ~7
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%r = icmp eq <4 x i32> %and, <i32 0, i32 0, i32 0, i32 undef>
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ret <4 x i1> %r
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}
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define <4 x i1> @vec_shl_and_negC_eq_undef3(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: @vec_shl_and_negC_eq_undef3(
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; CHECK-NEXT: [[SHL:%.*]] = shl <4 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHL]], <i32 -8, i32 -8, i32 undef, i32 -8>
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; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i32> [[AND]], <i32 0, i32 0, i32 0, i32 undef>
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; CHECK-NEXT: ret <4 x i1> [[R]]
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;
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%shl = shl <4 x i32> %x, %y
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%and = and <4 x i32> %shl, <i32 4294967288, i32 4294967288, i32 undef, i32 4294967288> ; ~7
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%r = icmp eq <4 x i32> %and, <i32 0, i32 0, i32 0, i32 undef>
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ret <4 x i1> %r
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}
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; Extra use
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; Fold happened
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define i1 @scalar_shl_and_negC_eq_extra_use_shl(i32 %x, i32 %y, i32 %z, i32* %p) {
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; CHECK-LABEL: @scalar_shl_and_negC_eq_extra_use_shl(
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; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[SHL]], [[Z:%.*]]
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; CHECK-NEXT: store i32 [[XOR]], i32* [[P:%.*]], align 4
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; CHECK-NEXT: [[R:%.*]] = icmp ult i32 [[SHL]], 8
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; CHECK-NEXT: ret i1 [[R]]
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;
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%shl = shl i32 %x, %y
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%xor = xor i32 %shl, %z ; extra use of shl
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store i32 %xor, i32* %p
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%and = and i32 %shl, 4294967288 ; ~7
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%r = icmp eq i32 %and, 0
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ret i1 %r
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}
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; Not fold
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define i1 @scalar_shl_and_negC_eq_extra_use_and(i32 %x, i32 %y, i32 %z, i32* %p) {
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; CHECK-LABEL: @scalar_shl_and_negC_eq_extra_use_and(
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; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHL]], -8
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; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[AND]], [[Z:%.*]]
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; CHECK-NEXT: store i32 [[MUL]], i32* [[P:%.*]], align 4
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; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[AND]], 0
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; CHECK-NEXT: ret i1 [[R]]
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|
;
|
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%shl = shl i32 %x, %y
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%and = and i32 %shl, 4294967288 ; ~7
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%mul = mul i32 %and, %z ; extra use of and
|
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|
store i32 %mul, i32* %p
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%r = icmp eq i32 %and, 0
|
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|
ret i1 %r
|
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|
|
}
|
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|
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|
|
; Not fold
|
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|
define i1 @scalar_shl_and_negC_eq_extra_use_shl_and(i32 %x, i32 %y, i32 %z, i32* %p, i32* %q) {
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|
|
; CHECK-LABEL: @scalar_shl_and_negC_eq_extra_use_shl_and(
|
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; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]]
|
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|
; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHL]], -8
|
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|
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; CHECK-NEXT: store i32 [[AND]], i32* [[P:%.*]], align 4
|
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|
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; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SHL]], [[Z:%.*]]
|
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|
; CHECK-NEXT: store i32 [[ADD]], i32* [[Q:%.*]], align 4
|
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|
|
; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[AND]], 0
|
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|
|
; CHECK-NEXT: ret i1 [[R]]
|
|
|
|
;
|
|
|
|
%shl = shl i32 %x, %y
|
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|
|
%and = and i32 %shl, 4294967288 ; ~7
|
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|
|
store i32 %and, i32* %p ; extra use of and
|
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|
%add = add i32 %shl, %z ; extra use of shl
|
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|
store i32 %add, i32* %q
|
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|
%r = icmp eq i32 %and, 0
|
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|
|
ret i1 %r
|
|
|
|
}
|
|
|
|
|
|
|
|
; Negative tests
|
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|
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|
|
; X is constant
|
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|
define i1 @scalar_i32_shl_and_negC_eq_X_is_constant1(i32 %y) {
|
|
|
|
; CHECK-LABEL: @scalar_i32_shl_and_negC_eq_X_is_constant1(
|
|
|
|
; CHECK-NEXT: [[SHL:%.*]] = shl i32 12345, [[Y:%.*]]
|
|
|
|
; CHECK-NEXT: [[R:%.*]] = icmp ult i32 [[SHL]], 8
|
|
|
|
; CHECK-NEXT: ret i1 [[R]]
|
|
|
|
;
|
|
|
|
%shl = shl i32 12345, %y
|
|
|
|
%and = and i32 %shl, 4294967288 ; ~7
|
|
|
|
%r = icmp eq i32 %and, 0
|
|
|
|
ret i1 %r
|
|
|
|
}
|
|
|
|
|
|
|
|
define i1 @scalar_i32_shl_and_negC_eq_X_is_constant2(i32 %y) {
|
|
|
|
; CHECK-LABEL: @scalar_i32_shl_and_negC_eq_X_is_constant2(
|
|
|
|
; CHECK-NEXT: [[R:%.*]] = icmp ult i32 [[Y:%.*]], 3
|
|
|
|
; CHECK-NEXT: ret i1 [[R]]
|
|
|
|
;
|
|
|
|
%shl = shl i32 1, %y
|
|
|
|
%and = and i32 %shl, 4294967288 ; ~7
|
|
|
|
%r = icmp eq i32 %and, 0
|
|
|
|
ret i1 %r
|
|
|
|
}
|
|
|
|
|
|
|
|
; Check 'slt' predicate
|
|
|
|
|
|
|
|
define i1 @scalar_i32_shl_and_negC_slt(i32 %x, i32 %y) {
|
|
|
|
; CHECK-LABEL: @scalar_i32_shl_and_negC_slt(
|
|
|
|
; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]]
|
|
|
|
; CHECK-NEXT: [[R:%.*]] = icmp slt i32 [[SHL]], 0
|
|
|
|
; CHECK-NEXT: ret i1 [[R]]
|
|
|
|
;
|
|
|
|
%shl = shl i32 %x, %y
|
|
|
|
%and = and i32 %shl, 4294967288 ; ~7
|
|
|
|
%r = icmp slt i32 %and, 0
|
|
|
|
ret i1 %r
|
|
|
|
}
|
|
|
|
|
|
|
|
; Compare with nonzero
|
|
|
|
|
|
|
|
define i1 @scalar_i32_shl_and_negC_eq_nonzero(i32 %x, i32 %y) {
|
|
|
|
; CHECK-LABEL: @scalar_i32_shl_and_negC_eq_nonzero(
|
|
|
|
; CHECK-NEXT: ret i1 false
|
|
|
|
;
|
|
|
|
%shl = shl i32 %x, %y
|
|
|
|
%and = and i32 %shl, 4294967288 ; ~7
|
|
|
|
%r = icmp eq i32 %and, 1 ; should be comparing with 0
|
|
|
|
ret i1 %r
|
|
|
|
}
|