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llvm-project/llvm/test/CodeGen/PowerPC/swaps-le-7.ll

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Adding -verify-machineinstrs option to PowerPC tests Currently we have a number of tests that fail with -verify-machineinstrs. To detect this cases earlier we add the option to the testcases with the exception of tests that will currently fail with this option. PR 27456 keeps track of this failures. No code review, as discussed with Hal Finkel. llvm-svn: 277624
2016-08-04 02:17:35 +08:00
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -O3 < %s | FileCheck %s
Ensure all uses of permute instructions feed vector stores There is a problem in VSXSwapRemoval where it is incorrectly removing permute instructions. In this case, the permute is feeding both a vector store and also a non-store instruction. In this case, the permute cannot be removed. The fix is to simply look at all the uses of the vector register defined by the permute and ensure that all the uses are vector store instructions. This problem was reported in PR 27735 (https://llvm.org/bugs/show_bug.cgi?id=27735). Test case based on the original problem reported. Phabricator Review: http://reviews.llvm.org/D21802 llvm-svn: 274645
2016-07-07 02:03:52 +08:00
;
; This is a regression test based on https://llvm.org/bugs/show_bug.cgi?id=27735
;
@G1 = global <2 x double> <double 2.0, double -10.0>
@G2 = global <2 x double> <double 3.0, double 4.0>
@G3 = global <2 x double> <double 5.0, double 6.0>
@G4 = global <2 x double> <double 7.0, double 8.0>
; CHECK-LABEL: @zg
[PowerPC] Exploit single instruction load-and-splat for word and doubleword We currently produce a load, followed by (possibly a move for integers and) a splat as separate instructions. VSX has always had a splatting load for doublewords, but as of Power9, we have it for words as well. This patch just exploits these instructions. Differential revision: https://reviews.llvm.org/D63624 llvm-svn: 372139
2019-09-18 00:45:20 +08:00
; CHECK: lxvdsx
; CHECK-NEXT: lxvdsx
Ensure all uses of permute instructions feed vector stores There is a problem in VSXSwapRemoval where it is incorrectly removing permute instructions. In this case, the permute is feeding both a vector store and also a non-store instruction. In this case, the permute cannot be removed. The fix is to simply look at all the uses of the vector register defined by the permute and ensure that all the uses are vector store instructions. This problem was reported in PR 27735 (https://llvm.org/bugs/show_bug.cgi?id=27735). Test case based on the original problem reported. Phabricator Review: http://reviews.llvm.org/D21802 llvm-svn: 274645
2016-07-07 02:03:52 +08:00
; CHECK-NEXT: xvmuldp
[PowerPC] Replace the Post RA List Scheduler with the Machine Scheduler We want to run the Machine Scheduler instead of the List Scheduler after RA. Checked with a performance run on a Power 9 machine with SPEC 2006 and while some benchmarks improved and others degraded the geomean was slightly improved with the Machine Scheduler. Differential Revision: https://reviews.llvm.org/D45265 llvm-svn: 336295
2018-07-05 02:54:25 +08:00
; CHECK-DAG: xvmuldp
; CHECK-DAG: xvsubdp
; CHECK-DAG: xvadddp
; CHECK-DAG: xxswapd
; CHECK-DAG: xxpermdi
; CHECK-DAG: xvsubdp
; CHECK: xxswapd
Ensure all uses of permute instructions feed vector stores There is a problem in VSXSwapRemoval where it is incorrectly removing permute instructions. In this case, the permute is feeding both a vector store and also a non-store instruction. In this case, the permute cannot be removed. The fix is to simply look at all the uses of the vector register defined by the permute and ensure that all the uses are vector store instructions. This problem was reported in PR 27735 (https://llvm.org/bugs/show_bug.cgi?id=27735). Test case based on the original problem reported. Phabricator Review: http://reviews.llvm.org/D21802 llvm-svn: 274645
2016-07-07 02:03:52 +08:00
; CHECK-NEXT: stxvd2x
[PowerPC] Replace the Post RA List Scheduler with the Machine Scheduler We want to run the Machine Scheduler instead of the List Scheduler after RA. Checked with a performance run on a Power 9 machine with SPEC 2006 and while some benchmarks improved and others degraded the geomean was slightly improved with the Machine Scheduler. Differential Revision: https://reviews.llvm.org/D45265 llvm-svn: 336295
2018-07-05 02:54:25 +08:00
; CHECK: blr
Ensure all uses of permute instructions feed vector stores There is a problem in VSXSwapRemoval where it is incorrectly removing permute instructions. In this case, the permute is feeding both a vector store and also a non-store instruction. In this case, the permute cannot be removed. The fix is to simply look at all the uses of the vector register defined by the permute and ensure that all the uses are vector store instructions. This problem was reported in PR 27735 (https://llvm.org/bugs/show_bug.cgi?id=27735). Test case based on the original problem reported. Phabricator Review: http://reviews.llvm.org/D21802 llvm-svn: 274645
2016-07-07 02:03:52 +08:00
; Function Attrs: noinline
define void @zg(i8* %.G0011_640.0, i8* %.G0012_642.0, <2 x double>* %JJ, <2 x double>* %.ka0000_391, double %.unpack, double %.unpack66) #0 {
L.JA291:
%Z.L.JA291.2 = load <2 x double>, <2 x double>* %.ka0000_391, align 16
store <2 x double> %Z.L.JA291.2, <2 x double>* %JJ, align 8
%Z.L.JA291.3 = bitcast i8* %.G0012_642.0 to <2 x double>*
%Z.L.JA291.4 = load <2 x double>, <2 x double>* %Z.L.JA291.3, align 1
%.elt136 = bitcast i8* %.G0011_640.0 to double*
%.unpack137 = load double, double* %.elt136, align 1
%.elt138 = getelementptr inbounds i8, i8* %.G0011_640.0, i64 8
%Z.L.JA291.5 = bitcast i8* %.elt138 to double*
%.unpack139 = load double, double* %Z.L.JA291.5, align 1
%Z.L.JA291.6 = insertelement <2 x double> undef, double %.unpack137, i32 0
%Z.L.JA291.7 = insertelement <2 x double> %Z.L.JA291.6, double %.unpack137, i32 1
%Z.L.JA291.8 = fmul <2 x double> %Z.L.JA291.2, %Z.L.JA291.7
%Z.L.JA291.9 = shufflevector <2 x double> %Z.L.JA291.2, <2 x double> undef, <2 x i32> <i32 1, i32 0>
%Z.L.JA291.10 = insertelement <2 x double> undef, double %.unpack139, i32 0
%Z.L.JA291.11 = insertelement <2 x double> %Z.L.JA291.10, double %.unpack139, i32 1
%Z.L.JA291.12 = fmul <2 x double> %Z.L.JA291.9, %Z.L.JA291.11
%Z.L.JA291.13 = fsub <2 x double> %Z.L.JA291.8, %Z.L.JA291.12
%Z.L.JA291.14 = fadd <2 x double> %Z.L.JA291.8, %Z.L.JA291.12
%Z.L.JA291.15 = shufflevector <2 x double> %Z.L.JA291.13, <2 x double> %Z.L.JA291.14, <2 x i32> <i32 0, i32 3>
%Z.L.JA291.16 = fsub <2 x double> %Z.L.JA291.4, %Z.L.JA291.15
%Z.L.JA291.17 = bitcast i8* %.G0012_642.0 to <2 x double>*
store <2 x double> %Z.L.JA291.16, <2 x double>* %Z.L.JA291.17, align 8
%.. = bitcast <2 x double>* %JJ to i32*
%.pre = load i32, i32* %.., align 32
ret void
}
[PPC] cleanup of mayLoad/mayStore flags and memory operands. 1) Explicitly sets mayLoad/mayStore property in the tablegen files on load/store instructions. 2) Updated the flags on a number of intrinsics indicating that they write memory. 3) Added SDNPMemOperand flags for some target dependent SDNodes so that they propagate their memory operand Review: https://reviews.llvm.org/D28818 llvm-svn: 293200
2017-01-27 02:59:15 +08:00
attributes #0 = { noinline }