2019-06-05 01:05:34 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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[PowerPC] Add a pattern for a runtime bit check
Following a suggestion by Sanjay, we should lower:
%shl = shl i32 1, %y
%and = and i32 %x, %shl
%cmp = icmp eq i32 %and, %shl
ret i1 %cmp
into:
subfic r4, r4, 32
rlwnm r3, r3, r4, 31, 31
Add this pattern and some associated patterns for the 64-bit case and the
not-equal case. Fixes PR27356.
llvm-svn: 280454
2016-09-02 10:34:44 +08:00
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; RUN: llc < %s | FileCheck %s
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target datalayout = "e-m:e-i64:64-n32:64"
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target triple = "powerpc64le-unknown-linux-gnu"
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define i1 @and_cmp_variable_power_of_two(i32 %x, i32 %y) {
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2019-06-05 01:05:34 +08:00
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; CHECK-LABEL: and_cmp_variable_power_of_two:
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; CHECK: # %bb.0:
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[Codegen] (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0 fold
Summary:
This was originally reported in D62818.
https://rise4fun.com/Alive/oPH
InstCombine does the opposite fold, in hope that `C l>>/<< Y` expression
will be hoisted out of a loop if `Y` is invariant and `X` is not.
But as it is seen from the diffs here, if it didn't get hoisted,
the produced assembly is almost universally worse.
Much like with my recent "hoist add/sub by/from const" patches,
we should get almost universal win if we hoist constant,
there is almost always an "and/test by imm" instruction,
but "shift of imm" not so much, so we may avoid having to
materialize the immediate, and thus need one less register.
And since we now shift not by constant, but by something else,
the live-range of that something else may reduce.
Special care needs to be applied not to disturb x86 `BT` / hexagon `tstbit`
instruction pattern. And to not get into endless combine loop.
Reviewers: RKSimon, efriedma, t.p.northover, craig.topper, spatel, arsenm
Reviewed By: spatel
Subscribers: hiraditya, MaskRay, wuzish, xbolva00, nikic, nemanjai, jvesely, wdng, nhaehnle, javed.absar, tpr, kristof.beyls, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62871
llvm-svn: 366955
2019-07-25 06:57:22 +08:00
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; CHECK-NEXT: srw 3, 3, 4
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2019-06-05 01:05:34 +08:00
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; CHECK-NEXT: blr
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[PowerPC] Add a pattern for a runtime bit check
Following a suggestion by Sanjay, we should lower:
%shl = shl i32 1, %y
%and = and i32 %x, %shl
%cmp = icmp eq i32 %and, %shl
ret i1 %cmp
into:
subfic r4, r4, 32
rlwnm r3, r3, r4, 31, 31
Add this pattern and some associated patterns for the 64-bit case and the
not-equal case. Fixes PR27356.
llvm-svn: 280454
2016-09-02 10:34:44 +08:00
|
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%shl = shl i32 1, %y
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%and = and i32 %x, %shl
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%cmp = icmp eq i32 %and, %shl
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ret i1 %cmp
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}
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define i1 @and_cmp_variable_power_of_two_64(i64 %x, i64 %y) {
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2019-06-05 01:05:34 +08:00
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; CHECK-LABEL: and_cmp_variable_power_of_two_64:
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; CHECK: # %bb.0:
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[Codegen] (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0 fold
Summary:
This was originally reported in D62818.
https://rise4fun.com/Alive/oPH
InstCombine does the opposite fold, in hope that `C l>>/<< Y` expression
will be hoisted out of a loop if `Y` is invariant and `X` is not.
But as it is seen from the diffs here, if it didn't get hoisted,
the produced assembly is almost universally worse.
Much like with my recent "hoist add/sub by/from const" patches,
we should get almost universal win if we hoist constant,
there is almost always an "and/test by imm" instruction,
but "shift of imm" not so much, so we may avoid having to
materialize the immediate, and thus need one less register.
And since we now shift not by constant, but by something else,
the live-range of that something else may reduce.
Special care needs to be applied not to disturb x86 `BT` / hexagon `tstbit`
instruction pattern. And to not get into endless combine loop.
Reviewers: RKSimon, efriedma, t.p.northover, craig.topper, spatel, arsenm
Reviewed By: spatel
Subscribers: hiraditya, MaskRay, wuzish, xbolva00, nikic, nemanjai, jvesely, wdng, nhaehnle, javed.absar, tpr, kristof.beyls, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62871
llvm-svn: 366955
2019-07-25 06:57:22 +08:00
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; CHECK-NEXT: srd 3, 3, 4
|
2019-06-05 01:05:34 +08:00
|
|
|
; CHECK-NEXT: blr
|
[PowerPC] Add a pattern for a runtime bit check
Following a suggestion by Sanjay, we should lower:
%shl = shl i32 1, %y
%and = and i32 %x, %shl
%cmp = icmp eq i32 %and, %shl
ret i1 %cmp
into:
subfic r4, r4, 32
rlwnm r3, r3, r4, 31, 31
Add this pattern and some associated patterns for the 64-bit case and the
not-equal case. Fixes PR27356.
llvm-svn: 280454
2016-09-02 10:34:44 +08:00
|
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|
%shl = shl i64 1, %y
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%and = and i64 %x, %shl
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%cmp = icmp eq i64 %and, %shl
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ret i1 %cmp
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}
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define i1 @and_ncmp_variable_power_of_two(i32 %x, i32 %y) {
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2019-06-05 01:05:34 +08:00
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; CHECK-LABEL: and_ncmp_variable_power_of_two:
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; CHECK: # %bb.0:
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[Codegen] (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0 fold
Summary:
This was originally reported in D62818.
https://rise4fun.com/Alive/oPH
InstCombine does the opposite fold, in hope that `C l>>/<< Y` expression
will be hoisted out of a loop if `Y` is invariant and `X` is not.
But as it is seen from the diffs here, if it didn't get hoisted,
the produced assembly is almost universally worse.
Much like with my recent "hoist add/sub by/from const" patches,
we should get almost universal win if we hoist constant,
there is almost always an "and/test by imm" instruction,
but "shift of imm" not so much, so we may avoid having to
materialize the immediate, and thus need one less register.
And since we now shift not by constant, but by something else,
the live-range of that something else may reduce.
Special care needs to be applied not to disturb x86 `BT` / hexagon `tstbit`
instruction pattern. And to not get into endless combine loop.
Reviewers: RKSimon, efriedma, t.p.northover, craig.topper, spatel, arsenm
Reviewed By: spatel
Subscribers: hiraditya, MaskRay, wuzish, xbolva00, nikic, nemanjai, jvesely, wdng, nhaehnle, javed.absar, tpr, kristof.beyls, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62871
llvm-svn: 366955
2019-07-25 06:57:22 +08:00
|
|
|
; CHECK-NEXT: srw 3, 3, 4
|
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|
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|
; CHECK-NEXT: xori 3, 3, 1
|
2019-06-05 01:05:34 +08:00
|
|
|
; CHECK-NEXT: blr
|
[PowerPC] Add a pattern for a runtime bit check
Following a suggestion by Sanjay, we should lower:
%shl = shl i32 1, %y
%and = and i32 %x, %shl
%cmp = icmp eq i32 %and, %shl
ret i1 %cmp
into:
subfic r4, r4, 32
rlwnm r3, r3, r4, 31, 31
Add this pattern and some associated patterns for the 64-bit case and the
not-equal case. Fixes PR27356.
llvm-svn: 280454
2016-09-02 10:34:44 +08:00
|
|
|
%shl = shl i32 1, %y
|
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|
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|
%and = and i32 %x, %shl
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%cmp = icmp ne i32 %and, %shl
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ret i1 %cmp
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}
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define i1 @and_ncmp_variable_power_of_two_64(i64 %x, i64 %y) {
|
2019-06-05 01:05:34 +08:00
|
|
|
; CHECK-LABEL: and_ncmp_variable_power_of_two_64:
|
|
|
|
|
; CHECK: # %bb.0:
|
[Codegen] (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0 fold
Summary:
This was originally reported in D62818.
https://rise4fun.com/Alive/oPH
InstCombine does the opposite fold, in hope that `C l>>/<< Y` expression
will be hoisted out of a loop if `Y` is invariant and `X` is not.
But as it is seen from the diffs here, if it didn't get hoisted,
the produced assembly is almost universally worse.
Much like with my recent "hoist add/sub by/from const" patches,
we should get almost universal win if we hoist constant,
there is almost always an "and/test by imm" instruction,
but "shift of imm" not so much, so we may avoid having to
materialize the immediate, and thus need one less register.
And since we now shift not by constant, but by something else,
the live-range of that something else may reduce.
Special care needs to be applied not to disturb x86 `BT` / hexagon `tstbit`
instruction pattern. And to not get into endless combine loop.
Reviewers: RKSimon, efriedma, t.p.northover, craig.topper, spatel, arsenm
Reviewed By: spatel
Subscribers: hiraditya, MaskRay, wuzish, xbolva00, nikic, nemanjai, jvesely, wdng, nhaehnle, javed.absar, tpr, kristof.beyls, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62871
llvm-svn: 366955
2019-07-25 06:57:22 +08:00
|
|
|
; CHECK-NEXT: srd 3, 3, 4
|
|
|
|
|
; CHECK-NEXT: xori 3, 3, 1
|
2019-06-05 01:05:34 +08:00
|
|
|
; CHECK-NEXT: blr
|
[PowerPC] Add a pattern for a runtime bit check
Following a suggestion by Sanjay, we should lower:
%shl = shl i32 1, %y
%and = and i32 %x, %shl
%cmp = icmp eq i32 %and, %shl
ret i1 %cmp
into:
subfic r4, r4, 32
rlwnm r3, r3, r4, 31, 31
Add this pattern and some associated patterns for the 64-bit case and the
not-equal case. Fixes PR27356.
llvm-svn: 280454
2016-09-02 10:34:44 +08:00
|
|
|
%shl = shl i64 1, %y
|
|
|
|
|
%and = and i64 %x, %shl
|
|
|
|
|
%cmp = icmp ne i64 %and, %shl
|
|
|
|
|
ret i1 %cmp
|
|
|
|
|
}
|