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llvm-project/llvm/test/CodeGen/PowerPC/scheduling-mem-dependency.ll

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[PowerPC] Implement the areMemAccessesTriviallyDisjoint hook After implemented this hook, we will model the memory dependency in the scheduling dependency graph more precise, and will have more opportunity to reorder the load/stores, as they didn't have the dependency at some condition Differential Revision: https://reviews.llvm.org/D63804 llvm-svn: 364886
2019-07-02 11:28:52 +08:00
; REQUIRES: asserts
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
[PowerPC] Clear the sideeffect bit for those instructions that didn't have the match pattern If the instruction have match pattern, llvm-tblgen will infer the sideeffect bit from the match pattern and it works well. If not, the tblgen will set it as true that hurt the scheduling. PowerPC has some instructions that didn't specify the match pattern(i.e. LXSD etc), which is manually selected post-ra according to the register pressure. We need to clear the sideeffect flag for these instructions. Differential Revision: https://reviews.llvm.org/D69232
2019-10-30 15:56:35 +08:00
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK-P9
[PowerPC] Implement the areMemAccessesTriviallyDisjoint hook After implemented this hook, we will model the memory dependency in the scheduling dependency graph more precise, and will have more opportunity to reorder the load/stores, as they didn't have the dependency at some condition Differential Revision: https://reviews.llvm.org/D63804 llvm-svn: 364886
2019-07-02 11:28:52 +08:00
define i64 @store_disjoint_memory(i64* nocapture %P, i64 %v) {
entry:
; CHECK: ********** MI Scheduling **********
; CHECK-LABEL: store_disjoint_memory:%bb.0
[PowerPC] Clear the sideeffect bit for those instructions that didn't have the match pattern If the instruction have match pattern, llvm-tblgen will infer the sideeffect bit from the match pattern and it works well. If not, the tblgen will set it as true that hurt the scheduling. PowerPC has some instructions that didn't specify the match pattern(i.e. LXSD etc), which is manually selected post-ra according to the register pressure. We need to clear the sideeffect flag for these instructions. Differential Revision: https://reviews.llvm.org/D69232
2019-10-30 15:56:35 +08:00
; CHECK:SU([[REG2:[0-9]+]]): STD renamable $x{{[0-9]+}}, 24, renamable $x[[REG5:[0-9]+]]
[PowerPC] Implement the areMemAccessesTriviallyDisjoint hook After implemented this hook, we will model the memory dependency in the scheduling dependency graph more precise, and will have more opportunity to reorder the load/stores, as they didn't have the dependency at some condition Differential Revision: https://reviews.llvm.org/D63804 llvm-svn: 364886
2019-07-02 11:28:52 +08:00
; CHECK-NOT: Successors:
[PowerPC] Clear the sideeffect bit for those instructions that didn't have the match pattern If the instruction have match pattern, llvm-tblgen will infer the sideeffect bit from the match pattern and it works well. If not, the tblgen will set it as true that hurt the scheduling. PowerPC has some instructions that didn't specify the match pattern(i.e. LXSD etc), which is manually selected post-ra according to the register pressure. We need to clear the sideeffect flag for these instructions. Differential Revision: https://reviews.llvm.org/D69232
2019-10-30 15:56:35 +08:00
; CHECK-NOT: SU([[REG3]]): Ord Latency=0 Memory
; CHECK:SU([[REG3:[0-9]+]]): STD renamable $x{{[0-9]+}}, 16, renamable $x[[REG5]]
[PowerPC] Implement the areMemAccessesTriviallyDisjoint hook After implemented this hook, we will model the memory dependency in the scheduling dependency graph more precise, and will have more opportunity to reorder the load/stores, as they didn't have the dependency at some condition Differential Revision: https://reviews.llvm.org/D63804 llvm-svn: 364886
2019-07-02 11:28:52 +08:00
; CHECK: Predecessors:
[PowerPC] Clear the sideeffect bit for those instructions that didn't have the match pattern If the instruction have match pattern, llvm-tblgen will infer the sideeffect bit from the match pattern and it works well. If not, the tblgen will set it as true that hurt the scheduling. PowerPC has some instructions that didn't specify the match pattern(i.e. LXSD etc), which is manually selected post-ra according to the register pressure. We need to clear the sideeffect flag for these instructions. Differential Revision: https://reviews.llvm.org/D69232
2019-10-30 15:56:35 +08:00
; CHECK-NOT: SU([[REG2]]): Ord Latency=0 Memory
[PowerPC] Implement the areMemAccessesTriviallyDisjoint hook After implemented this hook, we will model the memory dependency in the scheduling dependency graph more precise, and will have more opportunity to reorder the load/stores, as they didn't have the dependency at some condition Differential Revision: https://reviews.llvm.org/D63804 llvm-svn: 364886
2019-07-02 11:28:52 +08:00
%arrayidx = getelementptr inbounds i64, i64* %P, i64 3
store i64 %v, i64* %arrayidx
%arrayidx1 = getelementptr inbounds i64, i64* %P, i64 2
store i64 %v, i64* %arrayidx1
ret i64 %v
}
[PowerPC] Clear the sideeffect bit for those instructions that didn't have the match pattern If the instruction have match pattern, llvm-tblgen will infer the sideeffect bit from the match pattern and it works well. If not, the tblgen will set it as true that hurt the scheduling. PowerPC has some instructions that didn't specify the match pattern(i.e. LXSD etc), which is manually selected post-ra according to the register pressure. We need to clear the sideeffect flag for these instructions. Differential Revision: https://reviews.llvm.org/D69232
2019-10-30 15:56:35 +08:00
; LXSD is an instruction that can be modeled.
@gd = external local_unnamed_addr global [500 x double], align 8
@gf = external local_unnamed_addr global [500 x float], align 4
define double @test_lxsd_no_barrier(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i, double %j, double %k, double %l, double %m) {
entry:
%0 = load double, double* getelementptr inbounds ([500 x double], [500 x double]* @gd, i64 0, i64 10), align 8
%1 = load double, double* getelementptr inbounds ([500 x double], [500 x double]* @gd, i64 0, i64 17), align 8
%2 = load double, double* getelementptr inbounds ([500 x double], [500 x double]* @gd, i64 0, i64 87), align 8
%3 = load double, double* getelementptr inbounds ([500 x double], [500 x double]* @gd, i64 0, i64 97), align 8
%4 = load double, double* getelementptr inbounds ([500 x double], [500 x double]* @gd, i64 0, i64 77), align 8
%add = fadd double %a, %b
%add1 = fadd double %add, %c
%add2 = fadd double %add1, %d
%add3 = fadd double %add2, %e
%add4 = fadd double %add3, %f
%add5 = fadd double %add4, %g
%add6 = fadd double %add5, %h
%add7 = fadd double %add6, %i
%add8 = fadd double %add7, %j
%add9 = fadd double %add8, %k
%add10 = fadd double %add9, %l
%add11 = fadd double %add10, %m
%add12 = fadd double %add11, %0
%add13 = fadd double %add12, %1
%add14 = fadd double %add13, %2
%add15 = fadd double %add14, %3
%add16 = fadd double %add15, %4
ret double %add16
; CHECK-P9: ********** MI Scheduling **********
; CHECK-P9-LABEL: test_lxsd_no_barrier:%bb.0 entry
; CHECK-P9-NOT:Global memory object and new barrier chain: SU({{[0-9]+}}).
; CHECK-P9:SU({{[0-9]+}}): renamable $vf{{[0-9]+}} = LXSD 136
; CHECK-P9:SU({{[0-9]+}}): renamable $vf{{[0-9]+}} = LXSD 696
; CHECK-P9:SU({{[0-9]+}}): renamable $vf{{[0-9]+}} = LXSD 776
; CHECK-P9:SU({{[0-9]+}}): renamable $vf{{[0-9]+}} = LXSD 616
}