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llvm-project/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll

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[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
[Power9]Legalize and emit code for truncate and convert QP to DW Legalize and emit code for: * xscvqpsdz : VSX Scalar truncate & Convert Quad-Precision to Signed Dword * xscvqpudz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Dword Differential Revision: https://reviews.llvm.org/D45553 llvm-svn: 331787
2018-05-09 02:23:31 +08:00
; RUN: -verify-machineinstrs -enable-ppc-quad-precision \
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
[Power9]Legalize and emit code for truncate and convert QP to DW Legalize and emit code for: * xscvqpsdz : VSX Scalar truncate & Convert Quad-Precision to Signed Dword * xscvqpudz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Dword Differential Revision: https://reviews.llvm.org/D45553 llvm-svn: 331787
2018-05-09 02:23:31 +08:00
@f128Array = global [4 x fp128] [fp128 0xL00000000000000004004C00000000000,
fp128 0xLF000000000000000400808AB851EB851,
fp128 0xL5000000000000000400E0C26324C8366,
fp128 0xL8000000000000000400A24E2E147AE14],
align 16
; Function Attrs: norecurse nounwind readonly
define i64 @qpConv2sdw(fp128* nocapture readonly %a) {
entry:
%0 = load fp128, fp128* %a, align 16
%conv = fptosi fp128 %0 to i64
ret i64 %conv
; CHECK-LABEL: qpConv2sdw
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK: lxv v[[REG:[0-9]+]], 0(r3)
; CHECK-NEXT: xscvqpsdz v[[CONV:[0-9]+]], v[[REG]]
; CHECK-NEXT: mfvsrd r3, v[[CONV]]
[Power9]Legalize and emit code for truncate and convert QP to DW Legalize and emit code for: * xscvqpsdz : VSX Scalar truncate & Convert Quad-Precision to Signed Dword * xscvqpudz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Dword Differential Revision: https://reviews.llvm.org/D45553 llvm-svn: 331787
2018-05-09 02:23:31 +08:00
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @qpConv2sdw_02(i64* nocapture %res) local_unnamed_addr #1 {
entry:
%0 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array, i64 0,
i64 2), align 16
%conv = fptosi fp128 %0 to i64
store i64 %conv, i64* %res, align 8
ret void
; CHECK-LABEL: qpConv2sdw_02
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0@toc@ha
; CHECK: ld r[[REG0]], .LC0@toc@l(r[[REG0]])
; CHECK: lxv v[[REG:[0-9]+]], 32(r[[REG0]])
; CHECK-NEXT: xscvqpsdz v[[CONV:[0-9]+]], v[[REG]]
; CHECK-NEXT: stxsd v[[CONV]], 0(r3)
[Power9]Legalize and emit code for truncate and convert QP to DW Legalize and emit code for: * xscvqpsdz : VSX Scalar truncate & Convert Quad-Precision to Signed Dword * xscvqpudz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Dword Differential Revision: https://reviews.llvm.org/D45553 llvm-svn: 331787
2018-05-09 02:23:31 +08:00
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readonly
define i64 @qpConv2sdw_03(fp128* nocapture readonly %a) {
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array, i64 0,
i64 1), align 16
%add = fadd fp128 %0, %1
%conv = fptosi fp128 %add to i64
ret i64 %conv
; CHECK-LABEL: qpConv2sdw_03
[Power9] Enable the Out-of-Order scheduling model for P9 hw When switched to the MI scheduler for P9, the hardware is modeled as out of order. However, inside the MI Scheduler algorithm, we still use the in-order scheduling model as the MicroOpBufferSize isn't set. The MI scheduler take it as the hw cannot buffer the op. So, only when all the available instructions issued, the pending instruction could be scheduled. That is not true for our P9 hw in fact. This patch is trying to enable the Out-of-Order scheduling model. The buffer size 44 is picked from the P9 hw spec, and the perf test indicate that, its value won't hurt the cpu2017. With this patch, there are 3 specs improved over 3% and 1 spec deg over 3%. The detail is as follows: x264_r: +6.95% cactuBSSN_r: +6.94% lbm_r: +4.11% xz_r: -3.85% And the GEOMEAN for all the C/C++ spec in spec2017 is about 0.18% improved. Reviewer: Nemanjai Differential Revision: https://reviews.llvm.org/D55810 llvm-svn: 350285
2019-01-03 13:04:18 +08:00
; CHECK: lxv v[[REG:[0-9]+]], 0(r3)
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0@toc@ha
[Power9] Enable the Out-of-Order scheduling model for P9 hw When switched to the MI scheduler for P9, the hardware is modeled as out of order. However, inside the MI Scheduler algorithm, we still use the in-order scheduling model as the MicroOpBufferSize isn't set. The MI scheduler take it as the hw cannot buffer the op. So, only when all the available instructions issued, the pending instruction could be scheduled. That is not true for our P9 hw in fact. This patch is trying to enable the Out-of-Order scheduling model. The buffer size 44 is picked from the P9 hw spec, and the perf test indicate that, its value won't hurt the cpu2017. With this patch, there are 3 specs improved over 3% and 1 spec deg over 3%. The detail is as follows: x264_r: +6.95% cactuBSSN_r: +6.94% lbm_r: +4.11% xz_r: -3.85% And the GEOMEAN for all the C/C++ spec in spec2017 is about 0.18% improved. Reviewer: Nemanjai Differential Revision: https://reviews.llvm.org/D55810 llvm-svn: 350285
2019-01-03 13:04:18 +08:00
; CHECK: ld r[[REG0]], .LC0@toc@l(r[[REG0]])
; CHECK: lxv v[[REG1:[0-9]+]], 16(r[[REG0]])
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK: xsaddqp v[[REG]], v[[REG]], v[[REG1]]
; CHECK-NEXT: xscvqpsdz v[[CONV:[0-9]+]], v[[REG]]
; CHECK-NEXT: mfvsrd r3, v[[CONV]]
[Power9]Legalize and emit code for truncate and convert QP to DW Legalize and emit code for: * xscvqpsdz : VSX Scalar truncate & Convert Quad-Precision to Signed Dword * xscvqpudz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Dword Differential Revision: https://reviews.llvm.org/D45553 llvm-svn: 331787
2018-05-09 02:23:31 +08:00
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @qpConv2sdw_04(fp128* nocapture readonly %a,
fp128* nocapture readonly %b, i64* nocapture %res) {
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16
%add = fadd fp128 %0, %1
%conv = fptosi fp128 %add to i64
store i64 %conv, i64* %res, align 8
ret void
; CHECK-LABEL: qpConv2sdw_04
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK-DAG: lxv v[[REG1:[0-9]+]], 0(r4)
; CHECK-DAG: lxv v[[REG:[0-9]+]], 0(r3)
; CHECK: xsaddqp v[[REG]], v[[REG]], v[[REG1]]
; CHECK-NEXT: xscvqpsdz v[[CONV:[0-9]+]], v[[REG]]
; CHECK-NEXT: stxsd v[[CONV]], 0(r5)
[Power9]Legalize and emit code for truncate and convert QP to DW Legalize and emit code for: * xscvqpsdz : VSX Scalar truncate & Convert Quad-Precision to Signed Dword * xscvqpudz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Dword Differential Revision: https://reviews.llvm.org/D45553 llvm-svn: 331787
2018-05-09 02:23:31 +08:00
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @qpConv2sdw_testXForm(i64* nocapture %res, i32 signext %idx) {
entry:
%0 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array,
i64 0, i64 2), align 16
%conv = fptosi fp128 %0 to i64
%idxprom = sext i32 %idx to i64
%arrayidx = getelementptr inbounds i64, i64* %res, i64 %idxprom
store i64 %conv, i64* %arrayidx, align 8
ret void
; CHECK-LABEL: qpConv2sdw_testXForm
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK: xscvqpsdz v[[CONV:[0-9]+]],
[Power9] Enable the Out-of-Order scheduling model for P9 hw When switched to the MI scheduler for P9, the hardware is modeled as out of order. However, inside the MI Scheduler algorithm, we still use the in-order scheduling model as the MicroOpBufferSize isn't set. The MI scheduler take it as the hw cannot buffer the op. So, only when all the available instructions issued, the pending instruction could be scheduled. That is not true for our P9 hw in fact. This patch is trying to enable the Out-of-Order scheduling model. The buffer size 44 is picked from the P9 hw spec, and the perf test indicate that, its value won't hurt the cpu2017. With this patch, there are 3 specs improved over 3% and 1 spec deg over 3%. The detail is as follows: x264_r: +6.95% cactuBSSN_r: +6.94% lbm_r: +4.11% xz_r: -3.85% And the GEOMEAN for all the C/C++ spec in spec2017 is about 0.18% improved. Reviewer: Nemanjai Differential Revision: https://reviews.llvm.org/D55810 llvm-svn: 350285
2019-01-03 13:04:18 +08:00
; CHECK: stxsdx v[[CONV]], r3, r4
[Power9]Legalize and emit code for truncate and convert QP to DW Legalize and emit code for: * xscvqpsdz : VSX Scalar truncate & Convert Quad-Precision to Signed Dword * xscvqpudz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Dword Differential Revision: https://reviews.llvm.org/D45553 llvm-svn: 331787
2018-05-09 02:23:31 +08:00
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readonly
define i64 @qpConv2udw(fp128* nocapture readonly %a) {
entry:
%0 = load fp128, fp128* %a, align 16
%conv = fptoui fp128 %0 to i64
ret i64 %conv
; CHECK-LABEL: qpConv2udw
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK: lxv v[[REG:[0-9]+]], 0(r3)
; CHECK-NEXT: xscvqpudz v[[CONV:[0-9]+]], v[[REG]]
; CHECK-NEXT: mfvsrd r3, v[[CONV]]
[Power9]Legalize and emit code for truncate and convert QP to DW Legalize and emit code for: * xscvqpsdz : VSX Scalar truncate & Convert Quad-Precision to Signed Dword * xscvqpudz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Dword Differential Revision: https://reviews.llvm.org/D45553 llvm-svn: 331787
2018-05-09 02:23:31 +08:00
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @qpConv2udw_02(i64* nocapture %res) {
entry:
%0 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array, i64 0,
i64 2), align 16
%conv = fptoui fp128 %0 to i64
store i64 %conv, i64* %res, align 8
ret void
; CHECK-LABEL: qpConv2udw_02
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0@toc@ha
; CHECK: ld r[[REG0]], .LC0@toc@l(r[[REG0]])
; CHECK: lxv v[[REG:[0-9]+]], 32(r[[REG0]])
; CHECK-NEXT: xscvqpudz v[[CONV:[0-9]+]], v[[REG]]
; CHECK-NEXT: stxsd v[[CONV]], 0(r3)
[Power9]Legalize and emit code for truncate and convert QP to DW Legalize and emit code for: * xscvqpsdz : VSX Scalar truncate & Convert Quad-Precision to Signed Dword * xscvqpudz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Dword Differential Revision: https://reviews.llvm.org/D45553 llvm-svn: 331787
2018-05-09 02:23:31 +08:00
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readonly
define i64 @qpConv2udw_03(fp128* nocapture readonly %a) {
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array, i64 0,
i64 1), align 16
%add = fadd fp128 %0, %1
%conv = fptoui fp128 %add to i64
ret i64 %conv
; CHECK-LABEL: qpConv2udw_03
[Power9] Enable the Out-of-Order scheduling model for P9 hw When switched to the MI scheduler for P9, the hardware is modeled as out of order. However, inside the MI Scheduler algorithm, we still use the in-order scheduling model as the MicroOpBufferSize isn't set. The MI scheduler take it as the hw cannot buffer the op. So, only when all the available instructions issued, the pending instruction could be scheduled. That is not true for our P9 hw in fact. This patch is trying to enable the Out-of-Order scheduling model. The buffer size 44 is picked from the P9 hw spec, and the perf test indicate that, its value won't hurt the cpu2017. With this patch, there are 3 specs improved over 3% and 1 spec deg over 3%. The detail is as follows: x264_r: +6.95% cactuBSSN_r: +6.94% lbm_r: +4.11% xz_r: -3.85% And the GEOMEAN for all the C/C++ spec in spec2017 is about 0.18% improved. Reviewer: Nemanjai Differential Revision: https://reviews.llvm.org/D55810 llvm-svn: 350285
2019-01-03 13:04:18 +08:00
; CHECK: lxv v[[REG:[0-9]+]], 0(r3)
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0@toc@ha
; CHECK-DAG: ld r[[REG0]], .LC0@toc@l(r[[REG0]])
; CHECK-DAG: lxv v[[REG1:[0-9]+]], 16(r[[REG0]])
; CHECK: xsaddqp v[[REG]], v[[REG]], v[[REG1]]
; CHECK-NEXT: xscvqpudz v[[CONV:[0-9]+]], v[[REG]]
; CHECK-NEXT: mfvsrd r3, v[[CONV]]
[Power9]Legalize and emit code for truncate and convert QP to DW Legalize and emit code for: * xscvqpsdz : VSX Scalar truncate & Convert Quad-Precision to Signed Dword * xscvqpudz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Dword Differential Revision: https://reviews.llvm.org/D45553 llvm-svn: 331787
2018-05-09 02:23:31 +08:00
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @qpConv2udw_04(fp128* nocapture readonly %a,
fp128* nocapture readonly %b, i64* nocapture %res) {
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16
%add = fadd fp128 %0, %1
%conv = fptoui fp128 %add to i64
store i64 %conv, i64* %res, align 8
ret void
; CHECK-LABEL: qpConv2udw_04
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK-DAG: lxv v[[REG1:[0-9]+]], 0(r4)
; CHECK-DAG: lxv v[[REG:[0-9]+]], 0(r3)
; CHECK: xsaddqp v[[REG]], v[[REG]], v[[REG1]]
; CHECK-NEXT: xscvqpudz v[[CONV:[0-9]+]], v[[REG]]
; CHECK-NEXT: stxsd v[[CONV]], 0(r5)
[Power9]Legalize and emit code for truncate and convert QP to DW Legalize and emit code for: * xscvqpsdz : VSX Scalar truncate & Convert Quad-Precision to Signed Dword * xscvqpudz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Dword Differential Revision: https://reviews.llvm.org/D45553 llvm-svn: 331787
2018-05-09 02:23:31 +08:00
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @qpConv2udw_testXForm(i64* nocapture %res, i32 signext %idx) {
entry:
%0 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array,
i64 0, i64 0), align 16
%conv = fptoui fp128 %0 to i64
%idxprom = sext i32 %idx to i64
%arrayidx = getelementptr inbounds i64, i64* %res, i64 %idxprom
store i64 %conv, i64* %arrayidx, align 8
ret void
; CHECK-LABEL: qpConv2udw_testXForm
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK: xscvqpudz v[[CONV:[0-9]+]],
[Power9] Enable the Out-of-Order scheduling model for P9 hw When switched to the MI scheduler for P9, the hardware is modeled as out of order. However, inside the MI Scheduler algorithm, we still use the in-order scheduling model as the MicroOpBufferSize isn't set. The MI scheduler take it as the hw cannot buffer the op. So, only when all the available instructions issued, the pending instruction could be scheduled. That is not true for our P9 hw in fact. This patch is trying to enable the Out-of-Order scheduling model. The buffer size 44 is picked from the P9 hw spec, and the perf test indicate that, its value won't hurt the cpu2017. With this patch, there are 3 specs improved over 3% and 1 spec deg over 3%. The detail is as follows: x264_r: +6.95% cactuBSSN_r: +6.94% lbm_r: +4.11% xz_r: -3.85% And the GEOMEAN for all the C/C++ spec in spec2017 is about 0.18% improved. Reviewer: Nemanjai Differential Revision: https://reviews.llvm.org/D55810 llvm-svn: 350285
2019-01-03 13:04:18 +08:00
; CHECK: stxsdx v[[CONV]], r3, r4
[Power9]Legalize and emit code for truncate and convert QP to DW Legalize and emit code for: * xscvqpsdz : VSX Scalar truncate & Convert Quad-Precision to Signed Dword * xscvqpudz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Dword Differential Revision: https://reviews.llvm.org/D45553 llvm-svn: 331787
2018-05-09 02:23:31 +08:00
; CHECK-NEXT: blr
}
[Power9]Legalize and emit code for truncate and convert Quad-Precision to Word Legalize and emit code for: * xscvqpswz : VSX Scalar truncate & Convert Quad-Precision to Signed Word * xscvqpuwz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Word Differential Revision: https://reviews.llvm.org/D45635 llvm-svn: 331790
2018-05-09 02:34:00 +08:00
; Function Attrs: norecurse nounwind readonly
define signext i32 @qpConv2sw(fp128* nocapture readonly %a) {
entry:
%0 = load fp128, fp128* %a, align 16
%conv = fptosi fp128 %0 to i32
ret i32 %conv
; CHECK-LABEL: qpConv2sw
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK: lxv v[[REG:[0-9]+]], 0(r3)
; CHECK-NEXT: xscvqpswz v[[CONV:[0-9]+]], v[[REG]]
; CHECK-NEXT: mfvsrwz r[[REG2:[0-9]+]], v[[CONV]]
; CHECK-NEXT: extsw r3, r[[REG2]]
[Power9]Legalize and emit code for truncate and convert Quad-Precision to Word Legalize and emit code for: * xscvqpswz : VSX Scalar truncate & Convert Quad-Precision to Signed Word * xscvqpuwz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Word Differential Revision: https://reviews.llvm.org/D45635 llvm-svn: 331790
2018-05-09 02:34:00 +08:00
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @qpConv2sw_02(i32* nocapture %res) {
entry:
%0 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array, i64 0,
i64 2), align 16
%conv = fptosi fp128 %0 to i32
store i32 %conv, i32* %res, align 4
ret void
; CHECK-LABEL: qpConv2sw_02
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0@toc@ha
; CHECK: ld r[[REG0]], .LC0@toc@l(r[[REG0]])
; CHECK: lxv v[[REG:[0-9]+]], 32(r[[REG0]])
; CHECK-NEXT: xscvqpswz v[[CONV:[0-9]+]], v[[REG]]
; CHECK-NEXT: stxsiwx v[[CONV]], 0, r3
[Power9]Legalize and emit code for truncate and convert Quad-Precision to Word Legalize and emit code for: * xscvqpswz : VSX Scalar truncate & Convert Quad-Precision to Signed Word * xscvqpuwz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Word Differential Revision: https://reviews.llvm.org/D45635 llvm-svn: 331790
2018-05-09 02:34:00 +08:00
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readonly
define signext i32 @qpConv2sw_03(fp128* nocapture readonly %a) {
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array, i64 0,
i64 1), align 16
%add = fadd fp128 %0, %1
%conv = fptosi fp128 %add to i32
ret i32 %conv
; CHECK-LABEL: qpConv2sw_03
[Power9] Enable the Out-of-Order scheduling model for P9 hw When switched to the MI scheduler for P9, the hardware is modeled as out of order. However, inside the MI Scheduler algorithm, we still use the in-order scheduling model as the MicroOpBufferSize isn't set. The MI scheduler take it as the hw cannot buffer the op. So, only when all the available instructions issued, the pending instruction could be scheduled. That is not true for our P9 hw in fact. This patch is trying to enable the Out-of-Order scheduling model. The buffer size 44 is picked from the P9 hw spec, and the perf test indicate that, its value won't hurt the cpu2017. With this patch, there are 3 specs improved over 3% and 1 spec deg over 3%. The detail is as follows: x264_r: +6.95% cactuBSSN_r: +6.94% lbm_r: +4.11% xz_r: -3.85% And the GEOMEAN for all the C/C++ spec in spec2017 is about 0.18% improved. Reviewer: Nemanjai Differential Revision: https://reviews.llvm.org/D55810 llvm-svn: 350285
2019-01-03 13:04:18 +08:00
; CHECK: lxv v[[REG:[0-9]+]], 0(r3)
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0@toc@ha
; CHECK-DAG: ld r[[REG0]], .LC0@toc@l(r[[REG0]])
; CHECK-DAG: lxv v[[REG1:[0-9]+]], 16(r[[REG0]])
; CHECK-NEXT: xsaddqp v[[ADD:[0-9]+]], v[[REG]], v[[REG1]]
; CHECK-NEXT: xscvqpswz v[[CONV:[0-9]+]], v[[ADD]]
; CHECK-NEXT: mfvsrwz r[[REG2:[0-9]+]], v[[CONV]]
; CHECK-NEXT: extsw r3, r[[REG2]]
[Power9]Legalize and emit code for truncate and convert Quad-Precision to Word Legalize and emit code for: * xscvqpswz : VSX Scalar truncate & Convert Quad-Precision to Signed Word * xscvqpuwz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Word Differential Revision: https://reviews.llvm.org/D45635 llvm-svn: 331790
2018-05-09 02:34:00 +08:00
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @qpConv2sw_04(fp128* nocapture readonly %a,
fp128* nocapture readonly %b, i32* nocapture %res) {
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16
%add = fadd fp128 %0, %1
%conv = fptosi fp128 %add to i32
store i32 %conv, i32* %res, align 4
ret void
; CHECK-LABEL: qpConv2sw_04
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK-DAG: lxv v[[REG1:[0-9]+]], 0(r4)
; CHECK-DAG: lxv v[[REG:[0-9]+]], 0(r3)
; CHECK-NEXT: xsaddqp v[[ADD:[0-9]+]], v[[REG]], v[[REG1]]
; CHECK-NEXT: xscvqpswz v[[CONV:[0-9]+]], v[[ADD]]
; CHECK-NEXT: stxsiwx v[[CONV]], 0, r5
[Power9]Legalize and emit code for truncate and convert Quad-Precision to Word Legalize and emit code for: * xscvqpswz : VSX Scalar truncate & Convert Quad-Precision to Signed Word * xscvqpuwz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Word Differential Revision: https://reviews.llvm.org/D45635 llvm-svn: 331790
2018-05-09 02:34:00 +08:00
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readonly
define zeroext i32 @qpConv2uw(fp128* nocapture readonly %a) {
entry:
%0 = load fp128, fp128* %a, align 16
%conv = fptoui fp128 %0 to i32
ret i32 %conv
; CHECK-LABEL: qpConv2uw
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK: lxv v[[REG:[0-9]+]], 0(r3)
; CHECK-NEXT: xscvqpuwz v[[CONV:[0-9]+]], v[[REG]]
; CHECK-NEXT: mfvsrwz r3, v[[CONV]]
[Power9]Legalize and emit code for truncate and convert Quad-Precision to Word Legalize and emit code for: * xscvqpswz : VSX Scalar truncate & Convert Quad-Precision to Signed Word * xscvqpuwz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Word Differential Revision: https://reviews.llvm.org/D45635 llvm-svn: 331790
2018-05-09 02:34:00 +08:00
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @qpConv2uw_02(i32* nocapture %res) {
entry:
%0 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array, i64 0,
i64 2), align 16
%conv = fptoui fp128 %0 to i32
store i32 %conv, i32* %res, align 4
ret void
; CHECK-LABEL: qpConv2uw_02
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0@toc@ha
; CHECK: ld r[[REG0]], .LC0@toc@l(r[[REG0]])
; CHECK: lxv v[[REG:[0-9]+]], 32(r[[REG0]])
; CHECK-NEXT: xscvqpuwz v[[CONV:[0-9]+]], v[[REG]]
; CHECK-NEXT: stxsiwx v[[CONV]], 0, r3
[Power9]Legalize and emit code for truncate and convert Quad-Precision to Word Legalize and emit code for: * xscvqpswz : VSX Scalar truncate & Convert Quad-Precision to Signed Word * xscvqpuwz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Word Differential Revision: https://reviews.llvm.org/D45635 llvm-svn: 331790
2018-05-09 02:34:00 +08:00
; CHECK: blr
}
; Function Attrs: norecurse nounwind readonly
define zeroext i32 @qpConv2uw_03(fp128* nocapture readonly %a) {
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array, i64 0,
i64 1), align 16
%add = fadd fp128 %0, %1
%conv = fptoui fp128 %add to i32
ret i32 %conv
; CHECK-LABEL: qpConv2uw_03
[Power9] Enable the Out-of-Order scheduling model for P9 hw When switched to the MI scheduler for P9, the hardware is modeled as out of order. However, inside the MI Scheduler algorithm, we still use the in-order scheduling model as the MicroOpBufferSize isn't set. The MI scheduler take it as the hw cannot buffer the op. So, only when all the available instructions issued, the pending instruction could be scheduled. That is not true for our P9 hw in fact. This patch is trying to enable the Out-of-Order scheduling model. The buffer size 44 is picked from the P9 hw spec, and the perf test indicate that, its value won't hurt the cpu2017. With this patch, there are 3 specs improved over 3% and 1 spec deg over 3%. The detail is as follows: x264_r: +6.95% cactuBSSN_r: +6.94% lbm_r: +4.11% xz_r: -3.85% And the GEOMEAN for all the C/C++ spec in spec2017 is about 0.18% improved. Reviewer: Nemanjai Differential Revision: https://reviews.llvm.org/D55810 llvm-svn: 350285
2019-01-03 13:04:18 +08:00
; CHECK: lxv v[[REG:[0-9]+]], 0(r3)
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0@toc@ha
; CHECK-DAG: ld r[[REG0]], .LC0@toc@l(r[[REG0]])
; CHECK-DAG: lxv v[[REG1:[0-9]+]], 16(r[[REG0]])
; CHECK-NEXT: xsaddqp v[[ADD:[0-9]+]], v[[REG]], v[[REG1]]
; CHECK-NEXT: xscvqpuwz v[[CONV:[0-9]+]], v[[ADD]]
; CHECK-NEXT: mfvsrwz r3, v[[CONV]]
[Power9]Legalize and emit code for truncate and convert Quad-Precision to Word Legalize and emit code for: * xscvqpswz : VSX Scalar truncate & Convert Quad-Precision to Signed Word * xscvqpuwz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Word Differential Revision: https://reviews.llvm.org/D45635 llvm-svn: 331790
2018-05-09 02:34:00 +08:00
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @qpConv2uw_04(fp128* nocapture readonly %a,
fp128* nocapture readonly %b, i32* nocapture %res) {
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16
%add = fadd fp128 %0, %1
%conv = fptoui fp128 %add to i32
store i32 %conv, i32* %res, align 4
ret void
; CHECK-LABEL: qpConv2uw_04
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK-DAG: lxv v[[REG1:[0-9]+]], 0(r4)
; CHECK-DAG: lxv v[[REG:[0-9]+]], 0(r3)
; CHECK-NEXT: xsaddqp v[[ADD:[0-9]+]], v[[REG]], v[[REG1]]
; CHECK-NEXT: xscvqpuwz v[[CONV:[0-9]+]], v[[ADD]]
; CHECK-NEXT: stxsiwx v[[CONV]], 0, r5
[Power9]Legalize and emit code for truncate and convert Quad-Precision to Word Legalize and emit code for: * xscvqpswz : VSX Scalar truncate & Convert Quad-Precision to Signed Word * xscvqpuwz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Word Differential Revision: https://reviews.llvm.org/D45635 llvm-svn: 331790
2018-05-09 02:34:00 +08:00
; CHECK: blr
}
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-09 02:52:06 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Function Attrs: norecurse nounwind readonly
define signext i16 @qpConv2shw(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2shw:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
[DAGCombiner][X86][PowerPC] Teach visitSIGN_EXTEND_INREG to fold (sext_in_reg (aext/sext x)) -> (sext x) when x has more than 1 sign bit and the sext_inreg is from one of them. If x has multiple sign bits than it doesn't matter which one we extend from so we can sext from x's msb instead. The X86 setcc-combine.ll changes are a little weird. It appears we ended up with a (sext_inreg (aext (trunc (extractelt)))) after type legalization. The sext_inreg+aext now gets optimized by this combine to leave (sext (trunc (extractelt))). Then we visit the trunc before we visit the sext. This ends up changing the truncate to an extractvectorelt from a bitcasted vector. I have a follow up patch to fix this. Differential Revision: https://reviews.llvm.org/D56156 llvm-svn: 350235
2019-01-03 01:58:27 +08:00
; CHECK-NEXT: extsw r3, r3
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-09 02:52:06 +08:00
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
%conv = fptosi fp128 %0 to i16
ret i16 %conv
}
; Function Attrs: norecurse nounwind
define void @qpConv2shw_02(i16* nocapture %res) {
; CHECK-LABEL: qpConv2shw_02:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: lxv v2, 32(r4)
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: stxsihx v2, 0, r3
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-09 02:52:06 +08:00
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array,
i64 0, i64 2), align 16
%conv = fptosi fp128 %0 to i16
store i16 %conv, i16* %res, align 2
ret void
}
; Function Attrs: norecurse nounwind readonly
define signext i16 @qpConv2shw_03(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2shw_03:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK-NEXT: lxv v2, 0(r3)
[Power9] Enable the Out-of-Order scheduling model for P9 hw When switched to the MI scheduler for P9, the hardware is modeled as out of order. However, inside the MI Scheduler algorithm, we still use the in-order scheduling model as the MicroOpBufferSize isn't set. The MI scheduler take it as the hw cannot buffer the op. So, only when all the available instructions issued, the pending instruction could be scheduled. That is not true for our P9 hw in fact. This patch is trying to enable the Out-of-Order scheduling model. The buffer size 44 is picked from the P9 hw spec, and the perf test indicate that, its value won't hurt the cpu2017. With this patch, there are 3 specs improved over 3% and 1 spec deg over 3%. The detail is as follows: x264_r: +6.95% cactuBSSN_r: +6.94% lbm_r: +4.11% xz_r: -3.85% And the GEOMEAN for all the C/C++ spec in spec2017 is about 0.18% improved. Reviewer: Nemanjai Differential Revision: https://reviews.llvm.org/D55810 llvm-svn: 350285
2019-01-03 13:04:18 +08:00
; CHECK-NEXT: addis [[REG:r[0-9]+]], r2, .LC0@toc@ha
; CHECK-NEXT: ld [[REG1:r[0-9]+]], .LC0@toc@l([[REG]])
; CHECK-NEXT: lxv v3, 16([[REG1]])
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
[DAGCombiner][X86][PowerPC] Teach visitSIGN_EXTEND_INREG to fold (sext_in_reg (aext/sext x)) -> (sext x) when x has more than 1 sign bit and the sext_inreg is from one of them. If x has multiple sign bits than it doesn't matter which one we extend from so we can sext from x's msb instead. The X86 setcc-combine.ll changes are a little weird. It appears we ended up with a (sext_inreg (aext (trunc (extractelt)))) after type legalization. The sext_inreg+aext now gets optimized by this combine to leave (sext (trunc (extractelt))). Then we visit the trunc before we visit the sext. This ends up changing the truncate to an extractvectorelt from a bitcasted vector. I have a follow up patch to fix this. Differential Revision: https://reviews.llvm.org/D56156 llvm-svn: 350235
2019-01-03 01:58:27 +08:00
; CHECK-NEXT: extsw r3, r3
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-09 02:52:06 +08:00
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array,
i64 0, i64 1), align 16
%add = fadd fp128 %0, %1
%conv = fptosi fp128 %add to i16
ret i16 %conv
}
; Function Attrs: norecurse nounwind
define void @qpConv2shw_04(fp128* nocapture readonly %a,
fp128* nocapture readonly %b, i16* nocapture %res) {
; CHECK-LABEL: qpConv2shw_04:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: lxv v3, 0(r4)
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: stxsihx v2, 0, r5
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-09 02:52:06 +08:00
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16
%add = fadd fp128 %0, %1
%conv = fptosi fp128 %add to i16
store i16 %conv, i16* %res, align 2
ret void
}
; Function Attrs: norecurse nounwind readonly
define zeroext i16 @qpConv2uhw(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2uhw:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: clrldi r3, r3, 32
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-09 02:52:06 +08:00
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
%conv = fptoui fp128 %0 to i16
ret i16 %conv
}
; Function Attrs: norecurse nounwind
define void @qpConv2uhw_02(i16* nocapture %res) {
; CHECK-LABEL: qpConv2uhw_02:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: lxv v2, 32(r4)
; CHECK-NEXT: xscvqpuwz v2, v2
; CHECK-NEXT: stxsihx v2, 0, r3
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-09 02:52:06 +08:00
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array,
i64 0, i64 2), align 16
%conv = fptoui fp128 %0 to i16
store i16 %conv, i16* %res, align 2
ret void
}
; Function Attrs: norecurse nounwind readonly
define zeroext i16 @qpConv2uhw_03(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2uhw_03:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK-NEXT: lxv v2, 0(r3)
[Power9] Enable the Out-of-Order scheduling model for P9 hw When switched to the MI scheduler for P9, the hardware is modeled as out of order. However, inside the MI Scheduler algorithm, we still use the in-order scheduling model as the MicroOpBufferSize isn't set. The MI scheduler take it as the hw cannot buffer the op. So, only when all the available instructions issued, the pending instruction could be scheduled. That is not true for our P9 hw in fact. This patch is trying to enable the Out-of-Order scheduling model. The buffer size 44 is picked from the P9 hw spec, and the perf test indicate that, its value won't hurt the cpu2017. With this patch, there are 3 specs improved over 3% and 1 spec deg over 3%. The detail is as follows: x264_r: +6.95% cactuBSSN_r: +6.94% lbm_r: +4.11% xz_r: -3.85% And the GEOMEAN for all the C/C++ spec in spec2017 is about 0.18% improved. Reviewer: Nemanjai Differential Revision: https://reviews.llvm.org/D55810 llvm-svn: 350285
2019-01-03 13:04:18 +08:00
; CHECK-NEXT: addis [[REG:r[0-9]+]], r2, .LC0@toc@ha
; CHECK-NEXT: ld [[REG1:r[0-9]+]], .LC0@toc@l([[REG]])
; CHECK-NEXT: lxv v3, 16([[REG1]])
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: clrldi r3, r3, 32
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-09 02:52:06 +08:00
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array,
i64 0, i64 1), align 16
%add = fadd fp128 %0, %1
%conv = fptoui fp128 %add to i16
ret i16 %conv
}
; Function Attrs: norecurse nounwind
define void @qpConv2uhw_04(fp128* nocapture readonly %a,
fp128* nocapture readonly %b, i16* nocapture %res) {
; CHECK-LABEL: qpConv2uhw_04:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: lxv v3, 0(r4)
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpuwz v2, v2
; CHECK-NEXT: stxsihx v2, 0, r5
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-09 02:52:06 +08:00
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16
%add = fadd fp128 %0, %1
%conv = fptoui fp128 %add to i16
store i16 %conv, i16* %res, align 2
ret void
}
; Function Attrs: norecurse nounwind readonly
define signext i8 @qpConv2sb(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2sb:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
[DAGCombiner][X86][PowerPC] Teach visitSIGN_EXTEND_INREG to fold (sext_in_reg (aext/sext x)) -> (sext x) when x has more than 1 sign bit and the sext_inreg is from one of them. If x has multiple sign bits than it doesn't matter which one we extend from so we can sext from x's msb instead. The X86 setcc-combine.ll changes are a little weird. It appears we ended up with a (sext_inreg (aext (trunc (extractelt)))) after type legalization. The sext_inreg+aext now gets optimized by this combine to leave (sext (trunc (extractelt))). Then we visit the trunc before we visit the sext. This ends up changing the truncate to an extractvectorelt from a bitcasted vector. I have a follow up patch to fix this. Differential Revision: https://reviews.llvm.org/D56156 llvm-svn: 350235
2019-01-03 01:58:27 +08:00
; CHECK-NEXT: extsw r3, r3
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-09 02:52:06 +08:00
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
%conv = fptosi fp128 %0 to i8
ret i8 %conv
}
; Function Attrs: norecurse nounwind
define void @qpConv2sb_02(i8* nocapture %res) {
; CHECK-LABEL: qpConv2sb_02:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: lxv v2, 32(r4)
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: stxsibx v2, 0, r3
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-09 02:52:06 +08:00
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array,
i64 0, i64 2), align 16
%conv = fptosi fp128 %0 to i8
store i8 %conv, i8* %res, align 1
ret void
}
; Function Attrs: norecurse nounwind readonly
define signext i8 @qpConv2sb_03(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2sb_03:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK-NEXT: lxv v2, 0(r3)
[Power9] Enable the Out-of-Order scheduling model for P9 hw When switched to the MI scheduler for P9, the hardware is modeled as out of order. However, inside the MI Scheduler algorithm, we still use the in-order scheduling model as the MicroOpBufferSize isn't set. The MI scheduler take it as the hw cannot buffer the op. So, only when all the available instructions issued, the pending instruction could be scheduled. That is not true for our P9 hw in fact. This patch is trying to enable the Out-of-Order scheduling model. The buffer size 44 is picked from the P9 hw spec, and the perf test indicate that, its value won't hurt the cpu2017. With this patch, there are 3 specs improved over 3% and 1 spec deg over 3%. The detail is as follows: x264_r: +6.95% cactuBSSN_r: +6.94% lbm_r: +4.11% xz_r: -3.85% And the GEOMEAN for all the C/C++ spec in spec2017 is about 0.18% improved. Reviewer: Nemanjai Differential Revision: https://reviews.llvm.org/D55810 llvm-svn: 350285
2019-01-03 13:04:18 +08:00
; CHECK-NEXT: addis [[REG:r[0-9]+]], r2, .LC0@toc@ha
; CHECK-NEXT: ld [[REG1:r[0-9]+]], .LC0@toc@l([[REG]])
; CHECK-NEXT: lxv v3, 16([[REG1]])
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
[DAGCombiner][X86][PowerPC] Teach visitSIGN_EXTEND_INREG to fold (sext_in_reg (aext/sext x)) -> (sext x) when x has more than 1 sign bit and the sext_inreg is from one of them. If x has multiple sign bits than it doesn't matter which one we extend from so we can sext from x's msb instead. The X86 setcc-combine.ll changes are a little weird. It appears we ended up with a (sext_inreg (aext (trunc (extractelt)))) after type legalization. The sext_inreg+aext now gets optimized by this combine to leave (sext (trunc (extractelt))). Then we visit the trunc before we visit the sext. This ends up changing the truncate to an extractvectorelt from a bitcasted vector. I have a follow up patch to fix this. Differential Revision: https://reviews.llvm.org/D56156 llvm-svn: 350235
2019-01-03 01:58:27 +08:00
; CHECK-NEXT: extsw r3, r3
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-09 02:52:06 +08:00
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array,
i64 0, i64 1), align 16
%add = fadd fp128 %0, %1
%conv = fptosi fp128 %add to i8
ret i8 %conv
}
; Function Attrs: norecurse nounwind
define void @qpConv2sb_04(fp128* nocapture readonly %a,
fp128* nocapture readonly %b, i8* nocapture %res) {
; CHECK-LABEL: qpConv2sb_04:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: lxv v3, 0(r4)
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: stxsibx v2, 0, r5
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-09 02:52:06 +08:00
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16
%add = fadd fp128 %0, %1
%conv = fptosi fp128 %add to i8
store i8 %conv, i8* %res, align 1
ret void
}
; Function Attrs: norecurse nounwind readonly
define zeroext i8 @qpConv2ub(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2ub:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: clrldi r3, r3, 32
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-09 02:52:06 +08:00
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
%conv = fptoui fp128 %0 to i8
ret i8 %conv
}
; Function Attrs: norecurse nounwind
define void @qpConv2ub_02(i8* nocapture %res) {
; CHECK-LABEL: qpConv2ub_02:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: lxv v2, 32(r4)
; CHECK-NEXT: xscvqpuwz v2, v2
; CHECK-NEXT: stxsibx v2, 0, r3
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-09 02:52:06 +08:00
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array,
i64 0, i64 2), align 16
%conv = fptoui fp128 %0 to i8
store i8 %conv, i8* %res, align 1
ret void
}
; Function Attrs: norecurse nounwind readonly
define zeroext i8 @qpConv2ub_03(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2ub_03:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK-NEXT: lxv v2, 0(r3)
[Power9] Enable the Out-of-Order scheduling model for P9 hw When switched to the MI scheduler for P9, the hardware is modeled as out of order. However, inside the MI Scheduler algorithm, we still use the in-order scheduling model as the MicroOpBufferSize isn't set. The MI scheduler take it as the hw cannot buffer the op. So, only when all the available instructions issued, the pending instruction could be scheduled. That is not true for our P9 hw in fact. This patch is trying to enable the Out-of-Order scheduling model. The buffer size 44 is picked from the P9 hw spec, and the perf test indicate that, its value won't hurt the cpu2017. With this patch, there are 3 specs improved over 3% and 1 spec deg over 3%. The detail is as follows: x264_r: +6.95% cactuBSSN_r: +6.94% lbm_r: +4.11% xz_r: -3.85% And the GEOMEAN for all the C/C++ spec in spec2017 is about 0.18% improved. Reviewer: Nemanjai Differential Revision: https://reviews.llvm.org/D55810 llvm-svn: 350285
2019-01-03 13:04:18 +08:00
; CHECK-NEXT: addis [[REG:r[0-9]+]], r2, .LC0@toc@ha
; CHECK-NEXT: ld [[REG1:r[0-9]+]], .LC0@toc@l([[REG]])
; CHECK-NEXT: lxv v3, 16([[REG1]])
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: clrldi r3, r3, 32
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-09 02:52:06 +08:00
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array,
i64 0, i64 1), align 16
%add = fadd fp128 %0, %1
%conv = fptoui fp128 %add to i8
ret i8 %conv
}
; Function Attrs: norecurse nounwind
define void @qpConv2ub_04(fp128* nocapture readonly %a,
fp128* nocapture readonly %b, i8* nocapture %res) {
; CHECK-LABEL: qpConv2ub_04:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-13 04:18:57 +08:00
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: lxv v3, 0(r4)
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpuwz v2, v2
; CHECK-NEXT: stxsibx v2, 0, r5
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-09 02:52:06 +08:00
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16
%add = fadd fp128 %0, %1
%conv = fptoui fp128 %add to i8
store i8 %conv, i8* %res, align 1
ret void
}