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llvm-project/llvm/test/CodeGen/Mips/select.ll

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[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=32
; RUN: llc < %s -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r2 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=32R2
; RUN: llc < %s -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r6 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=32R6
; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -mcpu=mips64 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=64
; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -mcpu=mips64r2 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=64R2
; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -mcpu=mips64r6 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=64R6
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
@d2 = external global double
@d3 = external global double
[mips] Promote i32 arguments to i64 for the N32/N64 ABI and fix <64-bit structs... Summary: ... and after all that refactoring, it's possible to distinguish softfloat floating point values from integers so this patch no longer breaks softfloat to do it. Remove direct handling of i32's in the N32/N64 ABI by promoting them to i64. This more closely reflects the ABI documentation and also fixes problems with stack arguments on big-endian targets. We now rely on signext/zeroext annotations (already generated by clang) and the Assert[SZ]ext nodes to avoid the introduction of unnecessary sign/zero extends. It was not possible to convert three tests to use signext/zeroext. These tests are bswap.ll, ctlz-v.ll, ctlz-v.ll. It's not possible to put signext on a vector type so we just accept the sign extends here for now. These tests don't pass the vectors the same way clang does (clang puts multiple elements in the same argument, these map 1 element to 1 argument) so we don't need to worry too much about it. With this patch, all known N32/N64 bugs should be fixed and we now pass the first 10,000 tests generated by ABITest.py. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6117 llvm-svn: 221534
2014-11-08 00:54:21 +08:00
define i32 @i32_icmp_ne_i32_val(i32 signext %s, i32 signext %f0, i32 signext %f1) nounwind readnone {
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 32-LABEL: i32_icmp_ne_i32_val:
; 32: # %bb.0: # %entry
; 32-NEXT: movn $5, $6, $4
; 32-NEXT: jr $ra
; 32-NEXT: move $2, $5
;
; 32R2-LABEL: i32_icmp_ne_i32_val:
; 32R2: # %bb.0: # %entry
; 32R2-NEXT: movn $5, $6, $4
; 32R2-NEXT: jr $ra
; 32R2-NEXT: move $2, $5
;
; 32R6-LABEL: i32_icmp_ne_i32_val:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: seleqz $1, $5, $4
; 32R6-NEXT: selnez $2, $6, $4
; 32R6-NEXT: jr $ra
; 32R6-NEXT: or $2, $2, $1
;
; 64-LABEL: i32_icmp_ne_i32_val:
; 64: # %bb.0: # %entry
; 64-NEXT: movn $5, $6, $4
; 64-NEXT: jr $ra
; 64-NEXT: move $2, $5
;
; 64R2-LABEL: i32_icmp_ne_i32_val:
; 64R2: # %bb.0: # %entry
; 64R2-NEXT: movn $5, $6, $4
; 64R2-NEXT: jr $ra
; 64R2-NEXT: move $2, $5
;
; 64R6-LABEL: i32_icmp_ne_i32_val:
; 64R6: # %bb.0: # %entry
; 64R6-NEXT: seleqz $1, $5, $4
; 64R6-NEXT: selnez $2, $6, $4
; 64R6-NEXT: jr $ra
; 64R6-NEXT: or $2, $2, $1
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
entry:
%tobool = icmp ne i32 %s, 0
%cond = select i1 %tobool, i32 %f1, i32 %f0
ret i32 %cond
}
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; FIXME: The sll works around an implementation detail in the code generator
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
; (setcc's result is i32 so bits 32-63 are undefined). It's not really
; needed.
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
define i64 @i32_icmp_ne_i64_val(i32 signext %s, i64 %f0, i64 %f1) nounwind readnone {
; 32-LABEL: i32_icmp_ne_i64_val:
; 32: # %bb.0: # %entry
; 32-NEXT: lw $1, 16($sp)
; 32-NEXT: movn $6, $1, $4
; 32-NEXT: lw $1, 20($sp)
; 32-NEXT: movn $7, $1, $4
; 32-NEXT: move $2, $6
; 32-NEXT: jr $ra
; 32-NEXT: move $3, $7
;
; 32R2-LABEL: i32_icmp_ne_i64_val:
; 32R2: # %bb.0: # %entry
; 32R2-NEXT: lw $1, 16($sp)
; 32R2-NEXT: movn $6, $1, $4
; 32R2-NEXT: lw $1, 20($sp)
; 32R2-NEXT: movn $7, $1, $4
; 32R2-NEXT: move $2, $6
; 32R2-NEXT: jr $ra
; 32R2-NEXT: move $3, $7
;
; 32R6-LABEL: i32_icmp_ne_i64_val:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: seleqz $1, $6, $4
; 32R6-NEXT: lw $2, 16($sp)
; 32R6-NEXT: selnez $2, $2, $4
; 32R6-NEXT: or $2, $2, $1
; 32R6-NEXT: seleqz $1, $7, $4
; 32R6-NEXT: lw $3, 20($sp)
; 32R6-NEXT: selnez $3, $3, $4
; 32R6-NEXT: jr $ra
; 32R6-NEXT: or $3, $3, $1
;
; 64-LABEL: i32_icmp_ne_i64_val:
; 64: # %bb.0: # %entry
; 64-NEXT: movn $5, $6, $4
; 64-NEXT: jr $ra
; 64-NEXT: move $2, $5
;
; 64R2-LABEL: i32_icmp_ne_i64_val:
; 64R2: # %bb.0: # %entry
; 64R2-NEXT: movn $5, $6, $4
; 64R2-NEXT: jr $ra
; 64R2-NEXT: move $2, $5
;
; 64R6-LABEL: i32_icmp_ne_i64_val:
; 64R6: # %bb.0: # %entry
; 64R6-NEXT: sll $1, $4, 0
; 64R6-NEXT: seleqz $2, $5, $1
; 64R6-NEXT: selnez $1, $6, $1
; 64R6-NEXT: jr $ra
; 64R6-NEXT: or $2, $1, $2
entry:
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
%tobool = icmp ne i32 %s, 0
%cond = select i1 %tobool, i64 %f1, i64 %f0
ret i64 %cond
}
define i64 @i64_icmp_ne_i64_val(i64 %s, i64 %f0, i64 %f1) nounwind readnone {
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 32-LABEL: i64_icmp_ne_i64_val:
; 32: # %bb.0: # %entry
; 32-NEXT: or $1, $4, $5
; 32-NEXT: lw $2, 16($sp)
; 32-NEXT: movn $6, $2, $1
; 32-NEXT: lw $2, 20($sp)
; 32-NEXT: movn $7, $2, $1
; 32-NEXT: move $2, $6
; 32-NEXT: jr $ra
; 32-NEXT: move $3, $7
;
; 32R2-LABEL: i64_icmp_ne_i64_val:
; 32R2: # %bb.0: # %entry
; 32R2-NEXT: or $1, $4, $5
; 32R2-NEXT: lw $2, 16($sp)
; 32R2-NEXT: movn $6, $2, $1
; 32R2-NEXT: lw $2, 20($sp)
; 32R2-NEXT: movn $7, $2, $1
; 32R2-NEXT: move $2, $6
; 32R2-NEXT: jr $ra
; 32R2-NEXT: move $3, $7
;
; 32R6-LABEL: i64_icmp_ne_i64_val:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: or $1, $4, $5
; 32R6-NEXT: seleqz $2, $6, $1
; 32R6-NEXT: lw $3, 16($sp)
; 32R6-NEXT: selnez $3, $3, $1
; 32R6-NEXT: or $2, $3, $2
; 32R6-NEXT: seleqz $3, $7, $1
; 32R6-NEXT: lw $4, 20($sp)
; 32R6-NEXT: selnez $1, $4, $1
; 32R6-NEXT: jr $ra
; 32R6-NEXT: or $3, $1, $3
;
; 64-LABEL: i64_icmp_ne_i64_val:
; 64: # %bb.0: # %entry
; 64-NEXT: movn $5, $6, $4
; 64-NEXT: jr $ra
; 64-NEXT: move $2, $5
;
; 64R2-LABEL: i64_icmp_ne_i64_val:
; 64R2: # %bb.0: # %entry
; 64R2-NEXT: movn $5, $6, $4
; 64R2-NEXT: jr $ra
; 64R2-NEXT: move $2, $5
;
; 64R6-LABEL: i64_icmp_ne_i64_val:
; 64R6: # %bb.0: # %entry
; 64R6-NEXT: seleqz $1, $5, $4
; 64R6-NEXT: selnez $2, $6, $4
; 64R6-NEXT: jr $ra
; 64R6-NEXT: or $2, $2, $1
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
entry:
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
%tobool = icmp ne i64 %s, 0
%cond = select i1 %tobool, i64 %f1, i64 %f0
ret i64 %cond
}
[mips] Promote i32 arguments to i64 for the N32/N64 ABI and fix <64-bit structs... Summary: ... and after all that refactoring, it's possible to distinguish softfloat floating point values from integers so this patch no longer breaks softfloat to do it. Remove direct handling of i32's in the N32/N64 ABI by promoting them to i64. This more closely reflects the ABI documentation and also fixes problems with stack arguments on big-endian targets. We now rely on signext/zeroext annotations (already generated by clang) and the Assert[SZ]ext nodes to avoid the introduction of unnecessary sign/zero extends. It was not possible to convert three tests to use signext/zeroext. These tests are bswap.ll, ctlz-v.ll, ctlz-v.ll. It's not possible to put signext on a vector type so we just accept the sign extends here for now. These tests don't pass the vectors the same way clang does (clang puts multiple elements in the same argument, these map 1 element to 1 argument) so we don't need to worry too much about it. With this patch, all known N32/N64 bugs should be fixed and we now pass the first 10,000 tests generated by ABITest.py. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6117 llvm-svn: 221534
2014-11-08 00:54:21 +08:00
define float @i32_icmp_ne_f32_val(i32 signext %s, float %f0, float %f1) nounwind readnone {
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 32-LABEL: i32_icmp_ne_f32_val:
; 32: # %bb.0: # %entry
; 32-NEXT: mtc1 $6, $f0
; 32-NEXT: mtc1 $5, $f1
; 32-NEXT: jr $ra
; 32-NEXT: movn.s $f0, $f1, $4
;
; 32R2-LABEL: i32_icmp_ne_f32_val:
; 32R2: # %bb.0: # %entry
; 32R2-NEXT: mtc1 $6, $f0
; 32R2-NEXT: mtc1 $5, $f1
; 32R2-NEXT: jr $ra
; 32R2-NEXT: movn.s $f0, $f1, $4
;
; 32R6-LABEL: i32_icmp_ne_f32_val:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: sltu $1, $zero, $4
; 32R6-NEXT: negu $1, $1
; 32R6-NEXT: mtc1 $5, $f1
; 32R6-NEXT: mtc1 $6, $f2
; 32R6-NEXT: mtc1 $1, $f0
; 32R6-NEXT: jr $ra
; 32R6-NEXT: sel.s $f0, $f2, $f1
;
; 64-LABEL: i32_icmp_ne_f32_val:
; 64: # %bb.0: # %entry
; 64-NEXT: mov.s $f0, $f14
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64-NEXT: jr $ra
; 64-NEXT: movn.s $f0, $f13, $4
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 64R2-LABEL: i32_icmp_ne_f32_val:
; 64R2: # %bb.0: # %entry
; 64R2-NEXT: mov.s $f0, $f14
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64R2-NEXT: jr $ra
; 64R2-NEXT: movn.s $f0, $f13, $4
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 64R6-LABEL: i32_icmp_ne_f32_val:
; 64R6: # %bb.0: # %entry
; 64R6-NEXT: sltu $1, $zero, $4
; 64R6-NEXT: negu $1, $1
; 64R6-NEXT: mtc1 $1, $f0
; 64R6-NEXT: jr $ra
; 64R6-NEXT: sel.s $f0, $f14, $f13
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
entry:
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
%tobool = icmp ne i32 %s, 0
%cond = select i1 %tobool, float %f0, float %f1
ret float %cond
}
[mips] Promote i32 arguments to i64 for the N32/N64 ABI and fix <64-bit structs... Summary: ... and after all that refactoring, it's possible to distinguish softfloat floating point values from integers so this patch no longer breaks softfloat to do it. Remove direct handling of i32's in the N32/N64 ABI by promoting them to i64. This more closely reflects the ABI documentation and also fixes problems with stack arguments on big-endian targets. We now rely on signext/zeroext annotations (already generated by clang) and the Assert[SZ]ext nodes to avoid the introduction of unnecessary sign/zero extends. It was not possible to convert three tests to use signext/zeroext. These tests are bswap.ll, ctlz-v.ll, ctlz-v.ll. It's not possible to put signext on a vector type so we just accept the sign extends here for now. These tests don't pass the vectors the same way clang does (clang puts multiple elements in the same argument, these map 1 element to 1 argument) so we don't need to worry too much about it. With this patch, all known N32/N64 bugs should be fixed and we now pass the first 10,000 tests generated by ABITest.py. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6117 llvm-svn: 221534
2014-11-08 00:54:21 +08:00
define double @i32_icmp_ne_f64_val(i32 signext %s, double %f0, double %f1) nounwind readnone {
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 32-LABEL: i32_icmp_ne_f64_val:
; 32: # %bb.0: # %entry
; 32-NEXT: mtc1 $6, $f2
; 32-NEXT: mtc1 $7, $f3
; 32-NEXT: ldc1 $f0, 16($sp)
; 32-NEXT: jr $ra
; 32-NEXT: movn.d $f0, $f2, $4
;
; 32R2-LABEL: i32_icmp_ne_f64_val:
; 32R2: # %bb.0: # %entry
; 32R2-NEXT: mtc1 $6, $f2
; 32R2-NEXT: mthc1 $7, $f2
; 32R2-NEXT: ldc1 $f0, 16($sp)
; 32R2-NEXT: jr $ra
; 32R2-NEXT: movn.d $f0, $f2, $4
;
; 32R6-LABEL: i32_icmp_ne_f64_val:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: mtc1 $6, $f1
; 32R6-NEXT: mthc1 $7, $f1
; 32R6-NEXT: sltu $1, $zero, $4
; 32R6-NEXT: negu $1, $1
; 32R6-NEXT: mtc1 $1, $f0
; 32R6-NEXT: ldc1 $f2, 16($sp)
; 32R6-NEXT: jr $ra
; 32R6-NEXT: sel.d $f0, $f2, $f1
;
; 64-LABEL: i32_icmp_ne_f64_val:
; 64: # %bb.0: # %entry
; 64-NEXT: mov.d $f0, $f14
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64-NEXT: jr $ra
; 64-NEXT: movn.d $f0, $f13, $4
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 64R2-LABEL: i32_icmp_ne_f64_val:
; 64R2: # %bb.0: # %entry
; 64R2-NEXT: mov.d $f0, $f14
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64R2-NEXT: jr $ra
; 64R2-NEXT: movn.d $f0, $f13, $4
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 64R6-LABEL: i32_icmp_ne_f64_val:
; 64R6: # %bb.0: # %entry
; 64R6-NEXT: sltu $1, $zero, $4
; 64R6-NEXT: negu $1, $1
; 64R6-NEXT: mtc1 $1, $f0
; 64R6-NEXT: jr $ra
; 64R6-NEXT: sel.d $f0, $f14, $f13
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
entry:
%tobool = icmp ne i32 %s, 0
%cond = select i1 %tobool, double %f0, double %f1
ret double %cond
}
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
define float @f32_fcmp_oeq_f32_val(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 32-LABEL: f32_fcmp_oeq_f32_val:
; 32: # %bb.0: # %entry
; 32-NEXT: mov.s $f0, $f14
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 32-NEXT: mtc1 $7, $f1
; 32-NEXT: mtc1 $6, $f2
; 32-NEXT: c.eq.s $f2, $f1
; 32-NEXT: jr $ra
; 32-NEXT: movt.s $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 32R2-LABEL: f32_fcmp_oeq_f32_val:
; 32R2: # %bb.0: # %entry
; 32R2-NEXT: mov.s $f0, $f14
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 32R2-NEXT: mtc1 $7, $f1
; 32R2-NEXT: mtc1 $6, $f2
; 32R2-NEXT: c.eq.s $f2, $f1
; 32R2-NEXT: jr $ra
; 32R2-NEXT: movt.s $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 32R6-LABEL: f32_fcmp_oeq_f32_val:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: mtc1 $7, $f0
; 32R6-NEXT: mtc1 $6, $f1
; 32R6-NEXT: cmp.eq.s $f0, $f1, $f0
; 32R6-NEXT: jr $ra
; 32R6-NEXT: sel.s $f0, $f14, $f12
;
; 64-LABEL: f32_fcmp_oeq_f32_val:
; 64: # %bb.0: # %entry
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64-NEXT: mov.s $f0, $f13
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 64-NEXT: c.eq.s $f14, $f15
; 64-NEXT: jr $ra
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64-NEXT: movt.s $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 64R2-LABEL: f32_fcmp_oeq_f32_val:
; 64R2: # %bb.0: # %entry
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64R2-NEXT: mov.s $f0, $f13
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 64R2-NEXT: c.eq.s $f14, $f15
; 64R2-NEXT: jr $ra
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64R2-NEXT: movt.s $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 64R6-LABEL: f32_fcmp_oeq_f32_val:
; 64R6: # %bb.0: # %entry
; 64R6-NEXT: cmp.eq.s $f0, $f14, $f15
; 64R6-NEXT: jr $ra
; 64R6-NEXT: sel.s $f0, $f13, $f12
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
entry:
%cmp = fcmp oeq float %f2, %f3
%cond = select i1 %cmp, float %f0, float %f1
ret float %cond
}
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
define float @f32_fcmp_olt_f32_val(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 32-LABEL: f32_fcmp_olt_f32_val:
; 32: # %bb.0: # %entry
; 32-NEXT: mov.s $f0, $f14
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 32-NEXT: mtc1 $7, $f1
; 32-NEXT: mtc1 $6, $f2
; 32-NEXT: c.olt.s $f2, $f1
; 32-NEXT: jr $ra
; 32-NEXT: movt.s $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 32R2-LABEL: f32_fcmp_olt_f32_val:
; 32R2: # %bb.0: # %entry
; 32R2-NEXT: mov.s $f0, $f14
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 32R2-NEXT: mtc1 $7, $f1
; 32R2-NEXT: mtc1 $6, $f2
; 32R2-NEXT: c.olt.s $f2, $f1
; 32R2-NEXT: jr $ra
; 32R2-NEXT: movt.s $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 32R6-LABEL: f32_fcmp_olt_f32_val:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: mtc1 $7, $f0
; 32R6-NEXT: mtc1 $6, $f1
; 32R6-NEXT: cmp.lt.s $f0, $f1, $f0
; 32R6-NEXT: jr $ra
; 32R6-NEXT: sel.s $f0, $f14, $f12
;
; 64-LABEL: f32_fcmp_olt_f32_val:
; 64: # %bb.0: # %entry
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64-NEXT: mov.s $f0, $f13
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 64-NEXT: c.olt.s $f14, $f15
; 64-NEXT: jr $ra
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64-NEXT: movt.s $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 64R2-LABEL: f32_fcmp_olt_f32_val:
; 64R2: # %bb.0: # %entry
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64R2-NEXT: mov.s $f0, $f13
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 64R2-NEXT: c.olt.s $f14, $f15
; 64R2-NEXT: jr $ra
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64R2-NEXT: movt.s $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 64R6-LABEL: f32_fcmp_olt_f32_val:
; 64R6: # %bb.0: # %entry
; 64R6-NEXT: cmp.lt.s $f0, $f14, $f15
; 64R6-NEXT: jr $ra
; 64R6-NEXT: sel.s $f0, $f13, $f12
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
entry:
%cmp = fcmp olt float %f2, %f3
%cond = select i1 %cmp, float %f0, float %f1
ret float %cond
}
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
define float @f32_fcmp_ogt_f32_val(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 32-LABEL: f32_fcmp_ogt_f32_val:
; 32: # %bb.0: # %entry
; 32-NEXT: mov.s $f0, $f14
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 32-NEXT: mtc1 $7, $f1
; 32-NEXT: mtc1 $6, $f2
; 32-NEXT: c.ule.s $f2, $f1
; 32-NEXT: jr $ra
; 32-NEXT: movf.s $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 32R2-LABEL: f32_fcmp_ogt_f32_val:
; 32R2: # %bb.0: # %entry
; 32R2-NEXT: mov.s $f0, $f14
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 32R2-NEXT: mtc1 $7, $f1
; 32R2-NEXT: mtc1 $6, $f2
; 32R2-NEXT: c.ule.s $f2, $f1
; 32R2-NEXT: jr $ra
; 32R2-NEXT: movf.s $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 32R6-LABEL: f32_fcmp_ogt_f32_val:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: mtc1 $6, $f0
; 32R6-NEXT: mtc1 $7, $f1
; 32R6-NEXT: cmp.lt.s $f0, $f1, $f0
; 32R6-NEXT: jr $ra
; 32R6-NEXT: sel.s $f0, $f14, $f12
;
; 64-LABEL: f32_fcmp_ogt_f32_val:
; 64: # %bb.0: # %entry
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64-NEXT: mov.s $f0, $f13
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 64-NEXT: c.ule.s $f14, $f15
; 64-NEXT: jr $ra
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64-NEXT: movf.s $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 64R2-LABEL: f32_fcmp_ogt_f32_val:
; 64R2: # %bb.0: # %entry
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64R2-NEXT: mov.s $f0, $f13
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 64R2-NEXT: c.ule.s $f14, $f15
; 64R2-NEXT: jr $ra
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64R2-NEXT: movf.s $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 64R6-LABEL: f32_fcmp_ogt_f32_val:
; 64R6: # %bb.0: # %entry
; 64R6-NEXT: cmp.lt.s $f0, $f15, $f14
; 64R6-NEXT: jr $ra
; 64R6-NEXT: sel.s $f0, $f13, $f12
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
entry:
%cmp = fcmp ogt float %f2, %f3
%cond = select i1 %cmp, float %f0, float %f1
ret float %cond
}
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
define double @f32_fcmp_ogt_f64_val(double %f0, double %f1, float %f2, float %f3) nounwind readnone {
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 32-LABEL: f32_fcmp_ogt_f64_val:
; 32: # %bb.0: # %entry
; 32-NEXT: mov.d $f0, $f14
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 32-NEXT: lwc1 $f2, 20($sp)
; 32-NEXT: lwc1 $f3, 16($sp)
; 32-NEXT: c.ule.s $f3, $f2
; 32-NEXT: jr $ra
; 32-NEXT: movf.d $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 32R2-LABEL: f32_fcmp_ogt_f64_val:
; 32R2: # %bb.0: # %entry
; 32R2-NEXT: mov.d $f0, $f14
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 32R2-NEXT: lwc1 $f2, 20($sp)
; 32R2-NEXT: lwc1 $f3, 16($sp)
; 32R2-NEXT: c.ule.s $f3, $f2
; 32R2-NEXT: jr $ra
; 32R2-NEXT: movf.d $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 32R6-LABEL: f32_fcmp_ogt_f64_val:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: lwc1 $f0, 16($sp)
; 32R6-NEXT: lwc1 $f1, 20($sp)
; 32R6-NEXT: cmp.lt.s $f0, $f1, $f0
; 32R6-NEXT: mfc1 $1, $f0
; 32R6-NEXT: mtc1 $1, $f0
; 32R6-NEXT: jr $ra
; 32R6-NEXT: sel.d $f0, $f14, $f12
;
; 64-LABEL: f32_fcmp_ogt_f64_val:
; 64: # %bb.0: # %entry
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64-NEXT: mov.d $f0, $f13
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 64-NEXT: c.ule.s $f14, $f15
; 64-NEXT: jr $ra
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64-NEXT: movf.d $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 64R2-LABEL: f32_fcmp_ogt_f64_val:
; 64R2: # %bb.0: # %entry
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64R2-NEXT: mov.d $f0, $f13
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 64R2-NEXT: c.ule.s $f14, $f15
; 64R2-NEXT: jr $ra
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64R2-NEXT: movf.d $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 64R6-LABEL: f32_fcmp_ogt_f64_val:
; 64R6: # %bb.0: # %entry
; 64R6-NEXT: cmp.lt.s $f0, $f15, $f14
; 64R6-NEXT: mfc1 $1, $f0
; 64R6-NEXT: mtc1 $1, $f0
; 64R6-NEXT: jr $ra
; 64R6-NEXT: sel.d $f0, $f13, $f12
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
entry:
%cmp = fcmp ogt float %f2, %f3
%cond = select i1 %cmp, double %f0, double %f1
ret double %cond
}
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
define double @f64_fcmp_oeq_f64_val(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 32-LABEL: f64_fcmp_oeq_f64_val:
; 32: # %bb.0: # %entry
; 32-NEXT: mov.d $f0, $f14
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 32-NEXT: ldc1 $f2, 24($sp)
; 32-NEXT: ldc1 $f4, 16($sp)
; 32-NEXT: c.eq.d $f4, $f2
; 32-NEXT: jr $ra
; 32-NEXT: movt.d $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 32R2-LABEL: f64_fcmp_oeq_f64_val:
; 32R2: # %bb.0: # %entry
; 32R2-NEXT: mov.d $f0, $f14
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 32R2-NEXT: ldc1 $f2, 24($sp)
; 32R2-NEXT: ldc1 $f4, 16($sp)
; 32R2-NEXT: c.eq.d $f4, $f2
; 32R2-NEXT: jr $ra
; 32R2-NEXT: movt.d $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 32R6-LABEL: f64_fcmp_oeq_f64_val:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: ldc1 $f0, 24($sp)
; 32R6-NEXT: ldc1 $f1, 16($sp)
; 32R6-NEXT: cmp.eq.d $f0, $f1, $f0
; 32R6-NEXT: mfc1 $1, $f0
; 32R6-NEXT: mtc1 $1, $f0
; 32R6-NEXT: jr $ra
; 32R6-NEXT: sel.d $f0, $f14, $f12
;
; 64-LABEL: f64_fcmp_oeq_f64_val:
; 64: # %bb.0: # %entry
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64-NEXT: mov.d $f0, $f13
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 64-NEXT: c.eq.d $f14, $f15
; 64-NEXT: jr $ra
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64-NEXT: movt.d $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 64R2-LABEL: f64_fcmp_oeq_f64_val:
; 64R2: # %bb.0: # %entry
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64R2-NEXT: mov.d $f0, $f13
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 64R2-NEXT: c.eq.d $f14, $f15
; 64R2-NEXT: jr $ra
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64R2-NEXT: movt.d $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 64R6-LABEL: f64_fcmp_oeq_f64_val:
; 64R6: # %bb.0: # %entry
; 64R6-NEXT: cmp.eq.d $f0, $f14, $f15
; 64R6-NEXT: mfc1 $1, $f0
; 64R6-NEXT: mtc1 $1, $f0
; 64R6-NEXT: jr $ra
; 64R6-NEXT: sel.d $f0, $f13, $f12
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
entry:
%cmp = fcmp oeq double %f2, %f3
%cond = select i1 %cmp, double %f0, double %f1
ret double %cond
}
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
define double @f64_fcmp_olt_f64_val(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 32-LABEL: f64_fcmp_olt_f64_val:
; 32: # %bb.0: # %entry
; 32-NEXT: mov.d $f0, $f14
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 32-NEXT: ldc1 $f2, 24($sp)
; 32-NEXT: ldc1 $f4, 16($sp)
; 32-NEXT: c.olt.d $f4, $f2
; 32-NEXT: jr $ra
; 32-NEXT: movt.d $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 32R2-LABEL: f64_fcmp_olt_f64_val:
; 32R2: # %bb.0: # %entry
; 32R2-NEXT: mov.d $f0, $f14
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 32R2-NEXT: ldc1 $f2, 24($sp)
; 32R2-NEXT: ldc1 $f4, 16($sp)
; 32R2-NEXT: c.olt.d $f4, $f2
; 32R2-NEXT: jr $ra
; 32R2-NEXT: movt.d $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 32R6-LABEL: f64_fcmp_olt_f64_val:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: ldc1 $f0, 24($sp)
; 32R6-NEXT: ldc1 $f1, 16($sp)
; 32R6-NEXT: cmp.lt.d $f0, $f1, $f0
; 32R6-NEXT: mfc1 $1, $f0
; 32R6-NEXT: mtc1 $1, $f0
; 32R6-NEXT: jr $ra
; 32R6-NEXT: sel.d $f0, $f14, $f12
;
; 64-LABEL: f64_fcmp_olt_f64_val:
; 64: # %bb.0: # %entry
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64-NEXT: mov.d $f0, $f13
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 64-NEXT: c.olt.d $f14, $f15
; 64-NEXT: jr $ra
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64-NEXT: movt.d $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 64R2-LABEL: f64_fcmp_olt_f64_val:
; 64R2: # %bb.0: # %entry
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64R2-NEXT: mov.d $f0, $f13
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 64R2-NEXT: c.olt.d $f14, $f15
; 64R2-NEXT: jr $ra
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64R2-NEXT: movt.d $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 64R6-LABEL: f64_fcmp_olt_f64_val:
; 64R6: # %bb.0: # %entry
; 64R6-NEXT: cmp.lt.d $f0, $f14, $f15
; 64R6-NEXT: mfc1 $1, $f0
; 64R6-NEXT: mtc1 $1, $f0
; 64R6-NEXT: jr $ra
; 64R6-NEXT: sel.d $f0, $f13, $f12
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
entry:
%cmp = fcmp olt double %f2, %f3
%cond = select i1 %cmp, double %f0, double %f1
ret double %cond
}
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
define double @f64_fcmp_ogt_f64_val(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 32-LABEL: f64_fcmp_ogt_f64_val:
; 32: # %bb.0: # %entry
; 32-NEXT: mov.d $f0, $f14
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 32-NEXT: ldc1 $f2, 24($sp)
; 32-NEXT: ldc1 $f4, 16($sp)
; 32-NEXT: c.ule.d $f4, $f2
; 32-NEXT: jr $ra
; 32-NEXT: movf.d $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 32R2-LABEL: f64_fcmp_ogt_f64_val:
; 32R2: # %bb.0: # %entry
; 32R2-NEXT: mov.d $f0, $f14
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 32R2-NEXT: ldc1 $f2, 24($sp)
; 32R2-NEXT: ldc1 $f4, 16($sp)
; 32R2-NEXT: c.ule.d $f4, $f2
; 32R2-NEXT: jr $ra
; 32R2-NEXT: movf.d $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 32R6-LABEL: f64_fcmp_ogt_f64_val:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: ldc1 $f0, 16($sp)
; 32R6-NEXT: ldc1 $f1, 24($sp)
; 32R6-NEXT: cmp.lt.d $f0, $f1, $f0
; 32R6-NEXT: mfc1 $1, $f0
; 32R6-NEXT: mtc1 $1, $f0
; 32R6-NEXT: jr $ra
; 32R6-NEXT: sel.d $f0, $f14, $f12
;
; 64-LABEL: f64_fcmp_ogt_f64_val:
; 64: # %bb.0: # %entry
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64-NEXT: mov.d $f0, $f13
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 64-NEXT: c.ule.d $f14, $f15
; 64-NEXT: jr $ra
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64-NEXT: movf.d $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 64R2-LABEL: f64_fcmp_ogt_f64_val:
; 64R2: # %bb.0: # %entry
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64R2-NEXT: mov.d $f0, $f13
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 64R2-NEXT: c.ule.d $f14, $f15
; 64R2-NEXT: jr $ra
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64R2-NEXT: movf.d $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 64R6-LABEL: f64_fcmp_ogt_f64_val:
; 64R6: # %bb.0: # %entry
; 64R6-NEXT: cmp.lt.d $f0, $f15, $f14
; 64R6-NEXT: mfc1 $1, $f0
; 64R6-NEXT: mtc1 $1, $f0
; 64R6-NEXT: jr $ra
; 64R6-NEXT: sel.d $f0, $f13, $f12
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
entry:
%cmp = fcmp ogt double %f2, %f3
%cond = select i1 %cmp, double %f0, double %f1
ret double %cond
}
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
define float @f64_fcmp_ogt_f32_val(float %f0, float %f1, double %f2, double %f3) nounwind readnone {
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 32-LABEL: f64_fcmp_ogt_f32_val:
; 32: # %bb.0: # %entry
; 32-NEXT: mov.s $f0, $f14
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 32-NEXT: mtc1 $6, $f2
; 32-NEXT: mtc1 $7, $f3
; 32-NEXT: ldc1 $f4, 16($sp)
; 32-NEXT: c.ule.d $f2, $f4
; 32-NEXT: jr $ra
; 32-NEXT: movf.s $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 32R2-LABEL: f64_fcmp_ogt_f32_val:
; 32R2: # %bb.0: # %entry
; 32R2-NEXT: mov.s $f0, $f14
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 32R2-NEXT: mtc1 $6, $f2
; 32R2-NEXT: mthc1 $7, $f2
; 32R2-NEXT: ldc1 $f4, 16($sp)
; 32R2-NEXT: c.ule.d $f2, $f4
; 32R2-NEXT: jr $ra
; 32R2-NEXT: movf.s $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 32R6-LABEL: f64_fcmp_ogt_f32_val:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: mtc1 $6, $f0
; 32R6-NEXT: mthc1 $7, $f0
; 32R6-NEXT: ldc1 $f1, 16($sp)
; 32R6-NEXT: cmp.lt.d $f0, $f1, $f0
; 32R6-NEXT: jr $ra
; 32R6-NEXT: sel.s $f0, $f14, $f12
;
; 64-LABEL: f64_fcmp_ogt_f32_val:
; 64: # %bb.0: # %entry
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64-NEXT: mov.s $f0, $f13
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 64-NEXT: c.ule.d $f14, $f15
; 64-NEXT: jr $ra
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64-NEXT: movf.s $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 64R2-LABEL: f64_fcmp_ogt_f32_val:
; 64R2: # %bb.0: # %entry
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64R2-NEXT: mov.s $f0, $f13
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 64R2-NEXT: c.ule.d $f14, $f15
; 64R2-NEXT: jr $ra
[Mips] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Simon Dardis llvm-svn: 325870
2018-02-23 16:30:15 +08:00
; 64R2-NEXT: movf.s $f0, $f12, $fcc0
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
;
; 64R6-LABEL: f64_fcmp_ogt_f32_val:
; 64R6: # %bb.0: # %entry
; 64R6-NEXT: cmp.lt.d $f0, $f15, $f14
; 64R6-NEXT: jr $ra
; 64R6-NEXT: sel.s $f0, $f13, $f12
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
entry:
%cmp = fcmp ogt double %f2, %f3
%cond = select i1 %cmp, float %f0, float %f1
ret float %cond
}
[mips] Promote i32 arguments to i64 for the N32/N64 ABI and fix <64-bit structs... Summary: ... and after all that refactoring, it's possible to distinguish softfloat floating point values from integers so this patch no longer breaks softfloat to do it. Remove direct handling of i32's in the N32/N64 ABI by promoting them to i64. This more closely reflects the ABI documentation and also fixes problems with stack arguments on big-endian targets. We now rely on signext/zeroext annotations (already generated by clang) and the Assert[SZ]ext nodes to avoid the introduction of unnecessary sign/zero extends. It was not possible to convert three tests to use signext/zeroext. These tests are bswap.ll, ctlz-v.ll, ctlz-v.ll. It's not possible to put signext on a vector type so we just accept the sign extends here for now. These tests don't pass the vectors the same way clang does (clang puts multiple elements in the same argument, these map 1 element to 1 argument) so we don't need to worry too much about it. With this patch, all known N32/N64 bugs should be fixed and we now pass the first 10,000 tests generated by ABITest.py. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6117 llvm-svn: 221534
2014-11-08 00:54:21 +08:00
define i32 @f32_fcmp_oeq_i32_val(i32 signext %f0, i32 signext %f1, float %f2, float %f3) nounwind readnone {
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 32-LABEL: f32_fcmp_oeq_i32_val:
; 32: # %bb.0: # %entry
; 32-NEXT: mtc1 $7, $f0
; 32-NEXT: mtc1 $6, $f1
; 32-NEXT: c.eq.s $f1, $f0
; 32-NEXT: movt $5, $4, $fcc0
; 32-NEXT: jr $ra
; 32-NEXT: move $2, $5
;
; 32R2-LABEL: f32_fcmp_oeq_i32_val:
; 32R2: # %bb.0: # %entry
; 32R2-NEXT: mtc1 $7, $f0
; 32R2-NEXT: mtc1 $6, $f1
; 32R2-NEXT: c.eq.s $f1, $f0
; 32R2-NEXT: movt $5, $4, $fcc0
; 32R2-NEXT: jr $ra
; 32R2-NEXT: move $2, $5
;
; 32R6-LABEL: f32_fcmp_oeq_i32_val:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: mtc1 $7, $f0
; 32R6-NEXT: mtc1 $6, $f1
; 32R6-NEXT: cmp.eq.s $f0, $f1, $f0
; 32R6-NEXT: mfc1 $1, $f0
; 32R6-NEXT: andi $1, $1, 1
; 32R6-NEXT: seleqz $2, $5, $1
; 32R6-NEXT: selnez $1, $4, $1
; 32R6-NEXT: jr $ra
; 32R6-NEXT: or $2, $1, $2
;
; 64-LABEL: f32_fcmp_oeq_i32_val:
; 64: # %bb.0: # %entry
; 64-NEXT: c.eq.s $f14, $f15
; 64-NEXT: movt $5, $4, $fcc0
; 64-NEXT: jr $ra
; 64-NEXT: move $2, $5
;
; 64R2-LABEL: f32_fcmp_oeq_i32_val:
; 64R2: # %bb.0: # %entry
; 64R2-NEXT: c.eq.s $f14, $f15
; 64R2-NEXT: movt $5, $4, $fcc0
; 64R2-NEXT: jr $ra
; 64R2-NEXT: move $2, $5
;
; 64R6-LABEL: f32_fcmp_oeq_i32_val:
; 64R6: # %bb.0: # %entry
; 64R6-NEXT: cmp.eq.s $f0, $f14, $f15
; 64R6-NEXT: mfc1 $1, $f0
; 64R6-NEXT: andi $1, $1, 1
; 64R6-NEXT: seleqz $2, $5, $1
; 64R6-NEXT: selnez $1, $4, $1
; 64R6-NEXT: jr $ra
; 64R6-NEXT: or $2, $1, $2
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
entry:
%cmp = fcmp oeq float %f2, %f3
%cond = select i1 %cmp, i32 %f0, i32 %f1
ret i32 %cond
}
[mips] Promote i32 arguments to i64 for the N32/N64 ABI and fix <64-bit structs... Summary: ... and after all that refactoring, it's possible to distinguish softfloat floating point values from integers so this patch no longer breaks softfloat to do it. Remove direct handling of i32's in the N32/N64 ABI by promoting them to i64. This more closely reflects the ABI documentation and also fixes problems with stack arguments on big-endian targets. We now rely on signext/zeroext annotations (already generated by clang) and the Assert[SZ]ext nodes to avoid the introduction of unnecessary sign/zero extends. It was not possible to convert three tests to use signext/zeroext. These tests are bswap.ll, ctlz-v.ll, ctlz-v.ll. It's not possible to put signext on a vector type so we just accept the sign extends here for now. These tests don't pass the vectors the same way clang does (clang puts multiple elements in the same argument, these map 1 element to 1 argument) so we don't need to worry too much about it. With this patch, all known N32/N64 bugs should be fixed and we now pass the first 10,000 tests generated by ABITest.py. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6117 llvm-svn: 221534
2014-11-08 00:54:21 +08:00
define i32 @f32_fcmp_olt_i32_val(i32 signext %f0, i32 signext %f1, float %f2, float %f3) nounwind readnone {
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 32-LABEL: f32_fcmp_olt_i32_val:
; 32: # %bb.0: # %entry
; 32-NEXT: mtc1 $7, $f0
; 32-NEXT: mtc1 $6, $f1
; 32-NEXT: c.olt.s $f1, $f0
; 32-NEXT: movt $5, $4, $fcc0
; 32-NEXT: jr $ra
; 32-NEXT: move $2, $5
;
; 32R2-LABEL: f32_fcmp_olt_i32_val:
; 32R2: # %bb.0: # %entry
; 32R2-NEXT: mtc1 $7, $f0
; 32R2-NEXT: mtc1 $6, $f1
; 32R2-NEXT: c.olt.s $f1, $f0
; 32R2-NEXT: movt $5, $4, $fcc0
; 32R2-NEXT: jr $ra
; 32R2-NEXT: move $2, $5
;
; 32R6-LABEL: f32_fcmp_olt_i32_val:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: mtc1 $7, $f0
; 32R6-NEXT: mtc1 $6, $f1
; 32R6-NEXT: cmp.lt.s $f0, $f1, $f0
; 32R6-NEXT: mfc1 $1, $f0
; 32R6-NEXT: andi $1, $1, 1
; 32R6-NEXT: seleqz $2, $5, $1
; 32R6-NEXT: selnez $1, $4, $1
; 32R6-NEXT: jr $ra
; 32R6-NEXT: or $2, $1, $2
;
; 64-LABEL: f32_fcmp_olt_i32_val:
; 64: # %bb.0: # %entry
; 64-NEXT: c.olt.s $f14, $f15
; 64-NEXT: movt $5, $4, $fcc0
; 64-NEXT: jr $ra
; 64-NEXT: move $2, $5
;
; 64R2-LABEL: f32_fcmp_olt_i32_val:
; 64R2: # %bb.0: # %entry
; 64R2-NEXT: c.olt.s $f14, $f15
; 64R2-NEXT: movt $5, $4, $fcc0
; 64R2-NEXT: jr $ra
; 64R2-NEXT: move $2, $5
;
; 64R6-LABEL: f32_fcmp_olt_i32_val:
; 64R6: # %bb.0: # %entry
; 64R6-NEXT: cmp.lt.s $f0, $f14, $f15
; 64R6-NEXT: mfc1 $1, $f0
; 64R6-NEXT: andi $1, $1, 1
; 64R6-NEXT: seleqz $2, $5, $1
; 64R6-NEXT: selnez $1, $4, $1
; 64R6-NEXT: jr $ra
; 64R6-NEXT: or $2, $1, $2
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
entry:
%cmp = fcmp olt float %f2, %f3
%cond = select i1 %cmp, i32 %f0, i32 %f1
ret i32 %cond
}
[mips] Promote i32 arguments to i64 for the N32/N64 ABI and fix <64-bit structs... Summary: ... and after all that refactoring, it's possible to distinguish softfloat floating point values from integers so this patch no longer breaks softfloat to do it. Remove direct handling of i32's in the N32/N64 ABI by promoting them to i64. This more closely reflects the ABI documentation and also fixes problems with stack arguments on big-endian targets. We now rely on signext/zeroext annotations (already generated by clang) and the Assert[SZ]ext nodes to avoid the introduction of unnecessary sign/zero extends. It was not possible to convert three tests to use signext/zeroext. These tests are bswap.ll, ctlz-v.ll, ctlz-v.ll. It's not possible to put signext on a vector type so we just accept the sign extends here for now. These tests don't pass the vectors the same way clang does (clang puts multiple elements in the same argument, these map 1 element to 1 argument) so we don't need to worry too much about it. With this patch, all known N32/N64 bugs should be fixed and we now pass the first 10,000 tests generated by ABITest.py. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6117 llvm-svn: 221534
2014-11-08 00:54:21 +08:00
define i32 @f32_fcmp_ogt_i32_val(i32 signext %f0, i32 signext %f1, float %f2, float %f3) nounwind readnone {
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 32-LABEL: f32_fcmp_ogt_i32_val:
; 32: # %bb.0: # %entry
; 32-NEXT: mtc1 $7, $f0
; 32-NEXT: mtc1 $6, $f1
; 32-NEXT: c.ule.s $f1, $f0
; 32-NEXT: movf $5, $4, $fcc0
; 32-NEXT: jr $ra
; 32-NEXT: move $2, $5
;
; 32R2-LABEL: f32_fcmp_ogt_i32_val:
; 32R2: # %bb.0: # %entry
; 32R2-NEXT: mtc1 $7, $f0
; 32R2-NEXT: mtc1 $6, $f1
; 32R2-NEXT: c.ule.s $f1, $f0
; 32R2-NEXT: movf $5, $4, $fcc0
; 32R2-NEXT: jr $ra
; 32R2-NEXT: move $2, $5
;
; 32R6-LABEL: f32_fcmp_ogt_i32_val:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: mtc1 $6, $f0
; 32R6-NEXT: mtc1 $7, $f1
; 32R6-NEXT: cmp.lt.s $f0, $f1, $f0
; 32R6-NEXT: mfc1 $1, $f0
; 32R6-NEXT: andi $1, $1, 1
; 32R6-NEXT: seleqz $2, $5, $1
; 32R6-NEXT: selnez $1, $4, $1
; 32R6-NEXT: jr $ra
; 32R6-NEXT: or $2, $1, $2
;
; 64-LABEL: f32_fcmp_ogt_i32_val:
; 64: # %bb.0: # %entry
; 64-NEXT: c.ule.s $f14, $f15
; 64-NEXT: movf $5, $4, $fcc0
; 64-NEXT: jr $ra
; 64-NEXT: move $2, $5
;
; 64R2-LABEL: f32_fcmp_ogt_i32_val:
; 64R2: # %bb.0: # %entry
; 64R2-NEXT: c.ule.s $f14, $f15
; 64R2-NEXT: movf $5, $4, $fcc0
; 64R2-NEXT: jr $ra
; 64R2-NEXT: move $2, $5
;
; 64R6-LABEL: f32_fcmp_ogt_i32_val:
; 64R6: # %bb.0: # %entry
; 64R6-NEXT: cmp.lt.s $f0, $f15, $f14
; 64R6-NEXT: mfc1 $1, $f0
; 64R6-NEXT: andi $1, $1, 1
; 64R6-NEXT: seleqz $2, $5, $1
; 64R6-NEXT: selnez $1, $4, $1
; 64R6-NEXT: jr $ra
; 64R6-NEXT: or $2, $1, $2
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
entry:
%cmp = fcmp ogt float %f2, %f3
%cond = select i1 %cmp, i32 %f0, i32 %f1
ret i32 %cond
}
[mips] Promote i32 arguments to i64 for the N32/N64 ABI and fix <64-bit structs... Summary: ... and after all that refactoring, it's possible to distinguish softfloat floating point values from integers so this patch no longer breaks softfloat to do it. Remove direct handling of i32's in the N32/N64 ABI by promoting them to i64. This more closely reflects the ABI documentation and also fixes problems with stack arguments on big-endian targets. We now rely on signext/zeroext annotations (already generated by clang) and the Assert[SZ]ext nodes to avoid the introduction of unnecessary sign/zero extends. It was not possible to convert three tests to use signext/zeroext. These tests are bswap.ll, ctlz-v.ll, ctlz-v.ll. It's not possible to put signext on a vector type so we just accept the sign extends here for now. These tests don't pass the vectors the same way clang does (clang puts multiple elements in the same argument, these map 1 element to 1 argument) so we don't need to worry too much about it. With this patch, all known N32/N64 bugs should be fixed and we now pass the first 10,000 tests generated by ABITest.py. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6117 llvm-svn: 221534
2014-11-08 00:54:21 +08:00
define i32 @f64_fcmp_oeq_i32_val(i32 signext %f0, i32 signext %f1) nounwind readonly {
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 32-LABEL: f64_fcmp_oeq_i32_val:
; 32: # %bb.0: # %entry
; 32-NEXT: lui $2, %hi(_gp_disp)
; 32-NEXT: addiu $2, $2, %lo(_gp_disp)
; 32-NEXT: addu $1, $2, $25
; 32-NEXT: lw $2, %got(d3)($1)
; 32-NEXT: ldc1 $f0, 0($2)
; 32-NEXT: lw $1, %got(d2)($1)
; 32-NEXT: ldc1 $f2, 0($1)
; 32-NEXT: c.eq.d $f2, $f0
; 32-NEXT: movt $5, $4, $fcc0
; 32-NEXT: jr $ra
; 32-NEXT: move $2, $5
;
; 32R2-LABEL: f64_fcmp_oeq_i32_val:
; 32R2: # %bb.0: # %entry
; 32R2-NEXT: lui $2, %hi(_gp_disp)
; 32R2-NEXT: addiu $2, $2, %lo(_gp_disp)
; 32R2-NEXT: addu $1, $2, $25
; 32R2-NEXT: lw $2, %got(d3)($1)
; 32R2-NEXT: ldc1 $f0, 0($2)
; 32R2-NEXT: lw $1, %got(d2)($1)
; 32R2-NEXT: ldc1 $f2, 0($1)
; 32R2-NEXT: c.eq.d $f2, $f0
; 32R2-NEXT: movt $5, $4, $fcc0
; 32R2-NEXT: jr $ra
; 32R2-NEXT: move $2, $5
;
; 32R6-LABEL: f64_fcmp_oeq_i32_val:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: lui $2, %hi(_gp_disp)
; 32R6-NEXT: addiu $2, $2, %lo(_gp_disp)
; 32R6-NEXT: addu $1, $2, $25
; 32R6-NEXT: lw $2, %got(d3)($1)
; 32R6-NEXT: ldc1 $f0, 0($2)
; 32R6-NEXT: lw $1, %got(d2)($1)
; 32R6-NEXT: ldc1 $f1, 0($1)
; 32R6-NEXT: cmp.eq.d $f0, $f1, $f0
; 32R6-NEXT: mfc1 $1, $f0
; 32R6-NEXT: andi $1, $1, 1
; 32R6-NEXT: seleqz $2, $5, $1
; 32R6-NEXT: selnez $1, $4, $1
; 32R6-NEXT: jr $ra
; 32R6-NEXT: or $2, $1, $2
;
; 64-LABEL: f64_fcmp_oeq_i32_val:
; 64: # %bb.0: # %entry
; 64-NEXT: lui $1, %hi(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
; 64-NEXT: daddu $1, $1, $25
; 64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
; 64-NEXT: ld $2, %got_disp(d3)($1)
; 64-NEXT: ldc1 $f0, 0($2)
; 64-NEXT: ld $1, %got_disp(d2)($1)
; 64-NEXT: ldc1 $f1, 0($1)
; 64-NEXT: c.eq.d $f1, $f0
; 64-NEXT: movt $5, $4, $fcc0
; 64-NEXT: jr $ra
; 64-NEXT: move $2, $5
;
; 64R2-LABEL: f64_fcmp_oeq_i32_val:
; 64R2: # %bb.0: # %entry
; 64R2-NEXT: lui $1, %hi(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
; 64R2-NEXT: daddu $1, $1, $25
; 64R2-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
; 64R2-NEXT: ld $2, %got_disp(d3)($1)
; 64R2-NEXT: ldc1 $f0, 0($2)
; 64R2-NEXT: ld $1, %got_disp(d2)($1)
; 64R2-NEXT: ldc1 $f1, 0($1)
; 64R2-NEXT: c.eq.d $f1, $f0
; 64R2-NEXT: movt $5, $4, $fcc0
; 64R2-NEXT: jr $ra
; 64R2-NEXT: move $2, $5
;
; 64R6-LABEL: f64_fcmp_oeq_i32_val:
; 64R6: # %bb.0: # %entry
; 64R6-NEXT: lui $1, %hi(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
; 64R6-NEXT: daddu $1, $1, $25
; 64R6-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
; 64R6-NEXT: ld $2, %got_disp(d3)($1)
; 64R6-NEXT: ldc1 $f0, 0($2)
; 64R6-NEXT: ld $1, %got_disp(d2)($1)
; 64R6-NEXT: ldc1 $f1, 0($1)
; 64R6-NEXT: cmp.eq.d $f0, $f1, $f0
; 64R6-NEXT: mfc1 $1, $f0
; 64R6-NEXT: andi $1, $1, 1
; 64R6-NEXT: seleqz $2, $5, $1
; 64R6-NEXT: selnez $1, $4, $1
; 64R6-NEXT: jr $ra
; 64R6-NEXT: or $2, $1, $2
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp = load double, double* @d2, align 8
%tmp1 = load double, double* @d3, align 8
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
%cmp = fcmp oeq double %tmp, %tmp1
%cond = select i1 %cmp, i32 %f0, i32 %f1
ret i32 %cond
}
[mips] Promote i32 arguments to i64 for the N32/N64 ABI and fix <64-bit structs... Summary: ... and after all that refactoring, it's possible to distinguish softfloat floating point values from integers so this patch no longer breaks softfloat to do it. Remove direct handling of i32's in the N32/N64 ABI by promoting them to i64. This more closely reflects the ABI documentation and also fixes problems with stack arguments on big-endian targets. We now rely on signext/zeroext annotations (already generated by clang) and the Assert[SZ]ext nodes to avoid the introduction of unnecessary sign/zero extends. It was not possible to convert three tests to use signext/zeroext. These tests are bswap.ll, ctlz-v.ll, ctlz-v.ll. It's not possible to put signext on a vector type so we just accept the sign extends here for now. These tests don't pass the vectors the same way clang does (clang puts multiple elements in the same argument, these map 1 element to 1 argument) so we don't need to worry too much about it. With this patch, all known N32/N64 bugs should be fixed and we now pass the first 10,000 tests generated by ABITest.py. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6117 llvm-svn: 221534
2014-11-08 00:54:21 +08:00
define i32 @f64_fcmp_olt_i32_val(i32 signext %f0, i32 signext %f1) nounwind readonly {
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 32-LABEL: f64_fcmp_olt_i32_val:
; 32: # %bb.0: # %entry
; 32-NEXT: lui $2, %hi(_gp_disp)
; 32-NEXT: addiu $2, $2, %lo(_gp_disp)
; 32-NEXT: addu $1, $2, $25
; 32-NEXT: lw $2, %got(d3)($1)
; 32-NEXT: ldc1 $f0, 0($2)
; 32-NEXT: lw $1, %got(d2)($1)
; 32-NEXT: ldc1 $f2, 0($1)
; 32-NEXT: c.olt.d $f2, $f0
; 32-NEXT: movt $5, $4, $fcc0
; 32-NEXT: jr $ra
; 32-NEXT: move $2, $5
;
; 32R2-LABEL: f64_fcmp_olt_i32_val:
; 32R2: # %bb.0: # %entry
; 32R2-NEXT: lui $2, %hi(_gp_disp)
; 32R2-NEXT: addiu $2, $2, %lo(_gp_disp)
; 32R2-NEXT: addu $1, $2, $25
; 32R2-NEXT: lw $2, %got(d3)($1)
; 32R2-NEXT: ldc1 $f0, 0($2)
; 32R2-NEXT: lw $1, %got(d2)($1)
; 32R2-NEXT: ldc1 $f2, 0($1)
; 32R2-NEXT: c.olt.d $f2, $f0
; 32R2-NEXT: movt $5, $4, $fcc0
; 32R2-NEXT: jr $ra
; 32R2-NEXT: move $2, $5
;
; 32R6-LABEL: f64_fcmp_olt_i32_val:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: lui $2, %hi(_gp_disp)
; 32R6-NEXT: addiu $2, $2, %lo(_gp_disp)
; 32R6-NEXT: addu $1, $2, $25
; 32R6-NEXT: lw $2, %got(d3)($1)
; 32R6-NEXT: ldc1 $f0, 0($2)
; 32R6-NEXT: lw $1, %got(d2)($1)
; 32R6-NEXT: ldc1 $f1, 0($1)
; 32R6-NEXT: cmp.lt.d $f0, $f1, $f0
; 32R6-NEXT: mfc1 $1, $f0
; 32R6-NEXT: andi $1, $1, 1
; 32R6-NEXT: seleqz $2, $5, $1
; 32R6-NEXT: selnez $1, $4, $1
; 32R6-NEXT: jr $ra
; 32R6-NEXT: or $2, $1, $2
;
; 64-LABEL: f64_fcmp_olt_i32_val:
; 64: # %bb.0: # %entry
; 64-NEXT: lui $1, %hi(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
; 64-NEXT: daddu $1, $1, $25
; 64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
; 64-NEXT: ld $2, %got_disp(d3)($1)
; 64-NEXT: ldc1 $f0, 0($2)
; 64-NEXT: ld $1, %got_disp(d2)($1)
; 64-NEXT: ldc1 $f1, 0($1)
; 64-NEXT: c.olt.d $f1, $f0
; 64-NEXT: movt $5, $4, $fcc0
; 64-NEXT: jr $ra
; 64-NEXT: move $2, $5
;
; 64R2-LABEL: f64_fcmp_olt_i32_val:
; 64R2: # %bb.0: # %entry
; 64R2-NEXT: lui $1, %hi(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
; 64R2-NEXT: daddu $1, $1, $25
; 64R2-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
; 64R2-NEXT: ld $2, %got_disp(d3)($1)
; 64R2-NEXT: ldc1 $f0, 0($2)
; 64R2-NEXT: ld $1, %got_disp(d2)($1)
; 64R2-NEXT: ldc1 $f1, 0($1)
; 64R2-NEXT: c.olt.d $f1, $f0
; 64R2-NEXT: movt $5, $4, $fcc0
; 64R2-NEXT: jr $ra
; 64R2-NEXT: move $2, $5
;
; 64R6-LABEL: f64_fcmp_olt_i32_val:
; 64R6: # %bb.0: # %entry
; 64R6-NEXT: lui $1, %hi(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
; 64R6-NEXT: daddu $1, $1, $25
; 64R6-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
; 64R6-NEXT: ld $2, %got_disp(d3)($1)
; 64R6-NEXT: ldc1 $f0, 0($2)
; 64R6-NEXT: ld $1, %got_disp(d2)($1)
; 64R6-NEXT: ldc1 $f1, 0($1)
; 64R6-NEXT: cmp.lt.d $f0, $f1, $f0
; 64R6-NEXT: mfc1 $1, $f0
; 64R6-NEXT: andi $1, $1, 1
; 64R6-NEXT: seleqz $2, $5, $1
; 64R6-NEXT: selnez $1, $4, $1
; 64R6-NEXT: jr $ra
; 64R6-NEXT: or $2, $1, $2
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp = load double, double* @d2, align 8
%tmp1 = load double, double* @d3, align 8
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
%cmp = fcmp olt double %tmp, %tmp1
%cond = select i1 %cmp, i32 %f0, i32 %f1
ret i32 %cond
}
[mips] Promote i32 arguments to i64 for the N32/N64 ABI and fix <64-bit structs... Summary: ... and after all that refactoring, it's possible to distinguish softfloat floating point values from integers so this patch no longer breaks softfloat to do it. Remove direct handling of i32's in the N32/N64 ABI by promoting them to i64. This more closely reflects the ABI documentation and also fixes problems with stack arguments on big-endian targets. We now rely on signext/zeroext annotations (already generated by clang) and the Assert[SZ]ext nodes to avoid the introduction of unnecessary sign/zero extends. It was not possible to convert three tests to use signext/zeroext. These tests are bswap.ll, ctlz-v.ll, ctlz-v.ll. It's not possible to put signext on a vector type so we just accept the sign extends here for now. These tests don't pass the vectors the same way clang does (clang puts multiple elements in the same argument, these map 1 element to 1 argument) so we don't need to worry too much about it. With this patch, all known N32/N64 bugs should be fixed and we now pass the first 10,000 tests generated by ABITest.py. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6117 llvm-svn: 221534
2014-11-08 00:54:21 +08:00
define i32 @f64_fcmp_ogt_i32_val(i32 signext %f0, i32 signext %f1) nounwind readonly {
[mips] Regenerate tests for D38128 (NFC) llvm-svn: 325770
2018-02-22 19:53:01 +08:00
; 32-LABEL: f64_fcmp_ogt_i32_val:
; 32: # %bb.0: # %entry
; 32-NEXT: lui $2, %hi(_gp_disp)
; 32-NEXT: addiu $2, $2, %lo(_gp_disp)
; 32-NEXT: addu $1, $2, $25
; 32-NEXT: lw $2, %got(d3)($1)
; 32-NEXT: ldc1 $f0, 0($2)
; 32-NEXT: lw $1, %got(d2)($1)
; 32-NEXT: ldc1 $f2, 0($1)
; 32-NEXT: c.ule.d $f2, $f0
; 32-NEXT: movf $5, $4, $fcc0
; 32-NEXT: jr $ra
; 32-NEXT: move $2, $5
;
; 32R2-LABEL: f64_fcmp_ogt_i32_val:
; 32R2: # %bb.0: # %entry
; 32R2-NEXT: lui $2, %hi(_gp_disp)
; 32R2-NEXT: addiu $2, $2, %lo(_gp_disp)
; 32R2-NEXT: addu $1, $2, $25
; 32R2-NEXT: lw $2, %got(d3)($1)
; 32R2-NEXT: ldc1 $f0, 0($2)
; 32R2-NEXT: lw $1, %got(d2)($1)
; 32R2-NEXT: ldc1 $f2, 0($1)
; 32R2-NEXT: c.ule.d $f2, $f0
; 32R2-NEXT: movf $5, $4, $fcc0
; 32R2-NEXT: jr $ra
; 32R2-NEXT: move $2, $5
;
; 32R6-LABEL: f64_fcmp_ogt_i32_val:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: lui $2, %hi(_gp_disp)
; 32R6-NEXT: addiu $2, $2, %lo(_gp_disp)
; 32R6-NEXT: addu $1, $2, $25
; 32R6-NEXT: lw $2, %got(d2)($1)
; 32R6-NEXT: ldc1 $f0, 0($2)
; 32R6-NEXT: lw $1, %got(d3)($1)
; 32R6-NEXT: ldc1 $f1, 0($1)
; 32R6-NEXT: cmp.lt.d $f0, $f1, $f0
; 32R6-NEXT: mfc1 $1, $f0
; 32R6-NEXT: andi $1, $1, 1
; 32R6-NEXT: seleqz $2, $5, $1
; 32R6-NEXT: selnez $1, $4, $1
; 32R6-NEXT: jr $ra
; 32R6-NEXT: or $2, $1, $2
;
; 64-LABEL: f64_fcmp_ogt_i32_val:
; 64: # %bb.0: # %entry
; 64-NEXT: lui $1, %hi(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
; 64-NEXT: daddu $1, $1, $25
; 64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
; 64-NEXT: ld $2, %got_disp(d3)($1)
; 64-NEXT: ldc1 $f0, 0($2)
; 64-NEXT: ld $1, %got_disp(d2)($1)
; 64-NEXT: ldc1 $f1, 0($1)
; 64-NEXT: c.ule.d $f1, $f0
; 64-NEXT: movf $5, $4, $fcc0
; 64-NEXT: jr $ra
; 64-NEXT: move $2, $5
;
; 64R2-LABEL: f64_fcmp_ogt_i32_val:
; 64R2: # %bb.0: # %entry
; 64R2-NEXT: lui $1, %hi(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
; 64R2-NEXT: daddu $1, $1, $25
; 64R2-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
; 64R2-NEXT: ld $2, %got_disp(d3)($1)
; 64R2-NEXT: ldc1 $f0, 0($2)
; 64R2-NEXT: ld $1, %got_disp(d2)($1)
; 64R2-NEXT: ldc1 $f1, 0($1)
; 64R2-NEXT: c.ule.d $f1, $f0
; 64R2-NEXT: movf $5, $4, $fcc0
; 64R2-NEXT: jr $ra
; 64R2-NEXT: move $2, $5
;
; 64R6-LABEL: f64_fcmp_ogt_i32_val:
; 64R6: # %bb.0: # %entry
; 64R6-NEXT: lui $1, %hi(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
; 64R6-NEXT: daddu $1, $1, $25
; 64R6-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
; 64R6-NEXT: ld $2, %got_disp(d2)($1)
; 64R6-NEXT: ldc1 $f0, 0($2)
; 64R6-NEXT: ld $1, %got_disp(d3)($1)
; 64R6-NEXT: ldc1 $f1, 0($1)
; 64R6-NEXT: cmp.lt.d $f0, $f1, $f0
; 64R6-NEXT: mfc1 $1, $f0
; 64R6-NEXT: andi $1, $1, 1
; 64R6-NEXT: seleqz $2, $5, $1
; 64R6-NEXT: selnez $1, $4, $1
; 64R6-NEXT: jr $ra
; 64R6-NEXT: or $2, $1, $2
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp = load double, double* @d2, align 8
%tmp1 = load double, double* @d3, align 8
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650
2011-04-01 02:26:17 +08:00
%cmp = fcmp ogt double %tmp, %tmp1
%cond = select i1 %cmp, i32 %f0, i32 %f1
ret i32 %cond
}