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llvm-project/llvm/test/CodeGen/Mips/blez_bgez.ll

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[mips] Add microMIPS case to the tests and regenerate assertions using update_llc_test_checks.py. NFC llvm-svn: 337004
2018-07-13 23:03:24 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[mips] Add instruction selection patterns for blez and bgez. llvm-svn: 182396
2013-05-22 01:13:47 +08:00
[mips] Add microMIPS case to the tests and regenerate assertions using update_llc_test_checks.py. NFC llvm-svn: 337004
2018-07-13 23:03:24 +08:00
; Test that blez/ bgez are selected.
; RUN: llc -mtriple=mipsel-mti-linux-gnu < %s | FileCheck %s --check-prefix=MIPS32
; RUN: llc -mtriple=mips64el-mti-linux-gnu < %s | FileCheck %s --check-prefix=MIPS64
; RUN: llc -mtriple=mipsel-mti-linux-gnu -mattr=+micromips < %s | FileCheck %s --check-prefix=MM
[mips] Add instruction selection patterns for blez and bgez. llvm-svn: 182396
2013-05-22 01:13:47 +08:00
define void @test_blez(i32 %a) {
[mips] Add microMIPS case to the tests and regenerate assertions using update_llc_test_checks.py. NFC llvm-svn: 337004
2018-07-13 23:03:24 +08:00
; MIPS32-LABEL: test_blez:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: blez $4, $BB0_2
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.1: # %if.then
; MIPS32-NEXT: addiu $sp, $sp, -24
; MIPS32-NEXT: .cfi_def_cfa_offset 24
; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: .cfi_offset 31, -4
; MIPS32-NEXT: jal foo1
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 24
; MIPS32-NEXT: $BB0_2: # %if.end
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS64-LABEL: test_blez:
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: sll $1, $4, 0
; MIPS64-NEXT: blez $1, .LBB0_2
; MIPS64-NEXT: nop
; MIPS64-NEXT: # %bb.1: # %if.then
; MIPS64-NEXT: daddiu $sp, $sp, -16
; MIPS64-NEXT: .cfi_def_cfa_offset 16
; MIPS64-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
; MIPS64-NEXT: .cfi_offset 31, -8
; MIPS64-NEXT: jal foo1
; MIPS64-NEXT: nop
; MIPS64-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
; MIPS64-NEXT: daddiu $sp, $sp, 16
; MIPS64-NEXT: .LBB0_2: # %if.end
; MIPS64-NEXT: jr $ra
; MIPS64-NEXT: nop
;
; MM-LABEL: test_blez:
; MM: # %bb.0: # %entry
; MM-NEXT: blez $4, $BB0_3
; MM-NEXT: nop
; MM-NEXT: # %bb.1: # %entry
; MM-NEXT: j $BB0_2
; MM-NEXT: nop
; MM-NEXT: $BB0_2: # %if.then
; MM-NEXT: addiu $sp, $sp, -24
; MM-NEXT: .cfi_def_cfa_offset 24
; MM-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MM-NEXT: .cfi_offset 31, -4
; MM-NEXT: jal foo1
; MM-NEXT: nop
; MM-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MM-NEXT: addiu $sp, $sp, 24
; MM-NEXT: $BB0_3: # %if.end
; MM-NEXT: jrc $ra
[mips] Add instruction selection patterns for blez and bgez. llvm-svn: 182396
2013-05-22 01:13:47 +08:00
entry:
%cmp = icmp sgt i32 %a, 0
br i1 %cmp, label %if.then, label %if.end
if.then:
tail call void @foo1()
br label %if.end
if.end:
ret void
}
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
declare void @foo1()
[mips] Promote the result of SETCC nodes to GPR width. Summary: This patch modifies the existing comparison, branch, conditional-move and select patterns, and adds new ones where needed. Also, the updated SLT{u,i,iu} set of instructions generate a GPR width result. The majority of the code changes in the Mips back-end fix the wrong assumption that the result of SETCC nodes always produce an i32 value. The changes in the common code path account for the fact that in 64-bit MIPS targets, i1 is promoted to i32 instead of i64. Reviewers: dsanders Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D10970 llvm-svn: 262316
2016-03-01 18:08:01 +08:00
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
define void @test_bgez(i32 %a) {
[mips] Add microMIPS case to the tests and regenerate assertions using update_llc_test_checks.py. NFC llvm-svn: 337004
2018-07-13 23:03:24 +08:00
; MIPS32-LABEL: test_bgez:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: bltz $4, $BB1_2
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.1: # %if.end
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_2: # %if.then
; MIPS32-NEXT: addiu $sp, $sp, -24
; MIPS32-NEXT: .cfi_def_cfa_offset 24
; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: .cfi_offset 31, -4
; MIPS32-NEXT: jal foo1
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: addiu $sp, $sp, 24
;
; MIPS64-LABEL: test_bgez:
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: sll $1, $4, 0
; MIPS64-NEXT: bltz $1, .LBB1_2
; MIPS64-NEXT: nop
; MIPS64-NEXT: # %bb.1: # %if.end
; MIPS64-NEXT: jr $ra
; MIPS64-NEXT: nop
; MIPS64-NEXT: .LBB1_2: # %if.then
; MIPS64-NEXT: daddiu $sp, $sp, -16
; MIPS64-NEXT: .cfi_def_cfa_offset 16
; MIPS64-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
; MIPS64-NEXT: .cfi_offset 31, -8
; MIPS64-NEXT: jal foo1
; MIPS64-NEXT: nop
; MIPS64-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
; MIPS64-NEXT: jr $ra
; MIPS64-NEXT: daddiu $sp, $sp, 16
;
; MM-LABEL: test_bgez:
; MM: # %bb.0: # %entry
; MM-NEXT: bgez $4, $BB1_2
; MM-NEXT: nop
; MM-NEXT: # %bb.1: # %entry
; MM-NEXT: j $BB1_3
; MM-NEXT: nop
; MM-NEXT: $BB1_2: # %if.end
; MM-NEXT: jrc $ra
; MM-NEXT: $BB1_3: # %if.then
; MM-NEXT: addiu $sp, $sp, -24
; MM-NEXT: .cfi_def_cfa_offset 24
; MM-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MM-NEXT: .cfi_offset 31, -4
; MM-NEXT: jal foo1
; MM-NEXT: nop
; MM-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MM-NEXT: jr $ra
; MM-NEXT: addiu $sp, $sp, 24
[mips] Promote the result of SETCC nodes to GPR width. Summary: This patch modifies the existing comparison, branch, conditional-move and select patterns, and adds new ones where needed. Also, the updated SLT{u,i,iu} set of instructions generate a GPR width result. The majority of the code changes in the Mips back-end fix the wrong assumption that the result of SETCC nodes always produce an i32 value. The changes in the common code path account for the fact that in 64-bit MIPS targets, i1 is promoted to i32 instead of i64. Reviewers: dsanders Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D10970 llvm-svn: 262316
2016-03-01 18:08:01 +08:00
entry:
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
%cmp = icmp slt i32 %a, 0
[mips] Promote the result of SETCC nodes to GPR width. Summary: This patch modifies the existing comparison, branch, conditional-move and select patterns, and adds new ones where needed. Also, the updated SLT{u,i,iu} set of instructions generate a GPR width result. The majority of the code changes in the Mips back-end fix the wrong assumption that the result of SETCC nodes always produce an i32 value. The changes in the common code path account for the fact that in 64-bit MIPS targets, i1 is promoted to i32 instead of i64. Reviewers: dsanders Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D10970 llvm-svn: 262316
2016-03-01 18:08:01 +08:00
br i1 %cmp, label %if.then, label %if.end
if.then:
tail call void @foo1()
br label %if.end
if.end:
ret void
}