llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir

# RUN: llc -O0 -run-pass=legalize-mir -global-isel %s -o - 2>&1 | FileCheck %s

--- |
  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
  target triple = "aarch64-apple-ios"
  define void @test_scalar_add_big() {
  entry:
    ret void
  }
  define void @test_scalar_add_small() {
  entry:
    ret void
  }
  define void @test_vector_add() {
  entry:
    ret void
  }
...

---
name:            test_scalar_add_big
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body: |
  bb.0.entry:
    liveins: %x0, %x1, %x2, %x3
    ; CHECK-LABEL: name: test_scalar_add_big
    ; CHECK-DAG: [[LHS_LO:%.*]](64), [[LHS_HI:%.*]](64) = G_EXTRACT { s64, s64, s128 } %0, 0, 64
    ; CHECK-DAG: [[RHS_LO:%.*]](64), [[RHS_HI:%.*]](64) = G_EXTRACT { s64, s64, s128 } %1, 0, 64
    ; CHECK-DAG: [[CARRY0_32:%.*]](32) = G_CONSTANT s32 0
    ; CHECK-DAG: [[CARRY0:%[0-9]+]](1) = G_TRUNC { s1, s32 } [[CARRY0_32]]
    ; CHECK: [[RES_LO:%.*]](64), [[CARRY:%.*]](1) = G_UADDE s64 [[LHS_LO]], [[RHS_LO]], [[CARRY0]]
    ; CHECK: [[RES_HI:%.*]](64), {{%.*}}(1) = G_UADDE s64 [[LHS_HI]], [[RHS_HI]], [[CARRY]]
    ; CHECK: %2(128) = G_SEQUENCE { s128, s64, s64 } [[RES_LO]], 0, [[RES_HI]], 64

    %0(128) = G_SEQUENCE { s128, s64, s64 } %x0, 0, %x1, 64
    %1(128) = G_SEQUENCE { s128, s64, s64 } %x2, 0, %x3, 64
    %2(128) = G_ADD s128 %0, %1
    %x0, %x1 = G_EXTRACT { s64, s64, s128 } %2, 0, 64
...

---
name:            test_scalar_add_small
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body: |
  bb.0.entry:
    liveins: %x0, %x1, %x2, %x3
    ; CHECK-LABEL: name: test_scalar_add_small
    ; CHECK: [[RES:%.*]](8) = G_ADD s8 %0, %1

    %0(8) = G_TRUNC { s8, s64 } %x0
    %1(8) = G_TRUNC { s8, s64 } %x1
    %2(8) = G_ADD s8 %0, %1
    %x0 = G_ANYEXT { s64, s8 } %2
...

---
name:            test_vector_add
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body: |
  bb.0.entry:
    liveins: %q0, %q1, %q2, %q3
    ; CHECK-LABEL: name: test_vector_add
    ; CHECK-DAG: [[LHS_LO:%.*]](128), [[LHS_HI:%.*]](128) = G_EXTRACT { s128, s128, s256 } %0, 0, 128
    ; CHECK-DAG: [[RHS_LO:%.*]](128), [[RHS_HI:%.*]](128) = G_EXTRACT { s128, s128, s256 } %1, 0, 128
    ; CHECK: [[RES_LO:%.*]](128) = G_ADD <2 x s64> [[LHS_LO]], [[RHS_LO]]
    ; CHECK: [[RES_HI:%.*]](128) = G_ADD <2 x s64> [[LHS_HI]], [[RHS_HI]]
    ; CHECK: %2(256) = G_SEQUENCE { s256, s128, s128 } [[RES_LO]], 0, [[RES_HI]], 128

    %0(256) = G_SEQUENCE { s256, s128, s128 } %q0, 0, %q1, 128
    %1(256) = G_SEQUENCE { s256, s128, s128 } %q2, 0, %q3, 128
    %2(256) = G_ADD <4 x s64> %0, %1
    %q0, %q1 = G_EXTRACT { s128, s128, s256 } %2, 0, 128
...