2012-02-17 16:55:11 +08:00
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//===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
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2007-06-06 15:42:06 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-06-06 15:42:06 +08:00
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//
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2011-04-16 05:51:11 +08:00
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//===----------------------------------------------------------------------===//
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2007-06-06 15:42:06 +08:00
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//
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// Implements the info about Mips target spec.
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//
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2011-04-16 05:51:11 +08:00
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//===----------------------------------------------------------------------===//
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2007-06-06 15:42:06 +08:00
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2017-02-01 09:22:51 +08:00
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#include "MCTargetDesc/MipsABIInfo.h"
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#include "MCTargetDesc/MipsMCTargetDesc.h"
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2012-03-18 02:46:09 +08:00
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#include "Mips.h"
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2014-01-07 19:48:04 +08:00
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#include "Mips16ISelDAGToDAG.h"
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2013-04-10 03:46:01 +08:00
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#include "MipsSEISelDAGToDAG.h"
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2017-02-01 09:22:51 +08:00
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#include "MipsSubtarget.h"
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2014-11-13 17:26:31 +08:00
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#include "MipsTargetObjectFile.h"
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2017-02-01 09:22:51 +08:00
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#include "MipsTargetMachine.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringRef.h"
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2013-04-10 03:46:01 +08:00
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#include "llvm/Analysis/TargetTransformInfo.h"
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2017-02-01 09:22:51 +08:00
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/CodeGen/MachineFunction.h"
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2012-02-03 13:12:41 +08:00
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#include "llvm/CodeGen/Passes.h"
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2016-05-10 11:21:59 +08:00
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#include "llvm/CodeGen/TargetPassConfig.h"
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2017-02-01 09:22:51 +08:00
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/CodeGen.h"
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2013-04-10 03:46:01 +08:00
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#include "llvm/Support/Debug.h"
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2011-08-25 02:08:43 +08:00
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#include "llvm/Support/TargetRegistry.h"
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2014-01-07 19:48:04 +08:00
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#include "llvm/Support/raw_ostream.h"
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2017-02-01 09:22:51 +08:00
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#include "llvm/Target/TargetOptions.h"
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#include <string>
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2015-03-14 16:34:25 +08:00
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2007-06-06 15:42:06 +08:00
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using namespace llvm;
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2014-04-22 06:55:11 +08:00
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#define DEBUG_TYPE "mips"
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2009-07-25 14:49:55 +08:00
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extern "C" void LLVMInitializeMipsTarget() {
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// Register the target.
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2016-10-10 07:00:34 +08:00
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RegisterTargetMachine<MipsebTargetMachine> X(getTheMipsTarget());
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RegisterTargetMachine<MipselTargetMachine> Y(getTheMipselTarget());
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RegisterTargetMachine<MipsebTargetMachine> A(getTheMips64Target());
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RegisterTargetMachine<MipselTargetMachine> B(getTheMips64elTarget());
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2007-06-06 15:42:06 +08:00
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}
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2015-06-11 23:34:59 +08:00
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static std::string computeDataLayout(const Triple &TT, StringRef CPU,
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2015-03-12 08:07:24 +08:00
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const TargetOptions &Options,
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bool isLittle) {
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2017-02-01 09:22:51 +08:00
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std::string Ret;
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2015-09-16 00:17:27 +08:00
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MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions);
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2015-01-27 03:03:15 +08:00
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// There are both little and big endian mips.
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if (isLittle)
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Ret += "e";
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else
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Ret += "E";
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2016-07-19 18:49:03 +08:00
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if (ABI.IsO32())
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Ret += "-m:m";
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else
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Ret += "-m:e";
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2015-01-27 03:03:15 +08:00
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// Pointers are 32 bit on some ABIs.
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if (!ABI.IsN64())
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Ret += "-p:32:32";
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2015-07-08 05:31:54 +08:00
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// 8 and 16 bit integers only need to have natural alignment, but try to
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2015-01-27 03:03:15 +08:00
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// align them to 32 bits. 64 bit integers have natural alignment.
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Ret += "-i8:8:32-i16:16:32-i64:64";
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// 32 bit registers are always available and the stack is at least 64 bit
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// aligned. On N64 64 bit registers are also available and the stack is
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// 128 bit aligned.
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if (ABI.IsN64() || ABI.IsN32())
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Ret += "-n32:64-S128";
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else
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Ret += "-n32-S64";
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return Ret;
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}
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2016-05-19 06:04:49 +08:00
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static Reloc::Model getEffectiveRelocModel(CodeModel::Model CM,
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Optional<Reloc::Model> RM) {
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if (!RM.hasValue() || CM == CodeModel::JITDefault)
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return Reloc::Static;
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return *RM;
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}
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2007-08-28 13:13:42 +08:00
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// On function prologue, the stack is created by decrementing
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// its pointer. Once decremented, all references are done with positive
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2010-11-15 08:06:54 +08:00
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// offset from the stack/frame pointer, using StackGrowsUp enables
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2008-08-06 14:14:43 +08:00
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// an easier handling.
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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// Using CodeModel::Large enables different CALL behavior.
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2015-06-12 03:41:26 +08:00
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MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT,
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2014-07-02 08:54:07 +08:00
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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2016-05-19 06:04:49 +08:00
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Optional<Reloc::Model> RM,
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CodeModel::Model CM, CodeGenOpt::Level OL,
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bool isLittle)
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2015-06-12 03:41:26 +08:00
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: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
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2016-05-19 06:04:49 +08:00
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CPU, FS, Options, getEffectiveRelocModel(CM, RM), CM,
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OL),
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2017-02-01 09:22:51 +08:00
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isLittle(isLittle), TLOF(llvm::make_unique<MipsTargetObjectFile>()),
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2015-09-16 00:17:27 +08:00
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ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)),
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2015-06-12 03:41:26 +08:00
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Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this),
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NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
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2015-01-09 02:18:57 +08:00
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isLittle, *this),
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2015-06-12 03:41:26 +08:00
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Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
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isLittle, *this) {
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2014-07-19 07:41:32 +08:00
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Subtarget = &DefaultSubtarget;
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2013-05-13 09:16:13 +08:00
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initAsmInfo();
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2013-04-10 03:46:01 +08:00
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}
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2017-02-01 09:22:51 +08:00
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MipsTargetMachine::~MipsTargetMachine() = default;
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2014-11-21 07:37:18 +08:00
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2017-02-01 09:22:51 +08:00
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void MipsebTargetMachine::anchor() {}
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2011-12-20 10:50:00 +08:00
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2015-06-12 03:41:26 +08:00
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MipsebTargetMachine::MipsebTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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2016-05-19 06:04:49 +08:00
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Optional<Reloc::Model> RM,
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CodeModel::Model CM,
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2015-06-12 03:41:26 +08:00
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CodeGenOpt::Level OL)
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: MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
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2011-09-21 11:00:58 +08:00
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2017-02-01 09:22:51 +08:00
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void MipselTargetMachine::anchor() {}
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2011-12-20 10:50:00 +08:00
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2015-06-12 03:41:26 +08:00
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MipselTargetMachine::MipselTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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2016-05-19 06:04:49 +08:00
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Optional<Reloc::Model> RM,
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CodeModel::Model CM,
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2015-06-12 03:41:26 +08:00
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CodeGenOpt::Level OL)
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: MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
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2008-06-04 09:45:25 +08:00
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2014-09-26 09:44:08 +08:00
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const MipsSubtarget *
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2014-09-26 10:57:05 +08:00
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MipsTargetMachine::getSubtargetImpl(const Function &F) const {
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2015-02-14 10:37:48 +08:00
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Attribute CPUAttr = F.getFnAttribute("target-cpu");
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Attribute FSAttr = F.getFnAttribute("target-features");
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2014-09-26 09:44:08 +08:00
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std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
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? CPUAttr.getValueAsString().str()
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: TargetCPU;
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std::string FS = !FSAttr.hasAttribute(Attribute::None)
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? FSAttr.getValueAsString().str()
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: TargetFS;
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bool hasMips16Attr =
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2015-02-14 10:37:48 +08:00
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!F.getFnAttribute("mips16").hasAttribute(Attribute::None);
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2014-09-26 09:44:08 +08:00
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bool hasNoMips16Attr =
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2015-02-14 10:37:48 +08:00
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!F.getFnAttribute("nomips16").hasAttribute(Attribute::None);
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2014-09-26 09:44:08 +08:00
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2014-09-30 05:57:54 +08:00
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// FIXME: This is related to the code below to reset the target options,
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// we need to know whether or not the soft float flag is set on the
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2015-05-07 18:29:52 +08:00
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// function, so we can enable it as a subtarget feature.
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2015-05-12 09:26:05 +08:00
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bool softFloat =
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F.hasFnAttribute("use-soft-float") &&
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F.getFnAttribute("use-soft-float").getValueAsString() == "true";
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2014-09-30 05:57:54 +08:00
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2014-09-26 09:44:08 +08:00
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if (hasMips16Attr)
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FS += FS.empty() ? "+mips16" : ",+mips16";
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else if (hasNoMips16Attr)
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FS += FS.empty() ? "-mips16" : ",-mips16";
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2015-05-07 18:29:52 +08:00
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if (softFloat)
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FS += FS.empty() ? "+soft-float" : ",+soft-float";
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2014-09-26 09:44:08 +08:00
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2015-05-07 18:29:52 +08:00
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auto &I = SubtargetMap[CPU + FS];
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2014-09-26 09:44:08 +08:00
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if (!I) {
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// This needs to be done before we create a new subtarget since any
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// creation will depend on the TM and the code generation flags on the
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// function that reside in TargetOptions.
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resetTargetOptions(F);
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2015-06-16 23:44:21 +08:00
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I = llvm::make_unique<MipsSubtarget>(TargetTriple, CPU, FS, isLittle,
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*this);
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2014-09-26 09:44:08 +08:00
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}
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return I.get();
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}
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2014-07-19 07:41:32 +08:00
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void MipsTargetMachine::resetSubtarget(MachineFunction *MF) {
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DEBUG(dbgs() << "resetSubtarget\n");
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2014-09-26 09:44:08 +08:00
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2014-09-26 10:57:05 +08:00
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Subtarget = const_cast<MipsSubtarget *>(getSubtargetImpl(*MF->getFunction()));
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2014-08-05 10:39:49 +08:00
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MF->setSubtarget(Subtarget);
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2014-07-19 07:41:32 +08:00
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}
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2012-02-03 13:12:41 +08:00
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namespace {
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2017-02-01 09:22:51 +08:00
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2012-02-03 13:12:41 +08:00
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/// Mips Code Generator Pass Configuration Options.
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class MipsPassConfig : public TargetPassConfig {
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public:
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2012-02-04 10:56:59 +08:00
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MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
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2013-10-08 03:13:53 +08:00
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: TargetPassConfig(TM, PM) {
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// The current implementation of long branch pass requires a scratch
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// register ($at) to be available before branch instructions. Tail merging
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// can break this requirement, so disable it when long branch pass is
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// enabled.
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EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
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}
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2012-02-03 13:12:41 +08:00
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MipsTargetMachine &getMipsTargetMachine() const {
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return getTM<MipsTargetMachine>();
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}
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const MipsSubtarget &getMipsSubtarget() const {
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return *getMipsTargetMachine().getSubtargetImpl();
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}
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2014-04-29 15:58:02 +08:00
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void addIRPasses() override;
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bool addInstSelector() override;
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2014-12-12 05:26:47 +08:00
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void addPreEmitPass() override;
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void addPreRegAlloc() override;
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2012-02-03 13:12:41 +08:00
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};
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2017-02-01 09:22:51 +08:00
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} // end anonymous namespace
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2012-02-03 13:12:41 +08:00
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2012-02-04 10:56:59 +08:00
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TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new MipsPassConfig(this, PM);
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2012-02-03 13:12:41 +08:00
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}
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2013-04-11 00:58:04 +08:00
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void MipsPassConfig::addIRPasses() {
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TargetPassConfig::addIRPasses();
|
Erase fence insertion from SelectionDAGBuilder.cpp (NFC)
Summary:
Backends can use setInsertFencesForAtomic to signal to the middle-end that
montonic is the only memory ordering they can accept for
stores/loads/rmws/cmpxchg. The code lowering those accesses with a stronger
ordering to fences + monotonic accesses is currently living in
SelectionDAGBuilder.cpp. In this patch I propose moving this logic out of it
for several reasons:
- There is lots of redundancy to avoid: extremely similar logic already
exists in AtomicExpand.
- The current code in SelectionDAGBuilder does not use any target-hooks, it
does the same transformation for every backend that requires it
- As a result it is plain *unsound*, as it was apparently designed for ARM.
It happens to mostly work for the other targets because they are extremely
conservative, but Power for example had to switch to AtomicExpand to be
able to use lwsync safely (see r218331).
- Because it produces IR-level fences, it cannot be made sound ! This is noted
in the C++11 standard (section 29.3, page 1140):
```
Fences cannot, in general, be used to restore sequential consistency for atomic
operations with weaker ordering semantics.
```
It can also be seen by the following example (called IRIW in the litterature):
```
atomic<int> x = y = 0;
int r1, r2, r3, r4;
Thread 0:
x.store(1);
Thread 1:
y.store(1);
Thread 2:
r1 = x.load();
r2 = y.load();
Thread 3:
r3 = y.load();
r4 = x.load();
```
r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all seq_cst.
But if they are lowered to monotonic accesses, no amount of fences can prevent it..
This patch does three things (I could cut it into parts, but then some of them
would not be tested/testable, please tell me if you would prefer that):
- it provides a default implementation for emitLeadingFence/emitTrailingFence in
terms of IR-level fences, that mimic the original logic of SelectionDAGBuilder.
As we saw above, this is unsound, but the best that can be done without knowing
the targets well (and there is a comment warning about this risk).
- it then switches Mips/Sparc/XCore to use AtomicExpand, relying on this default
implementation (that exactly replicates the logic of SelectionDAGBuilder, so no
functional change)
- it finally erase this logic from SelectionDAGBuilder as it is dead-code.
Ideally, each target would define its own override for emitLeading/TrailingFence
using target-specific fences, but I do not know the Sparc/Mips/XCore memory model
well enough to do this, and they appear to be dealing fine with the ARM-inspired
default expansion for now (probably because they are overly conservative, as
Power was). If anyone wants to compile fences more agressively on these
platforms, the long comment should make it clear why he should first override
emitLeading/TrailingFence.
Test Plan: make check-all, no functional change
Reviewers: jfb, t.p.northover
Subscribers: aemerson, llvm-commits
Differential Revision: http://reviews.llvm.org/D5474
llvm-svn: 219957
2014-10-17 04:34:57 +08:00
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addPass(createAtomicExpandPass(&getMipsTargetMachine()));
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2013-04-11 00:58:04 +08:00
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if (getMipsSubtarget().os16())
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2015-03-14 16:34:25 +08:00
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addPass(createMipsOs16Pass(getMipsTargetMachine()));
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Checkin in of first of several patches to finish implementation of
mips16/mips32 floating point interoperability.
This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.
Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.
This is needed when returning float, double, single complex, double complex
in the Mips ABI.
Helper functions in libc for mips16 are available to do this.
For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.
Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.
This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.
The only register that is modified is ra in this call.
The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).
llvm-svn: 181641
2013-05-11 06:25:39 +08:00
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if (getMipsSubtarget().inMips16HardFloat())
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2015-03-14 17:02:23 +08:00
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addPass(createMips16HardFloatPass(getMipsTargetMachine()));
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2013-04-11 00:58:04 +08:00
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}
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2010-11-15 08:06:54 +08:00
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// Install an instruction selector pass using
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2007-06-06 15:42:06 +08:00
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// the ISelDag to gen Mips code.
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2012-05-01 16:27:43 +08:00
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bool MipsPassConfig::addInstSelector() {
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2015-03-14 17:20:52 +08:00
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addPass(createMipsModuleISelDagPass(getMipsTargetMachine()));
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[mips] SelectionDAGISel subclasses now follow the optimization level.
Summary:
It was recently discovered that, for Mips's SelectionDAGISel subclasses,
all optimization levels caused SelectionDAGISel to behave like -O2.
This change adds the necessary plumbing to initialize the optimization level.
Reviewers: andrew.w.kaylor
Subscribers: andrew.w.kaylor, sdardis, dean, llvm-commits, vradosavljevic, petarj, qcolombet, probinson, dsanders
Differential Revision: https://reviews.llvm.org/D14900
llvm-svn: 275410
2016-07-14 21:25:22 +08:00
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addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel()));
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addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel()));
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2007-06-06 15:42:06 +08:00
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return false;
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}
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2014-12-12 05:26:47 +08:00
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void MipsPassConfig::addPreRegAlloc() {
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2016-11-02 23:11:27 +08:00
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addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
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2014-03-11 00:31:25 +08:00
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}
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2015-02-01 21:20:00 +08:00
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TargetIRAnalysis MipsTargetMachine::getTargetIRAnalysis() {
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2015-09-17 07:38:13 +08:00
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return TargetIRAnalysis([this](const Function &F) {
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2015-02-01 21:20:00 +08:00
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if (Subtarget->allowMixed16_32()) {
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DEBUG(errs() << "No Target Transform Info Pass Added\n");
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// FIXME: This is no longer necessary as the TTI returned is per-function.
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2015-07-09 10:08:42 +08:00
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return TargetTransformInfo(F.getParent()->getDataLayout());
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2015-02-01 21:20:00 +08:00
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}
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DEBUG(errs() << "Target Transform Info Pass Added\n");
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2015-02-01 22:22:17 +08:00
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return TargetTransformInfo(BasicTTIImpl(this, F));
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2015-02-01 21:20:00 +08:00
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});
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2013-04-10 03:46:01 +08:00
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}
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2010-11-15 08:06:54 +08:00
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// Implemented by targets that want to run passes immediately before
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// machine code is emitted. return true if -print-machineinstrs should
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2007-06-06 15:42:06 +08:00
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// print out the code after the passes.
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2014-12-12 05:26:47 +08:00
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void MipsPassConfig::addPreEmitPass() {
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2012-06-14 09:19:35 +08:00
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MipsTargetMachine &TM = getMipsTargetMachine();
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2016-03-15 00:24:05 +08:00
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// The delay slot filler pass can potientially create forbidden slot (FS)
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// hazards for MIPSR6 which the hazard schedule pass (HSP) will fix. Any
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// (new) pass that creates compact branches after the HSP must handle FS
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// hazards itself or be pipelined before the HSP.
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2014-12-12 07:18:03 +08:00
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addPass(createMipsDelaySlotFillerPass(TM));
|
2016-03-15 02:10:20 +08:00
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addPass(createMipsHazardSchedule());
|
2014-12-12 07:18:03 +08:00
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addPass(createMipsLongBranchPass(TM));
|
2016-06-28 22:26:39 +08:00
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addPass(createMipsConstantIslandPass());
|
2007-06-06 15:42:06 +08:00
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}
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