2016-01-12 23:56:33 +08:00
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//===--- RDFLiveness.cpp --------------------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Computation of the liveness information from the data-flow graph.
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//
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// The main functionality of this code is to compute block live-in
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// information. With the live-in information in place, the placement
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// of kill flags can also be recalculated.
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//
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// The block live-in calculation is based on the ideas from the following
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// publication:
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//
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// Dibyendu Das, Ramakrishna Upadrasta, Benoit Dupont de Dinechin.
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// "Efficient Liveness Computation Using Merge Sets and DJ-Graphs."
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// ACM Transactions on Architecture and Code Optimization, Association for
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// Computing Machinery, 2012, ACM TACO Special Issue on "High-Performance
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// and Embedded Architectures and Compilers", 8 (4),
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// <10.1145/2086696.2086706>. <hal-00647369>
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//
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#include "RDFGraph.h"
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#include "RDFLiveness.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineDominanceFrontier.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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using namespace rdf;
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2016-05-27 18:06:40 +08:00
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namespace llvm {
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2016-01-12 23:56:33 +08:00
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namespace rdf {
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template<>
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raw_ostream &operator<< (raw_ostream &OS, const Print<Liveness::RefMap> &P) {
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OS << '{';
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for (auto &I : P.Obj) {
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OS << ' ' << PrintReg(I.first, &P.G.getTRI()) << '{';
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for (auto J = I.second.begin(), E = I.second.end(); J != E; ) {
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OS << Print<NodeId>(J->first, P.G) << PrintLaneMaskOpt(J->second);
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if (++J != E)
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OS << ',';
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}
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OS << '}';
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}
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OS << " }";
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return OS;
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}
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2016-05-27 18:06:40 +08:00
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} // namespace rdf
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} // namespace llvm
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2016-01-12 23:56:33 +08:00
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// The order in the returned sequence is the order of reaching defs in the
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// upward traversal: the first def is the closest to the given reference RefA,
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// the next one is further up, and so on.
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// The list ends at a reaching phi def, or when the reference from RefA is
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// covered by the defs in the list (see FullChain).
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// This function provides two modes of operation:
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// (1) Returning the sequence of reaching defs for a particular reference
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// node. This sequence will terminate at the first phi node [1].
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// (2) Returning a partial sequence of reaching defs, where the final goal
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// is to traverse past phi nodes to the actual defs arising from the code
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// itself.
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// In mode (2), the register reference for which the search was started
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// may be different from the reference node RefA, for which this call was
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// made, hence the argument RefRR, which holds the original register.
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// Also, some definitions may have already been encountered in a previous
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// call that will influence register covering. The register references
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// already defined are passed in through DefRRs.
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// In mode (1), the "continuation" considerations do not apply, and the
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// RefRR is the same as the register in RefA, and the set DefRRs is empty.
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//
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// [1] It is possible for multiple phi nodes to be included in the returned
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// sequence:
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// SubA = phi ...
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// SubB = phi ...
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// ... = SuperAB(rdef:SubA), SuperAB"(rdef:SubB)
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// However, these phi nodes are independent from one another in terms of
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// the data-flow.
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NodeList Liveness::getAllReachingDefs(RegisterRef RefRR,
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2016-10-04 01:14:48 +08:00
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NodeAddr<RefNode*> RefA, bool FullChain, const RegisterAggr &DefRRs) {
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2016-09-28 02:24:33 +08:00
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NodeList RDefs; // Return value.
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SetVector<NodeId> DefQ;
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SetVector<NodeId> Owners;
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2016-09-28 02:24:33 +08:00
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// Dead defs will be treated as if they were live, since they are actually
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// on the data-flow path. They cannot be ignored because even though they
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// do not generate meaningful values, they still modify registers.
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// If the reference is undefined, there is nothing to do.
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if (RefA.Addr->getFlags() & NodeAttrs::Undef)
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return RDefs;
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2016-01-12 23:56:33 +08:00
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// The initial queue should not have reaching defs for shadows. The
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// whole point of a shadow is that it will have a reaching def that
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// is not aliased to the reaching defs of the related shadows.
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NodeId Start = RefA.Id;
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auto SNA = DFG.addr<RefNode*>(Start);
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if (NodeId RD = SNA.Addr->getReachingDef())
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DefQ.insert(RD);
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// Collect all the reaching defs, going up until a phi node is encountered,
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// or there are no more reaching defs. From this set, the actual set of
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// reaching defs will be selected.
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// The traversal upwards must go on until a covering def is encountered.
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// It is possible that a collection of non-covering (individually) defs
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// will be sufficient, but keep going until a covering one is found.
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for (unsigned i = 0; i < DefQ.size(); ++i) {
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auto TA = DFG.addr<DefNode*>(DefQ[i]);
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if (TA.Addr->getFlags() & NodeAttrs::PhiRef)
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continue;
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// Stop at the covering/overwriting def of the initial register reference.
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RegisterRef RR = TA.Addr->getRegRef(DFG);
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if (!DFG.IsPreservingDef(TA))
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if (RegisterAggr::isCoverOf(RR, RefRR, PRI))
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continue;
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2016-01-12 23:56:33 +08:00
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// Get the next level of reaching defs. This will include multiple
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// reaching defs for shadows.
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for (auto S : DFG.getRelatedRefs(TA.Addr->getOwner(DFG), TA))
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2016-10-06 21:05:13 +08:00
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if (NodeId RD = NodeAddr<RefNode*>(S).Addr->getReachingDef())
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DefQ.insert(RD);
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}
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// Remove all non-phi defs that are not aliased to RefRR, and collect
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// the owners of the remaining defs.
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SetVector<NodeId> Defs;
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for (NodeId N : DefQ) {
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auto TA = DFG.addr<DefNode*>(N);
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bool IsPhi = TA.Addr->getFlags() & NodeAttrs::PhiRef;
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if (!IsPhi && !PRI.alias(RefRR, TA.Addr->getRegRef(DFG)))
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continue;
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Defs.insert(TA.Id);
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Owners.insert(TA.Addr->getOwner(DFG).Id);
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}
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// Return the MachineBasicBlock containing a given instruction.
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auto Block = [this] (NodeAddr<InstrNode*> IA) -> MachineBasicBlock* {
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if (IA.Addr->getKind() == NodeAttrs::Stmt)
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return NodeAddr<StmtNode*>(IA).Addr->getCode()->getParent();
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assert(IA.Addr->getKind() == NodeAttrs::Phi);
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NodeAddr<PhiNode*> PA = IA;
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NodeAddr<BlockNode*> BA = PA.Addr->getOwner(DFG);
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return BA.Addr->getCode();
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};
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// Less(A,B) iff instruction A is further down in the dominator tree than B.
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auto Less = [&Block,this] (NodeId A, NodeId B) -> bool {
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if (A == B)
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return false;
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auto OA = DFG.addr<InstrNode*>(A), OB = DFG.addr<InstrNode*>(B);
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MachineBasicBlock *BA = Block(OA), *BB = Block(OB);
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if (BA != BB)
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return MDT.dominates(BB, BA);
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// They are in the same block.
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bool StmtA = OA.Addr->getKind() == NodeAttrs::Stmt;
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bool StmtB = OB.Addr->getKind() == NodeAttrs::Stmt;
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if (StmtA) {
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if (!StmtB) // OB is a phi and phis dominate statements.
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return true;
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2016-10-06 21:05:13 +08:00
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MachineInstr *CA = NodeAddr<StmtNode*>(OA).Addr->getCode();
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MachineInstr *CB = NodeAddr<StmtNode*>(OB).Addr->getCode();
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2016-01-12 23:56:33 +08:00
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// The order must be linear, so tie-break such equalities.
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if (CA == CB)
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return A < B;
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return MDT.dominates(CB, CA);
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} else {
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// OA is a phi.
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if (StmtB)
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return false;
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// Both are phis. There is no ordering between phis (in terms of
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// the data-flow), so tie-break this via node id comparison.
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return A < B;
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}
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};
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std::vector<NodeId> Tmp(Owners.begin(), Owners.end());
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std::sort(Tmp.begin(), Tmp.end(), Less);
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// The vector is a list of instructions, so that defs coming from
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// the same instruction don't need to be artificially ordered.
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// Then, when computing the initial segment, and iterating over an
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// instruction, pick the defs that contribute to the covering (i.e. is
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// not covered by previously added defs). Check the defs individually,
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// i.e. first check each def if is covered or not (without adding them
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// to the tracking set), and then add all the selected ones.
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// The reason for this is this example:
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// *d1<A>, *d2<B>, ... Assume A and B are aliased (can happen in phi nodes).
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// *d3<C> If A \incl BuC, and B \incl AuC, then *d2 would be
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// covered if we added A first, and A would be covered
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// if we added B first.
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2016-10-04 01:14:48 +08:00
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RegisterAggr RRs(DefRRs);
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2016-01-12 23:56:33 +08:00
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auto DefInSet = [&Defs] (NodeAddr<RefNode*> TA) -> bool {
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return TA.Addr->getKind() == NodeAttrs::Def &&
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Defs.count(TA.Id);
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};
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2016-10-06 21:05:13 +08:00
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for (NodeId T : Tmp) {
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2016-10-04 01:14:48 +08:00
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if (!FullChain && RRs.hasCoverOf(RefRR))
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2016-01-12 23:56:33 +08:00
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break;
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auto TA = DFG.addr<InstrNode*>(T);
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bool IsPhi = DFG.IsCode<NodeAttrs::Phi>(TA);
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NodeList Ds;
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for (NodeAddr<DefNode*> DA : TA.Addr->members_if(DefInSet, DFG)) {
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2016-10-15 01:57:55 +08:00
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RegisterRef QR = DA.Addr->getRegRef(DFG);
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2016-01-12 23:56:33 +08:00
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// Add phi defs even if they are covered by subsequent defs. This is
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// for cases where the reached use is not covered by any of the defs
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// encountered so far: the phi def is needed to expose the liveness
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// of that use to the entry of the block.
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// Example:
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// phi d1<R3>(,d2,), ... Phi def d1 is covered by d2.
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// d2<R3>(d1,,u3), ...
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// ..., u3<D1>(d2) This use needs to be live on entry.
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2016-10-04 01:14:48 +08:00
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if (FullChain || IsPhi || !RRs.hasCoverOf(QR))
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2016-01-12 23:56:33 +08:00
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Ds.push_back(DA);
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}
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RDefs.insert(RDefs.end(), Ds.begin(), Ds.end());
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for (NodeAddr<DefNode*> DA : Ds) {
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// When collecting a full chain of definitions, do not consider phi
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// defs to actually define a register.
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uint16_t Flags = DA.Addr->getFlags();
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if (!FullChain || !(Flags & NodeAttrs::PhiRef))
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2016-09-08 04:10:56 +08:00
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if (!(Flags & NodeAttrs::Preserving)) // Don't care about Undef here.
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2016-10-15 01:57:55 +08:00
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RRs.insert(DA.Addr->getRegRef(DFG));
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2016-01-12 23:56:33 +08:00
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}
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}
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2016-09-28 02:24:33 +08:00
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auto DeadP = [](const NodeAddr<DefNode*> DA) -> bool {
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return DA.Addr->getFlags() & NodeAttrs::Dead;
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};
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RDefs.resize(std::distance(RDefs.begin(), remove_if(RDefs, DeadP)));
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2016-01-12 23:56:33 +08:00
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return RDefs;
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}
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2016-04-29 23:49:13 +08:00
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NodeSet Liveness::getAllReachingDefsRec(RegisterRef RefRR,
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NodeAddr<RefNode*> RefA, NodeSet &Visited, const NodeSet &Defs) {
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// Collect all defined registers. Do not consider phis to be defining
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// anything, only collect "real" definitions.
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2017-01-31 01:46:56 +08:00
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RegisterAggr DefRRs(PRI);
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2016-10-04 01:14:48 +08:00
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for (NodeId D : Defs) {
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2016-04-29 23:49:13 +08:00
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const auto DA = DFG.addr<const DefNode*>(D);
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if (!(DA.Addr->getFlags() & NodeAttrs::PhiRef))
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2016-10-15 01:57:55 +08:00
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DefRRs.insert(DA.Addr->getRegRef(DFG));
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2016-04-29 23:49:13 +08:00
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}
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2016-10-06 21:05:13 +08:00
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NodeList RDs = getAllReachingDefs(RefRR, RefA, true, DefRRs);
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2016-04-29 23:49:13 +08:00
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if (RDs.empty())
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return Defs;
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// Make a copy of the preexisting definitions and add the newly found ones.
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NodeSet TmpDefs = Defs;
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2016-10-06 21:05:13 +08:00
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for (NodeAddr<NodeBase*> R : RDs)
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2016-04-29 23:49:13 +08:00
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TmpDefs.insert(R.Id);
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NodeSet Result = Defs;
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for (NodeAddr<DefNode*> DA : RDs) {
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Result.insert(DA.Id);
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if (!(DA.Addr->getFlags() & NodeAttrs::PhiRef))
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continue;
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NodeAddr<PhiNode*> PA = DA.Addr->getOwner(DFG);
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if (Visited.count(PA.Id))
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continue;
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Visited.insert(PA.Id);
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// Go over all phi uses and get the reaching defs for each use.
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for (auto U : PA.Addr->members_if(DFG.IsRef<NodeAttrs::Use>, DFG)) {
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const auto &T = getAllReachingDefsRec(RefRR, U, Visited, TmpDefs);
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Result.insert(T.begin(), T.end());
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}
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}
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return Result;
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}
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NodeSet Liveness::getAllReachedUses(RegisterRef RefRR,
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2016-10-04 01:14:48 +08:00
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NodeAddr<DefNode*> DefA, const RegisterAggr &DefRRs) {
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2016-04-29 23:49:13 +08:00
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NodeSet Uses;
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// If the original register is already covered by all the intervening
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// defs, no more uses can be reached.
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2016-10-04 01:14:48 +08:00
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if (DefRRs.hasCoverOf(RefRR))
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2016-04-29 23:49:13 +08:00
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return Uses;
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// Add all directly reached uses.
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2016-09-28 02:24:33 +08:00
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// If the def is dead, it does not provide a value for any use.
|
|
|
|
bool IsDead = DefA.Addr->getFlags() & NodeAttrs::Dead;
|
|
|
|
NodeId U = !IsDead ? DefA.Addr->getReachedUse() : 0;
|
2016-04-29 23:49:13 +08:00
|
|
|
while (U != 0) {
|
|
|
|
auto UA = DFG.addr<UseNode*>(U);
|
2016-09-08 04:10:56 +08:00
|
|
|
if (!(UA.Addr->getFlags() & NodeAttrs::Undef)) {
|
2016-10-15 01:57:55 +08:00
|
|
|
RegisterRef UR = UA.Addr->getRegRef(DFG);
|
2017-01-31 01:46:56 +08:00
|
|
|
if (PRI.alias(RefRR, UR) && !DefRRs.hasCoverOf(UR))
|
2016-09-08 04:10:56 +08:00
|
|
|
Uses.insert(U);
|
|
|
|
}
|
2016-04-29 23:49:13 +08:00
|
|
|
U = UA.Addr->getSibling();
|
|
|
|
}
|
|
|
|
|
2016-09-28 02:24:33 +08:00
|
|
|
// Traverse all reached defs. This time dead defs cannot be ignored.
|
2016-04-29 23:49:13 +08:00
|
|
|
for (NodeId D = DefA.Addr->getReachedDef(), NextD; D != 0; D = NextD) {
|
|
|
|
auto DA = DFG.addr<DefNode*>(D);
|
|
|
|
NextD = DA.Addr->getSibling();
|
2016-10-15 01:57:55 +08:00
|
|
|
RegisterRef DR = DA.Addr->getRegRef(DFG);
|
2016-04-29 23:49:13 +08:00
|
|
|
// If this def is already covered, it cannot reach anything new.
|
|
|
|
// Similarly, skip it if it is not aliased to the interesting register.
|
2017-01-31 01:46:56 +08:00
|
|
|
if (DefRRs.hasCoverOf(DR) || !PRI.alias(RefRR, DR))
|
2016-04-29 23:49:13 +08:00
|
|
|
continue;
|
|
|
|
NodeSet T;
|
2016-09-08 04:10:56 +08:00
|
|
|
if (DFG.IsPreservingDef(DA)) {
|
2016-04-29 23:49:13 +08:00
|
|
|
// If it is a preserving def, do not update the set of intervening defs.
|
|
|
|
T = getAllReachedUses(RefRR, DA, DefRRs);
|
|
|
|
} else {
|
2016-10-04 01:14:48 +08:00
|
|
|
RegisterAggr NewDefRRs = DefRRs;
|
2016-04-29 23:49:13 +08:00
|
|
|
NewDefRRs.insert(DR);
|
|
|
|
T = getAllReachedUses(RefRR, DA, NewDefRRs);
|
|
|
|
}
|
|
|
|
Uses.insert(T.begin(), T.end());
|
|
|
|
}
|
|
|
|
return Uses;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2016-01-12 23:56:33 +08:00
|
|
|
void Liveness::computePhiInfo() {
|
2016-04-29 23:49:13 +08:00
|
|
|
RealUseMap.clear();
|
|
|
|
|
2016-01-12 23:56:33 +08:00
|
|
|
NodeList Phis;
|
|
|
|
NodeAddr<FuncNode*> FA = DFG.getFunc();
|
2016-10-06 21:05:13 +08:00
|
|
|
NodeList Blocks = FA.Addr->members(DFG);
|
2016-01-12 23:56:33 +08:00
|
|
|
for (NodeAddr<BlockNode*> BA : Blocks) {
|
|
|
|
auto Ps = BA.Addr->members_if(DFG.IsCode<NodeAttrs::Phi>, DFG);
|
|
|
|
Phis.insert(Phis.end(), Ps.begin(), Ps.end());
|
|
|
|
}
|
|
|
|
|
|
|
|
// phi use -> (map: reaching phi -> set of registers defined in between)
|
2016-10-04 01:14:48 +08:00
|
|
|
std::map<NodeId,std::map<NodeId,RegisterAggr>> PhiUp;
|
2016-01-12 23:56:33 +08:00
|
|
|
std::vector<NodeId> PhiUQ; // Work list of phis for upward propagation.
|
|
|
|
|
|
|
|
// Go over all phis.
|
|
|
|
for (NodeAddr<PhiNode*> PhiA : Phis) {
|
|
|
|
// Go over all defs and collect the reached uses that are non-phi uses
|
|
|
|
// (i.e. the "real uses").
|
2016-10-04 01:14:48 +08:00
|
|
|
RefMap &RealUses = RealUseMap[PhiA.Id];
|
|
|
|
NodeList PhiRefs = PhiA.Addr->members(DFG);
|
2016-01-12 23:56:33 +08:00
|
|
|
|
|
|
|
// Have a work queue of defs whose reached uses need to be found.
|
|
|
|
// For each def, add to the queue all reached (non-phi) defs.
|
|
|
|
SetVector<NodeId> DefQ;
|
|
|
|
NodeSet PhiDefs;
|
2016-10-04 01:14:48 +08:00
|
|
|
for (NodeAddr<RefNode*> R : PhiRefs) {
|
2016-01-12 23:56:33 +08:00
|
|
|
if (!DFG.IsRef<NodeAttrs::Def>(R))
|
|
|
|
continue;
|
|
|
|
DefQ.insert(R.Id);
|
|
|
|
PhiDefs.insert(R.Id);
|
|
|
|
}
|
2016-09-08 04:37:05 +08:00
|
|
|
|
|
|
|
// Collect the super-set of all possible reached uses. This set will
|
|
|
|
// contain all uses reached from this phi, either directly from the
|
|
|
|
// phi defs, or (recursively) via non-phi defs reached by the phi defs.
|
|
|
|
// This set of uses will later be trimmed to only contain these uses that
|
|
|
|
// are actually reached by the phi defs.
|
2016-01-12 23:56:33 +08:00
|
|
|
for (unsigned i = 0; i < DefQ.size(); ++i) {
|
|
|
|
NodeAddr<DefNode*> DA = DFG.addr<DefNode*>(DefQ[i]);
|
2016-09-28 02:24:33 +08:00
|
|
|
// Visit all reached uses. Phi defs should not really have the "dead"
|
|
|
|
// flag set, but check it anyway for consistency.
|
|
|
|
bool IsDead = DA.Addr->getFlags() & NodeAttrs::Dead;
|
|
|
|
NodeId UN = !IsDead ? DA.Addr->getReachedUse() : 0;
|
2016-01-12 23:56:33 +08:00
|
|
|
while (UN != 0) {
|
|
|
|
NodeAddr<UseNode*> A = DFG.addr<UseNode*>(UN);
|
2016-09-08 04:10:56 +08:00
|
|
|
uint16_t F = A.Addr->getFlags();
|
2016-10-20 00:30:56 +08:00
|
|
|
if ((F & (NodeAttrs::Undef | NodeAttrs::PhiRef)) == 0) {
|
2017-01-24 07:03:49 +08:00
|
|
|
RegisterRef R = DFG.normalizeRef(getRestrictedRegRef(A));
|
2016-10-20 00:30:56 +08:00
|
|
|
RealUses[R.Reg].insert({A.Id,R.Mask});
|
2017-01-24 07:03:49 +08:00
|
|
|
}
|
2016-01-12 23:56:33 +08:00
|
|
|
UN = A.Addr->getSibling();
|
|
|
|
}
|
2016-09-08 04:37:05 +08:00
|
|
|
// Visit all reached defs, and add them to the queue. These defs may
|
|
|
|
// override some of the uses collected here, but that will be handled
|
|
|
|
// later.
|
2016-01-12 23:56:33 +08:00
|
|
|
NodeId DN = DA.Addr->getReachedDef();
|
|
|
|
while (DN != 0) {
|
|
|
|
NodeAddr<DefNode*> A = DFG.addr<DefNode*>(DN);
|
|
|
|
for (auto T : DFG.getRelatedRefs(A.Addr->getOwner(DFG), A)) {
|
|
|
|
uint16_t Flags = NodeAddr<DefNode*>(T).Addr->getFlags();
|
|
|
|
// Must traverse the reached-def chain. Consider:
|
|
|
|
// def(D0) -> def(R0) -> def(R0) -> use(D0)
|
|
|
|
// The reachable use of D0 passes through a def of R0.
|
|
|
|
if (!(Flags & NodeAttrs::PhiRef))
|
|
|
|
DefQ.insert(T.Id);
|
|
|
|
}
|
|
|
|
DN = A.Addr->getSibling();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
// Filter out these uses that appear to be reachable, but really
|
|
|
|
// are not. For example:
|
|
|
|
//
|
|
|
|
// R1:0 = d1
|
|
|
|
// = R1:0 u2 Reached by d1.
|
|
|
|
// R0 = d3
|
|
|
|
// = R1:0 u4 Still reached by d1: indirectly through
|
|
|
|
// the def d3.
|
|
|
|
// R1 = d5
|
|
|
|
// = R1:0 u6 Not reached by d1 (covered collectively
|
|
|
|
// by d3 and d5), but following reached
|
|
|
|
// defs and uses from d1 will lead here.
|
2016-09-08 04:37:05 +08:00
|
|
|
auto InPhiDefs = [&PhiDefs] (NodeAddr<DefNode*> DA) -> bool {
|
2016-01-12 23:56:33 +08:00
|
|
|
return PhiDefs.count(DA.Id);
|
|
|
|
};
|
|
|
|
for (auto UI = RealUses.begin(), UE = RealUses.end(); UI != UE; ) {
|
|
|
|
// For each reached register UI->first, there is a set UI->second, of
|
|
|
|
// uses of it. For each such use, check if it is reached by this phi,
|
|
|
|
// i.e. check if the set of its reaching uses intersects the set of
|
|
|
|
// this phi's defs.
|
2016-10-20 00:30:56 +08:00
|
|
|
NodeRefSet &Uses = UI->second;
|
2016-01-12 23:56:33 +08:00
|
|
|
for (auto I = Uses.begin(), E = Uses.end(); I != E; ) {
|
2016-10-20 00:30:56 +08:00
|
|
|
auto UA = DFG.addr<UseNode*>(I->first);
|
2016-09-28 02:24:33 +08:00
|
|
|
// Undef flag is checked above.
|
|
|
|
assert((UA.Addr->getFlags() & NodeAttrs::Undef) == 0);
|
2017-01-24 07:03:49 +08:00
|
|
|
RegisterRef R(UI->first, I->second);
|
2016-10-20 00:30:56 +08:00
|
|
|
NodeList RDs = getAllReachingDefs(R, UA);
|
2016-09-08 04:37:05 +08:00
|
|
|
if (any_of(RDs, InPhiDefs))
|
2016-01-12 23:56:33 +08:00
|
|
|
++I;
|
|
|
|
else
|
|
|
|
I = Uses.erase(I);
|
|
|
|
}
|
|
|
|
if (Uses.empty())
|
|
|
|
UI = RealUses.erase(UI);
|
|
|
|
else
|
|
|
|
++UI;
|
|
|
|
}
|
|
|
|
|
|
|
|
// If this phi reaches some "real" uses, add it to the queue for upward
|
|
|
|
// propagation.
|
|
|
|
if (!RealUses.empty())
|
|
|
|
PhiUQ.push_back(PhiA.Id);
|
|
|
|
|
|
|
|
// Go over all phi uses and check if the reaching def is another phi.
|
|
|
|
// Collect the phis that are among the reaching defs of these uses.
|
2016-09-08 04:37:05 +08:00
|
|
|
// While traversing the list of reaching defs for each phi use, accumulate
|
|
|
|
// the set of registers defined between this phi (PhiA) and the owner phi
|
2016-01-12 23:56:33 +08:00
|
|
|
// of the reaching def.
|
2016-09-08 04:37:05 +08:00
|
|
|
NodeSet SeenUses;
|
2016-09-09 04:48:42 +08:00
|
|
|
|
2016-01-12 23:56:33 +08:00
|
|
|
for (auto I : PhiRefs) {
|
2016-09-08 04:37:05 +08:00
|
|
|
if (!DFG.IsRef<NodeAttrs::Use>(I) || SeenUses.count(I.Id))
|
2016-01-12 23:56:33 +08:00
|
|
|
continue;
|
|
|
|
NodeAddr<UseNode*> UA = I;
|
2016-09-09 04:48:42 +08:00
|
|
|
|
|
|
|
// Given a phi use UA, traverse all related phi uses (including UA).
|
|
|
|
// The related phi uses may reach different phi nodes or may reach the
|
|
|
|
// same phi node. If multiple uses reach the same phi P, the intervening
|
|
|
|
// defs must be accumulated for all such uses. To group all such uses
|
|
|
|
// into one set, map their node ids to the first use id that reaches P.
|
|
|
|
std::map<NodeId,NodeId> FirstUse; // Phi reached up -> first phi use.
|
2016-09-08 04:37:05 +08:00
|
|
|
|
|
|
|
for (NodeAddr<UseNode*> VA : DFG.getRelatedRefs(PhiA, UA)) {
|
|
|
|
SeenUses.insert(VA.Id);
|
2017-01-31 01:46:56 +08:00
|
|
|
RegisterAggr DefRRs(PRI);
|
2016-09-08 04:37:05 +08:00
|
|
|
for (NodeAddr<DefNode*> DA : getAllReachingDefs(VA)) {
|
|
|
|
if (DA.Addr->getFlags() & NodeAttrs::PhiRef) {
|
2016-09-09 04:48:42 +08:00
|
|
|
NodeId RP = DA.Addr->getOwner(DFG).Id;
|
|
|
|
NodeId FU = FirstUse.insert({RP,VA.Id}).first->second;
|
2016-10-04 01:14:48 +08:00
|
|
|
std::map<NodeId,RegisterAggr> &M = PhiUp[FU];
|
|
|
|
auto F = M.find(RP);
|
|
|
|
if (F == M.end())
|
|
|
|
M.insert(std::make_pair(RP, DefRRs));
|
|
|
|
else
|
|
|
|
F->second.insert(DefRRs);
|
2016-09-09 04:48:42 +08:00
|
|
|
}
|
2016-10-15 01:57:55 +08:00
|
|
|
DefRRs.insert(DA.Addr->getRegRef(DFG));
|
2016-09-08 04:37:05 +08:00
|
|
|
}
|
2016-01-12 23:56:33 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (Trace) {
|
2016-09-08 04:37:05 +08:00
|
|
|
dbgs() << "Phi-up-to-phi map with intervening defs:\n";
|
2016-01-12 23:56:33 +08:00
|
|
|
for (auto I : PhiUp) {
|
|
|
|
dbgs() << "phi " << Print<NodeId>(I.first, DFG) << " -> {";
|
|
|
|
for (auto R : I.second)
|
|
|
|
dbgs() << ' ' << Print<NodeId>(R.first, DFG)
|
2016-10-04 01:14:48 +08:00
|
|
|
<< Print<RegisterAggr>(R.second, DFG);
|
2016-01-12 23:56:33 +08:00
|
|
|
dbgs() << " }\n";
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Propagate the reached registers up in the phi chain.
|
|
|
|
//
|
|
|
|
// The following type of situation needs careful handling:
|
|
|
|
//
|
|
|
|
// phi d1<R1:0> (1)
|
|
|
|
// |
|
|
|
|
// ... d2<R1>
|
|
|
|
// |
|
|
|
|
// phi u3<R1:0> (2)
|
|
|
|
// |
|
|
|
|
// ... u4<R1>
|
|
|
|
//
|
|
|
|
// The phi node (2) defines a register pair R1:0, and reaches a "real"
|
|
|
|
// use u4 of just R1. The same phi node is also known to reach (upwards)
|
|
|
|
// the phi node (1). However, the use u4 is not reached by phi (1),
|
|
|
|
// because of the intervening definition d2 of R1. The data flow between
|
|
|
|
// phis (1) and (2) is restricted to R1:0 minus R1, i.e. R0.
|
|
|
|
//
|
|
|
|
// When propagating uses up the phi chains, get the all reaching defs
|
|
|
|
// for a given phi use, and traverse the list until the propagated ref
|
2016-09-08 04:37:05 +08:00
|
|
|
// is covered, or until reaching the final phi. Only assume that the
|
|
|
|
// reference reaches the phi in the latter case.
|
2016-01-12 23:56:33 +08:00
|
|
|
|
|
|
|
for (unsigned i = 0; i < PhiUQ.size(); ++i) {
|
|
|
|
auto PA = DFG.addr<PhiNode*>(PhiUQ[i]);
|
2016-09-08 04:37:05 +08:00
|
|
|
NodeList PUs = PA.Addr->members_if(DFG.IsRef<NodeAttrs::Use>, DFG);
|
|
|
|
RefMap &RUM = RealUseMap[PA.Id];
|
|
|
|
|
2016-10-06 21:05:13 +08:00
|
|
|
for (NodeAddr<UseNode*> UA : PUs) {
|
2016-10-04 01:14:48 +08:00
|
|
|
std::map<NodeId,RegisterAggr> &PUM = PhiUp[UA.Id];
|
2016-10-20 00:30:56 +08:00
|
|
|
RegisterRef UR = DFG.normalizeRef(getRestrictedRegRef(UA));
|
2016-10-04 01:14:48 +08:00
|
|
|
for (const std::pair<NodeId,RegisterAggr> &P : PUM) {
|
2016-01-12 23:56:33 +08:00
|
|
|
bool Changed = false;
|
2016-10-04 01:14:48 +08:00
|
|
|
const RegisterAggr &MidDefs = P.second;
|
2016-09-08 04:37:05 +08:00
|
|
|
|
2016-10-20 00:30:56 +08:00
|
|
|
// Collect the set PropUp of uses that are reached by the current
|
|
|
|
// phi PA, and are not covered by any intervening def between the
|
|
|
|
// currently visited use UA and the the upward phi P.
|
|
|
|
|
|
|
|
if (MidDefs.hasCoverOf(UR))
|
2016-01-12 23:56:33 +08:00
|
|
|
continue;
|
2016-10-20 00:30:56 +08:00
|
|
|
|
|
|
|
// General algorithm:
|
|
|
|
// for each (R,U) : U is use node of R, U is reached by PA
|
|
|
|
// if MidDefs does not cover (R,U)
|
|
|
|
// then add (R-MidDefs,U) to RealUseMap[P]
|
|
|
|
//
|
|
|
|
for (const std::pair<RegisterId,NodeRefSet> &T : RUM) {
|
|
|
|
RegisterRef R = DFG.restrictRef(RegisterRef(T.first), UR);
|
|
|
|
if (!R)
|
|
|
|
continue;
|
|
|
|
for (std::pair<NodeId,LaneBitmask> V : T.second) {
|
|
|
|
RegisterRef S = DFG.restrictRef(RegisterRef(R.Reg, V.second), R);
|
|
|
|
if (!S)
|
|
|
|
continue;
|
|
|
|
if (RegisterRef SS = MidDefs.clearIn(S)) {
|
|
|
|
NodeRefSet &RS = RealUseMap[P.first][SS.Reg];
|
|
|
|
Changed |= RS.insert({V.first,SS.Mask}).second;
|
|
|
|
}
|
|
|
|
}
|
2016-01-12 23:56:33 +08:00
|
|
|
}
|
2016-10-20 00:30:56 +08:00
|
|
|
|
2016-01-12 23:56:33 +08:00
|
|
|
if (Changed)
|
2016-09-08 04:37:05 +08:00
|
|
|
PhiUQ.push_back(P.first);
|
2016-01-12 23:56:33 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (Trace) {
|
|
|
|
dbgs() << "Real use map:\n";
|
|
|
|
for (auto I : RealUseMap) {
|
|
|
|
dbgs() << "phi " << Print<NodeId>(I.first, DFG);
|
|
|
|
NodeAddr<PhiNode*> PA = DFG.addr<PhiNode*>(I.first);
|
|
|
|
NodeList Ds = PA.Addr->members_if(DFG.IsRef<NodeAttrs::Def>, DFG);
|
|
|
|
if (!Ds.empty()) {
|
2016-10-15 01:57:55 +08:00
|
|
|
RegisterRef RR = NodeAddr<DefNode*>(Ds[0]).Addr->getRegRef(DFG);
|
2016-01-12 23:56:33 +08:00
|
|
|
dbgs() << '<' << Print<RegisterRef>(RR, DFG) << '>';
|
|
|
|
} else {
|
|
|
|
dbgs() << "<noreg>";
|
|
|
|
}
|
|
|
|
dbgs() << " -> " << Print<RefMap>(I.second, DFG) << '\n';
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void Liveness::computeLiveIns() {
|
|
|
|
// Populate the node-to-block map. This speeds up the calculations
|
|
|
|
// significantly.
|
|
|
|
NBMap.clear();
|
|
|
|
for (NodeAddr<BlockNode*> BA : DFG.getFunc().Addr->members(DFG)) {
|
|
|
|
MachineBasicBlock *BB = BA.Addr->getCode();
|
|
|
|
for (NodeAddr<InstrNode*> IA : BA.Addr->members(DFG)) {
|
|
|
|
for (NodeAddr<RefNode*> RA : IA.Addr->members(DFG))
|
|
|
|
NBMap.insert(std::make_pair(RA.Id, BB));
|
|
|
|
NBMap.insert(std::make_pair(IA.Id, BB));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
MachineFunction &MF = DFG.getMF();
|
|
|
|
|
|
|
|
// Compute IDF first, then the inverse.
|
|
|
|
decltype(IIDF) IDF;
|
2016-10-06 21:05:13 +08:00
|
|
|
for (MachineBasicBlock &B : MF) {
|
2016-01-12 23:56:33 +08:00
|
|
|
auto F1 = MDF.find(&B);
|
|
|
|
if (F1 == MDF.end())
|
|
|
|
continue;
|
|
|
|
SetVector<MachineBasicBlock*> IDFB(F1->second.begin(), F1->second.end());
|
|
|
|
for (unsigned i = 0; i < IDFB.size(); ++i) {
|
|
|
|
auto F2 = MDF.find(IDFB[i]);
|
|
|
|
if (F2 != MDF.end())
|
|
|
|
IDFB.insert(F2->second.begin(), F2->second.end());
|
|
|
|
}
|
|
|
|
// Add B to the IDF(B). This will put B in the IIDF(B).
|
|
|
|
IDFB.insert(&B);
|
|
|
|
IDF[&B].insert(IDFB.begin(), IDFB.end());
|
|
|
|
}
|
|
|
|
|
|
|
|
for (auto I : IDF)
|
|
|
|
for (auto S : I.second)
|
|
|
|
IIDF[S].insert(I.first);
|
|
|
|
|
|
|
|
computePhiInfo();
|
|
|
|
|
|
|
|
NodeAddr<FuncNode*> FA = DFG.getFunc();
|
2016-10-06 21:05:13 +08:00
|
|
|
NodeList Blocks = FA.Addr->members(DFG);
|
2016-01-12 23:56:33 +08:00
|
|
|
|
|
|
|
// Build the phi live-on-entry map.
|
|
|
|
for (NodeAddr<BlockNode*> BA : Blocks) {
|
|
|
|
MachineBasicBlock *MB = BA.Addr->getCode();
|
2016-10-06 21:05:13 +08:00
|
|
|
RefMap &LON = PhiLON[MB];
|
2016-01-12 23:56:33 +08:00
|
|
|
for (auto P : BA.Addr->members_if(DFG.IsCode<NodeAttrs::Phi>, DFG))
|
2016-10-06 21:05:46 +08:00
|
|
|
for (const RefMap::value_type &S : RealUseMap[P.Id])
|
2016-01-12 23:56:33 +08:00
|
|
|
LON[S.first].insert(S.second.begin(), S.second.end());
|
|
|
|
}
|
|
|
|
|
|
|
|
if (Trace) {
|
|
|
|
dbgs() << "Phi live-on-entry map:\n";
|
2016-10-06 21:05:46 +08:00
|
|
|
for (auto &I : PhiLON)
|
2016-01-12 23:56:33 +08:00
|
|
|
dbgs() << "block #" << I.first->getNumber() << " -> "
|
|
|
|
<< Print<RefMap>(I.second, DFG) << '\n';
|
|
|
|
}
|
|
|
|
|
|
|
|
// Build the phi live-on-exit map. Each phi node has some set of reached
|
|
|
|
// "real" uses. Propagate this set backwards into the block predecessors
|
|
|
|
// through the reaching defs of the corresponding phi uses.
|
|
|
|
for (NodeAddr<BlockNode*> BA : Blocks) {
|
2016-10-06 21:05:13 +08:00
|
|
|
NodeList Phis = BA.Addr->members_if(DFG.IsCode<NodeAttrs::Phi>, DFG);
|
2016-01-12 23:56:33 +08:00
|
|
|
for (NodeAddr<PhiNode*> PA : Phis) {
|
2016-10-06 21:05:13 +08:00
|
|
|
RefMap &RUs = RealUseMap[PA.Id];
|
2016-01-12 23:56:33 +08:00
|
|
|
if (RUs.empty())
|
|
|
|
continue;
|
|
|
|
|
|
|
|
for (auto U : PA.Addr->members_if(DFG.IsRef<NodeAttrs::Use>, DFG)) {
|
2016-10-20 00:30:56 +08:00
|
|
|
NodeAddr<PhiUseNode*> PUA = U;
|
|
|
|
if (PUA.Addr->getReachingDef() == 0)
|
2016-01-12 23:56:33 +08:00
|
|
|
continue;
|
|
|
|
|
|
|
|
// Mark all reached "real" uses of P as live on exit in the
|
|
|
|
// predecessor.
|
|
|
|
// Remap all the RUs so that they have a correct reaching def.
|
2016-10-20 00:30:56 +08:00
|
|
|
auto PrA = DFG.addr<BlockNode*>(PUA.Addr->getPredecessor());
|
2016-10-06 21:05:13 +08:00
|
|
|
RefMap &LOX = PhiLOX[PrA.Addr->getCode()];
|
2016-10-20 00:30:56 +08:00
|
|
|
|
|
|
|
RegisterRef UR = DFG.normalizeRef(getRestrictedRegRef(PUA));
|
|
|
|
for (const std::pair<RegisterId,NodeRefSet> &T : RUs) {
|
|
|
|
// Check if T.first aliases UR?
|
2016-12-15 22:36:06 +08:00
|
|
|
LaneBitmask M;
|
2016-10-20 00:30:56 +08:00
|
|
|
for (std::pair<NodeId,LaneBitmask> P : T.second)
|
|
|
|
M |= P.second;
|
|
|
|
|
|
|
|
RegisterRef S = DFG.restrictRef(RegisterRef(T.first, M), UR);
|
|
|
|
if (!S)
|
2016-01-12 23:56:33 +08:00
|
|
|
continue;
|
2016-10-20 00:30:56 +08:00
|
|
|
for (NodeAddr<DefNode*> D : getAllReachingDefs(S, PUA))
|
|
|
|
LOX[S.Reg].insert({D.Id, S.Mask});
|
2016-01-12 23:56:33 +08:00
|
|
|
}
|
|
|
|
} // for U : phi uses
|
|
|
|
} // for P : Phis
|
|
|
|
} // for B : Blocks
|
|
|
|
|
|
|
|
if (Trace) {
|
|
|
|
dbgs() << "Phi live-on-exit map:\n";
|
2016-10-06 21:05:46 +08:00
|
|
|
for (auto &I : PhiLOX)
|
2016-01-12 23:56:33 +08:00
|
|
|
dbgs() << "block #" << I.first->getNumber() << " -> "
|
|
|
|
<< Print<RefMap>(I.second, DFG) << '\n';
|
|
|
|
}
|
|
|
|
|
|
|
|
RefMap LiveIn;
|
|
|
|
traverse(&MF.front(), LiveIn);
|
|
|
|
|
|
|
|
// Add function live-ins to the live-in set of the function entry block.
|
2017-01-31 00:20:30 +08:00
|
|
|
LiveMap[&MF.front()].insert(DFG.getLiveIns());
|
2016-01-12 23:56:33 +08:00
|
|
|
|
|
|
|
if (Trace) {
|
|
|
|
// Dump the liveness map
|
2016-10-06 21:05:13 +08:00
|
|
|
for (MachineBasicBlock &B : MF) {
|
2016-10-20 00:30:56 +08:00
|
|
|
std::vector<RegisterRef> LV;
|
2016-01-12 23:56:33 +08:00
|
|
|
for (auto I = B.livein_begin(), E = B.livein_end(); I != E; ++I)
|
2016-10-20 00:30:56 +08:00
|
|
|
LV.push_back(RegisterRef(I->PhysReg, I->LaneMask));
|
|
|
|
std::sort(LV.begin(), LV.end());
|
2016-01-12 23:56:33 +08:00
|
|
|
dbgs() << "BB#" << B.getNumber() << "\t rec = {";
|
2016-10-20 00:30:56 +08:00
|
|
|
for (auto I : LV)
|
|
|
|
dbgs() << ' ' << Print<RegisterRef>(I, DFG);
|
|
|
|
dbgs() << " }\n";
|
|
|
|
//dbgs() << "\tcomp = " << Print<RegisterAggr>(LiveMap[&B], DFG) << '\n';
|
|
|
|
|
|
|
|
LV.clear();
|
|
|
|
for (std::pair<RegisterId,LaneBitmask> P : LiveMap[&B]) {
|
|
|
|
MCSubRegIndexIterator S(P.first, &TRI);
|
|
|
|
if (!S.isValid()) {
|
|
|
|
LV.push_back(RegisterRef(P.first));
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
do {
|
|
|
|
LaneBitmask M = TRI.getSubRegIndexLaneMask(S.getSubRegIndex());
|
2016-12-17 03:11:56 +08:00
|
|
|
if ((M & P.second).any())
|
2016-10-20 00:30:56 +08:00
|
|
|
LV.push_back(RegisterRef(S.getSubReg()));
|
|
|
|
++S;
|
|
|
|
} while (S.isValid());
|
|
|
|
}
|
|
|
|
std::sort(LV.begin(), LV.end());
|
|
|
|
dbgs() << "\tcomp = {";
|
|
|
|
for (auto I : LV)
|
|
|
|
dbgs() << ' ' << Print<RegisterRef>(I, DFG);
|
2016-01-12 23:56:33 +08:00
|
|
|
dbgs() << " }\n";
|
2016-10-20 00:30:56 +08:00
|
|
|
|
2016-01-12 23:56:33 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void Liveness::resetLiveIns() {
|
|
|
|
for (auto &B : DFG.getMF()) {
|
|
|
|
// Remove all live-ins.
|
|
|
|
std::vector<unsigned> T;
|
|
|
|
for (auto I = B.livein_begin(), E = B.livein_end(); I != E; ++I)
|
|
|
|
T.push_back(I->PhysReg);
|
|
|
|
for (auto I : T)
|
|
|
|
B.removeLiveIn(I);
|
|
|
|
// Add the newly computed live-ins.
|
|
|
|
auto &LiveIns = LiveMap[&B];
|
|
|
|
for (auto I : LiveIns) {
|
2016-10-20 00:30:56 +08:00
|
|
|
B.addLiveIn({MCPhysReg(I.first), I.second});
|
2016-01-12 23:56:33 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void Liveness::resetKills() {
|
|
|
|
for (auto &B : DFG.getMF())
|
|
|
|
resetKills(&B);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void Liveness::resetKills(MachineBasicBlock *B) {
|
2016-10-20 00:30:56 +08:00
|
|
|
auto CopyLiveIns = [this] (MachineBasicBlock *B, BitVector &LV) -> void {
|
|
|
|
for (auto I : B->liveins()) {
|
|
|
|
MCSubRegIndexIterator S(I.PhysReg, &TRI);
|
|
|
|
if (!S.isValid()) {
|
|
|
|
LV.set(I.PhysReg);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
do {
|
|
|
|
LaneBitmask M = TRI.getSubRegIndexLaneMask(S.getSubRegIndex());
|
2016-12-17 03:11:56 +08:00
|
|
|
if ((M & I.LaneMask).any())
|
2016-10-20 00:30:56 +08:00
|
|
|
LV.set(S.getSubReg());
|
|
|
|
++S;
|
|
|
|
} while (S.isValid());
|
|
|
|
}
|
2016-01-12 23:56:33 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
BitVector LiveIn(TRI.getNumRegs()), Live(TRI.getNumRegs());
|
|
|
|
CopyLiveIns(B, LiveIn);
|
|
|
|
for (auto SI : B->successors())
|
|
|
|
CopyLiveIns(SI, Live);
|
|
|
|
|
|
|
|
for (auto I = B->rbegin(), E = B->rend(); I != E; ++I) {
|
|
|
|
MachineInstr *MI = &*I;
|
|
|
|
if (MI->isDebugValue())
|
|
|
|
continue;
|
|
|
|
|
|
|
|
MI->clearKillInfo();
|
|
|
|
for (auto &Op : MI->operands()) {
|
2016-06-02 22:30:09 +08:00
|
|
|
// An implicit def of a super-register may not necessarily start a
|
|
|
|
// live range of it, since an implicit use could be used to keep parts
|
|
|
|
// of it live. Instead of analyzing the implicit operands, ignore
|
|
|
|
// implicit defs.
|
|
|
|
if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
|
2016-01-12 23:56:33 +08:00
|
|
|
continue;
|
|
|
|
unsigned R = Op.getReg();
|
|
|
|
if (!TargetRegisterInfo::isPhysicalRegister(R))
|
|
|
|
continue;
|
|
|
|
for (MCSubRegIterator SR(R, &TRI, true); SR.isValid(); ++SR)
|
|
|
|
Live.reset(*SR);
|
|
|
|
}
|
|
|
|
for (auto &Op : MI->operands()) {
|
|
|
|
if (!Op.isReg() || !Op.isUse())
|
|
|
|
continue;
|
|
|
|
unsigned R = Op.getReg();
|
|
|
|
if (!TargetRegisterInfo::isPhysicalRegister(R))
|
|
|
|
continue;
|
|
|
|
bool IsLive = false;
|
2016-04-20 22:33:23 +08:00
|
|
|
for (MCRegAliasIterator AR(R, &TRI, true); AR.isValid(); ++AR) {
|
|
|
|
if (!Live[*AR])
|
2016-01-12 23:56:33 +08:00
|
|
|
continue;
|
|
|
|
IsLive = true;
|
|
|
|
break;
|
|
|
|
}
|
2017-01-24 07:03:49 +08:00
|
|
|
if (!IsLive)
|
|
|
|
Op.setIsKill(true);
|
2016-01-12 23:56:33 +08:00
|
|
|
for (MCSubRegIterator SR(R, &TRI, true); SR.isValid(); ++SR)
|
|
|
|
Live.set(*SR);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
RegisterRef Liveness::getRestrictedRegRef(NodeAddr<RefNode*> RA) const {
|
|
|
|
assert(DFG.IsRef<NodeAttrs::Use>(RA));
|
|
|
|
if (RA.Addr->getFlags() & NodeAttrs::Shadow) {
|
|
|
|
NodeId RD = RA.Addr->getReachingDef();
|
|
|
|
assert(RD);
|
|
|
|
RA = DFG.addr<DefNode*>(RD);
|
|
|
|
}
|
2016-10-15 01:57:55 +08:00
|
|
|
return RA.Addr->getRegRef(DFG);
|
2016-01-12 23:56:33 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// Helper function to obtain the basic block containing the reaching def
|
|
|
|
// of the given use.
|
|
|
|
MachineBasicBlock *Liveness::getBlockWithRef(NodeId RN) const {
|
|
|
|
auto F = NBMap.find(RN);
|
|
|
|
if (F != NBMap.end())
|
|
|
|
return F->second;
|
|
|
|
llvm_unreachable("Node id not in map");
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void Liveness::traverse(MachineBasicBlock *B, RefMap &LiveIn) {
|
|
|
|
// The LiveIn map, for each (physical) register, contains the set of live
|
|
|
|
// reaching defs of that register that are live on entry to the associated
|
|
|
|
// block.
|
|
|
|
|
|
|
|
// The summary of the traversal algorithm:
|
|
|
|
//
|
|
|
|
// R is live-in in B, if there exists a U(R), such that rdef(R) dom B
|
|
|
|
// and (U \in IDF(B) or B dom U).
|
|
|
|
//
|
|
|
|
// for (C : children) {
|
|
|
|
// LU = {}
|
|
|
|
// traverse(C, LU)
|
|
|
|
// LiveUses += LU
|
|
|
|
// }
|
|
|
|
//
|
|
|
|
// LiveUses -= Defs(B);
|
|
|
|
// LiveUses += UpwardExposedUses(B);
|
|
|
|
// for (C : IIDF[B])
|
|
|
|
// for (U : LiveUses)
|
|
|
|
// if (Rdef(U) dom C)
|
|
|
|
// C.addLiveIn(U)
|
|
|
|
//
|
|
|
|
|
|
|
|
// Go up the dominator tree (depth-first).
|
|
|
|
MachineDomTreeNode *N = MDT.getNode(B);
|
|
|
|
for (auto I : *N) {
|
|
|
|
RefMap L;
|
|
|
|
MachineBasicBlock *SB = I->getBlock();
|
|
|
|
traverse(SB, L);
|
|
|
|
|
|
|
|
for (auto S : L)
|
|
|
|
LiveIn[S.first].insert(S.second.begin(), S.second.end());
|
|
|
|
}
|
|
|
|
|
|
|
|
if (Trace) {
|
2016-10-20 08:22:23 +08:00
|
|
|
dbgs() << "\n-- BB#" << B->getNumber() << ": " << __func__
|
2016-10-04 04:17:20 +08:00
|
|
|
<< " after recursion into: {";
|
2016-01-12 23:56:33 +08:00
|
|
|
for (auto I : *N)
|
|
|
|
dbgs() << ' ' << I->getBlock()->getNumber();
|
2016-10-04 04:17:20 +08:00
|
|
|
dbgs() << " }\n";
|
|
|
|
dbgs() << " LiveIn: " << Print<RefMap>(LiveIn, DFG) << '\n';
|
2016-10-20 00:30:56 +08:00
|
|
|
dbgs() << " Local: " << Print<RegisterAggr>(LiveMap[B], DFG) << '\n';
|
2016-01-12 23:56:33 +08:00
|
|
|
}
|
|
|
|
|
2016-10-06 04:08:09 +08:00
|
|
|
// Add reaching defs of phi uses that are live on exit from this block.
|
2016-01-12 23:56:33 +08:00
|
|
|
RefMap &PUs = PhiLOX[B];
|
2016-10-06 21:05:46 +08:00
|
|
|
for (auto &S : PUs)
|
2016-01-12 23:56:33 +08:00
|
|
|
LiveIn[S.first].insert(S.second.begin(), S.second.end());
|
|
|
|
|
|
|
|
if (Trace) {
|
|
|
|
dbgs() << "after LOX\n";
|
|
|
|
dbgs() << " LiveIn: " << Print<RefMap>(LiveIn, DFG) << '\n';
|
2016-10-20 00:30:56 +08:00
|
|
|
dbgs() << " Local: " << Print<RegisterAggr>(LiveMap[B], DFG) << '\n';
|
2016-01-12 23:56:33 +08:00
|
|
|
}
|
|
|
|
|
2016-10-06 04:08:09 +08:00
|
|
|
// The LiveIn map at this point has all defs that are live-on-exit from B,
|
|
|
|
// as if they were live-on-entry to B. First, we need to filter out all
|
|
|
|
// defs that are present in this block. Then we will add reaching defs of
|
|
|
|
// all upward-exposed uses.
|
|
|
|
|
|
|
|
// To filter out the defs, first make a copy of LiveIn, and then re-populate
|
|
|
|
// LiveIn with the defs that should remain.
|
|
|
|
RefMap LiveInCopy = LiveIn;
|
2016-01-12 23:56:33 +08:00
|
|
|
LiveIn.clear();
|
|
|
|
|
2016-10-20 00:30:56 +08:00
|
|
|
for (const std::pair<RegisterId,NodeRefSet> &LE : LiveInCopy) {
|
|
|
|
RegisterRef LRef(LE.first);
|
|
|
|
NodeRefSet &NewDefs = LiveIn[LRef.Reg]; // To be filled.
|
|
|
|
const NodeRefSet &OldDefs = LE.second;
|
|
|
|
for (NodeRef OR : OldDefs) {
|
2016-10-06 04:08:09 +08:00
|
|
|
// R is a def node that was live-on-exit
|
2016-10-20 00:30:56 +08:00
|
|
|
auto DA = DFG.addr<DefNode*>(OR.first);
|
2016-01-12 23:56:33 +08:00
|
|
|
NodeAddr<InstrNode*> IA = DA.Addr->getOwner(DFG);
|
|
|
|
NodeAddr<BlockNode*> BA = IA.Addr->getOwner(DFG);
|
2016-10-06 04:08:09 +08:00
|
|
|
if (B != BA.Addr->getCode()) {
|
|
|
|
// Defs from a different block need to be preserved. Defs from this
|
|
|
|
// block will need to be processed further, except for phi defs, the
|
|
|
|
// liveness of which is handled through the PhiLON/PhiLOX maps.
|
2016-10-20 00:30:56 +08:00
|
|
|
NewDefs.insert(OR);
|
2016-10-06 04:08:09 +08:00
|
|
|
continue;
|
2016-01-12 23:56:33 +08:00
|
|
|
}
|
|
|
|
|
2016-10-06 04:08:09 +08:00
|
|
|
// Defs from this block need to stop the liveness from being
|
|
|
|
// propagated upwards. This only applies to non-preserving defs,
|
|
|
|
// and to the parts of the register actually covered by those defs.
|
|
|
|
// (Note that phi defs should always be preserving.)
|
2017-01-31 01:46:56 +08:00
|
|
|
RegisterAggr RRs(PRI);
|
2016-10-20 00:30:56 +08:00
|
|
|
LRef.Mask = OR.second;
|
2016-10-06 04:08:09 +08:00
|
|
|
|
|
|
|
if (!DFG.IsPreservingDef(DA)) {
|
|
|
|
assert(!(IA.Addr->getFlags() & NodeAttrs::Phi));
|
|
|
|
// DA is a non-phi def that is live-on-exit from this block, and
|
|
|
|
// that is also located in this block. LRef is a register ref
|
|
|
|
// whose use this def reaches. If DA covers LRef, then no part
|
2016-10-20 00:30:56 +08:00
|
|
|
// of LRef is exposed upwards.A
|
2016-10-15 01:57:55 +08:00
|
|
|
if (RRs.insert(DA.Addr->getRegRef(DFG)).hasCoverOf(LRef))
|
2016-10-06 04:08:09 +08:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
// DA itself was not sufficient to cover LRef. In general, it is
|
|
|
|
// the last in a chain of aliased defs before the exit from this block.
|
|
|
|
// There could be other defs in this block that are a part of that
|
|
|
|
// chain. Check that now: accumulate the registers from these defs,
|
|
|
|
// and if they all together cover LRef, it is not live-on-entry.
|
2016-01-12 23:56:33 +08:00
|
|
|
for (NodeAddr<DefNode*> TA : getAllReachingDefs(DA)) {
|
2016-10-06 04:08:09 +08:00
|
|
|
// DefNode -> InstrNode -> BlockNode.
|
|
|
|
NodeAddr<InstrNode*> ITA = TA.Addr->getOwner(DFG);
|
|
|
|
NodeAddr<BlockNode*> BTA = ITA.Addr->getOwner(DFG);
|
|
|
|
// Reaching defs are ordered in the upward direction.
|
|
|
|
if (BTA.Addr->getCode() != B) {
|
|
|
|
// We have reached past the beginning of B, and the accumulated
|
|
|
|
// registers are not covering LRef. The first def from the
|
|
|
|
// upward chain will be live.
|
2016-10-20 00:30:56 +08:00
|
|
|
// Subtract all accumulated defs (RRs) from LRef.
|
2017-01-31 01:46:56 +08:00
|
|
|
RegisterAggr L(PRI);
|
2016-10-20 00:30:56 +08:00
|
|
|
L.insert(LRef).clear(RRs);
|
|
|
|
assert(!L.empty());
|
|
|
|
NewDefs.insert({TA.Id,L.begin()->second});
|
2016-10-06 04:08:09 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
// TA is in B. Only add this def to the accumulated cover if it is
|
|
|
|
// not preserving.
|
2016-01-12 23:56:33 +08:00
|
|
|
if (!(TA.Addr->getFlags() & NodeAttrs::Preserving))
|
2016-10-15 01:57:55 +08:00
|
|
|
RRs.insert(TA.Addr->getRegRef(DFG));
|
2016-10-06 04:08:09 +08:00
|
|
|
// If this is enough to cover LRef, then stop.
|
|
|
|
if (RRs.hasCoverOf(LRef))
|
2016-01-12 23:56:33 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
emptify(LiveIn);
|
|
|
|
|
|
|
|
if (Trace) {
|
|
|
|
dbgs() << "after defs in block\n";
|
|
|
|
dbgs() << " LiveIn: " << Print<RefMap>(LiveIn, DFG) << '\n';
|
2016-10-20 00:30:56 +08:00
|
|
|
dbgs() << " Local: " << Print<RegisterAggr>(LiveMap[B], DFG) << '\n';
|
2016-01-12 23:56:33 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Scan the block for upward-exposed uses and add them to the tracking set.
|
|
|
|
for (auto I : DFG.getFunc().Addr->findBlock(B, DFG).Addr->members(DFG)) {
|
|
|
|
NodeAddr<InstrNode*> IA = I;
|
|
|
|
if (IA.Addr->getKind() != NodeAttrs::Stmt)
|
|
|
|
continue;
|
|
|
|
for (NodeAddr<UseNode*> UA : IA.Addr->members_if(DFG.IsUse, DFG)) {
|
2016-09-08 04:10:56 +08:00
|
|
|
if (UA.Addr->getFlags() & NodeAttrs::Undef)
|
|
|
|
continue;
|
2016-10-20 00:30:56 +08:00
|
|
|
RegisterRef RR = DFG.normalizeRef(UA.Addr->getRegRef(DFG));
|
2016-10-06 21:05:13 +08:00
|
|
|
for (NodeAddr<DefNode*> D : getAllReachingDefs(UA))
|
2016-01-12 23:56:33 +08:00
|
|
|
if (getBlockWithRef(D.Id) != B)
|
2016-10-20 00:30:56 +08:00
|
|
|
LiveIn[RR.Reg].insert({D.Id,RR.Mask});
|
2016-01-12 23:56:33 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (Trace) {
|
|
|
|
dbgs() << "after uses in block\n";
|
|
|
|
dbgs() << " LiveIn: " << Print<RefMap>(LiveIn, DFG) << '\n';
|
2016-10-20 00:30:56 +08:00
|
|
|
dbgs() << " Local: " << Print<RegisterAggr>(LiveMap[B], DFG) << '\n';
|
2016-01-12 23:56:33 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Phi uses should not be propagated up the dominator tree, since they
|
|
|
|
// are not dominated by their corresponding reaching defs.
|
2016-10-20 00:30:56 +08:00
|
|
|
RegisterAggr &Local = LiveMap[B];
|
2016-10-06 21:05:13 +08:00
|
|
|
RefMap &LON = PhiLON[B];
|
2016-10-20 00:30:56 +08:00
|
|
|
for (auto &R : LON) {
|
2016-12-15 22:36:06 +08:00
|
|
|
LaneBitmask M;
|
2016-10-20 00:30:56 +08:00
|
|
|
for (auto P : R.second)
|
|
|
|
M |= P.second;
|
|
|
|
Local.insert(RegisterRef(R.first,M));
|
|
|
|
}
|
2016-01-12 23:56:33 +08:00
|
|
|
|
|
|
|
if (Trace) {
|
|
|
|
dbgs() << "after phi uses in block\n";
|
|
|
|
dbgs() << " LiveIn: " << Print<RefMap>(LiveIn, DFG) << '\n';
|
2016-10-20 00:30:56 +08:00
|
|
|
dbgs() << " Local: " << Print<RegisterAggr>(Local, DFG) << '\n';
|
2016-01-12 23:56:33 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
for (auto C : IIDF[B]) {
|
2016-10-20 00:30:56 +08:00
|
|
|
RegisterAggr &LiveC = LiveMap[C];
|
|
|
|
for (const std::pair<RegisterId,NodeRefSet> &S : LiveIn)
|
2016-01-12 23:56:33 +08:00
|
|
|
for (auto R : S.second)
|
2016-10-20 00:30:56 +08:00
|
|
|
if (MDT.properlyDominates(getBlockWithRef(R.first), C))
|
|
|
|
LiveC.insert(RegisterRef(S.first, R.second));
|
2016-01-12 23:56:33 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void Liveness::emptify(RefMap &M) {
|
|
|
|
for (auto I = M.begin(), E = M.end(); I != E; )
|
|
|
|
I = I->second.empty() ? M.erase(I) : std::next(I);
|
|
|
|
}
|
|
|
|
|