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llvm-project/llvm/test/CodeGen/PowerPC/swaps-le-6.ll

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[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr8 -ppc-vsr-nums-as-vr \
[PowerPC] Improve codegen for vector loads using scalar_to_vector This patch aims to improve the codegen for vector loads involving the scalar_to_vector (load X) sequence. Initially, ld->mv instructions were used for scalar_to_vector (load X), so this patch allows scalar_to_vector (load X) to utilize: LXSD and LXSDX for i64 and f64 LXSIWAX for i32 (sign extension to i64) LXSIWZX for i32 and f64 Committing on behalf of Amy Kwan. Differential Revision: https://reviews.llvm.org/D48950 llvm-svn: 339260
2018-08-08 23:20:43 +08:00
; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -O3 < %s | FileCheck %s
[Power9] Add exploitation of non-permuting memory ops This patch corresponds to review: https://reviews.llvm.org/D19825 The new lxvx/stxvx instructions do not require the swaps to line the elements up correctly. In order to select them over the lxvd2x/lxvw4x instructions which require swaps, the patterns for the old instruction have a predicate that ensures they won't be selected on Power9 and newer CPUs. llvm-svn: 282143
2016-09-22 17:52:19 +08:00
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \
[PowerPC] Improve codegen for vector loads using scalar_to_vector This patch aims to improve the codegen for vector loads involving the scalar_to_vector (load X) sequence. Initially, ld->mv instructions were used for scalar_to_vector (load X), so this patch allows scalar_to_vector (load X) to utilize: LXSD and LXSDX for i64 and f64 LXSIWAX for i32 (sign extension to i64) LXSIWZX for i32 and f64 Committing on behalf of Amy Kwan. Differential Revision: https://reviews.llvm.org/D48950 llvm-svn: 339260
2018-08-08 23:20:43 +08:00
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \
; RUN: < %s | FileCheck %s --check-prefix=CHECK-P9 \
[Power9] Add exploitation of non-permuting memory ops This patch corresponds to review: https://reviews.llvm.org/D19825 The new lxvx/stxvx instructions do not require the swaps to line the elements up correctly. In order to select them over the lxvd2x/lxvw4x instructions which require swaps, the patterns for the old instruction have a predicate that ensures they won't be selected on Power9 and newer CPUs. llvm-svn: 282143
2016-09-22 17:52:19 +08:00
; RUN: --implicit-check-not xxswapd
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-05 04:14:57 +08:00
; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \
[PowerPC] Improve codegen for vector loads using scalar_to_vector This patch aims to improve the codegen for vector loads involving the scalar_to_vector (load X) sequence. Initially, ld->mv instructions were used for scalar_to_vector (load X), so this patch allows scalar_to_vector (load X) to utilize: LXSD and LXSDX for i64 and f64 LXSIWAX for i32 (sign extension to i64) LXSIWZX for i32 and f64 Committing on behalf of Amy Kwan. Differential Revision: https://reviews.llvm.org/D48950 llvm-svn: 339260
2018-08-08 23:20:43 +08:00
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \
; RUN: -mattr=-power9-vector < %s | FileCheck %s
[PPC64LE] More vector swap optimization TLC This makes one substantive change and a few stylistic changes to the VSX swap optimization pass. The substantive change is to permit LXSDX and LXSSPX instructions to participate in swap optimization computations. The previous change to insert a swap following a SUBREG_TO_REG widening operation makes this almost trivial. I experimented with also permitting STXSDX and STXSSPX instructions. This can be done using similar techniques: we could insert a swap prior to a narrowing COPY operation, and then permit these stores to participate. I prototyped this, but discovered that the pattern of a narrowing COPY followed by an STXSDX does not occur in any of our test-suite code. So instead, I added commentary indicating that this could be done. Other TLC: - I changed SH_COPYSCALAR to SH_COPYWIDEN to more clearly indicate the direction of the copy. - I factored the insertion of swap instructions into a separate function. Finally, I added a new test case to check that the scalar-to-vector loads are working properly with swap optimization. llvm-svn: 242838
2015-07-22 05:40:17 +08:00
; These tests verify that VSX swap optimization works when loading a scalar
; into a vector register.
@x = global <2 x double> <double 9.970000e+01, double -1.032220e+02>, align 16
@z = global <2 x double> <double 2.332000e+01, double 3.111111e+01>, align 16
@y = global double 1.780000e+00, align 8
define void @bar0() {
[PowerPC] Improve codegen for vector loads using scalar_to_vector This patch aims to improve the codegen for vector loads involving the scalar_to_vector (load X) sequence. Initially, ld->mv instructions were used for scalar_to_vector (load X), so this patch allows scalar_to_vector (load X) to utilize: LXSD and LXSDX for i64 and f64 LXSIWAX for i32 (sign extension to i64) LXSIWZX for i32 and f64 Committing on behalf of Amy Kwan. Differential Revision: https://reviews.llvm.org/D48950 llvm-svn: 339260
2018-08-08 23:20:43 +08:00
; CHECK-LABEL: bar0:
; CHECK: # %bb.0: # %entry
; CHECK: addis r3, r2, .LC0@toc@ha
; CHECK: addis r4, r2, .LC1@toc@ha
; CHECK: ld r3, .LC0@toc@l(r3)
; CHECK: addis r3, r2, .LC2@toc@ha
; CHECK: ld r3, .LC2@toc@l(r3)
; CHECK: xxpermdi vs0, vs0, vs1, 1
; CHECK: stxvd2x vs0, 0, r3
; CHECK: blr
;
; CHECK-P9-LABEL: bar0:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9: addis r3, r2, .LC0@toc@ha
; CHECK-P9: addis r4, r2, .LC1@toc@ha
; CHECK-P9: ld r3, .LC0@toc@l(r3)
; CHECK-P9: ld r4, .LC1@toc@l(r4)
; CHECK-P9: lfd f0, 0(r3)
; CHECK-P9: lxvx vs1, 0, r4
; CHECK-P9: addis r3, r2, .LC2@toc@ha
; CHECK-P9: ld r3, .LC2@toc@l(r3)
; CHECK-P9: xxpermdi vs0, f0, f0, 2
; CHECK-P9: xxpermdi vs0, vs1, vs0, 1
; CHECK-P9: stxvx vs0, 0, r3
; CHECK-P9: blr
[PPC64LE] More vector swap optimization TLC This makes one substantive change and a few stylistic changes to the VSX swap optimization pass. The substantive change is to permit LXSDX and LXSSPX instructions to participate in swap optimization computations. The previous change to insert a swap following a SUBREG_TO_REG widening operation makes this almost trivial. I experimented with also permitting STXSDX and STXSSPX instructions. This can be done using similar techniques: we could insert a swap prior to a narrowing COPY operation, and then permit these stores to participate. I prototyped this, but discovered that the pattern of a narrowing COPY followed by an STXSDX does not occur in any of our test-suite code. So instead, I added commentary indicating that this could be done. Other TLC: - I changed SH_COPYSCALAR to SH_COPYWIDEN to more clearly indicate the direction of the copy. - I factored the insertion of swap instructions into a separate function. Finally, I added a new test case to check that the scalar-to-vector loads are working properly with swap optimization. llvm-svn: 242838
2015-07-22 05:40:17 +08:00
entry:
%0 = load <2 x double>, <2 x double>* @x, align 16
%1 = load double, double* @y, align 8
%vecins = insertelement <2 x double> %0, double %1, i32 0
store <2 x double> %vecins, <2 x double>* @z, align 16
ret void
}
define void @bar1() {
[PowerPC] Improve codegen for vector loads using scalar_to_vector This patch aims to improve the codegen for vector loads involving the scalar_to_vector (load X) sequence. Initially, ld->mv instructions were used for scalar_to_vector (load X), so this patch allows scalar_to_vector (load X) to utilize: LXSD and LXSDX for i64 and f64 LXSIWAX for i32 (sign extension to i64) LXSIWZX for i32 and f64 Committing on behalf of Amy Kwan. Differential Revision: https://reviews.llvm.org/D48950 llvm-svn: 339260
2018-08-08 23:20:43 +08:00
; CHECK-LABEL: bar1:
; CHECK: # %bb.0: # %entry
; CHECK: addis r3, r2, .LC0@toc@ha
; CHECK: addis r4, r2, .LC1@toc@ha
; CHECK: ld r3, .LC0@toc@l(r3)
; CHECK: addis r3, r2, .LC2@toc@ha
; CHECK: ld r3, .LC2@toc@l(r3)
; CHECK: xxmrghd vs0, vs1, vs0
; CHECK: stxvd2x vs0, 0, r3
; CHECK: blr
;
; CHECK-P9-LABEL: bar1:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9: addis r3, r2, .LC0@toc@ha
; CHECK-P9: addis r4, r2, .LC1@toc@ha
; CHECK-P9: ld r3, .LC0@toc@l(r3)
; CHECK-P9: ld r4, .LC1@toc@l(r4)
; CHECK-P9: lfd f0, 0(r3)
; CHECK-P9: lxvx vs1, 0, r4
; CHECK-P9: addis r3, r2, .LC2@toc@ha
; CHECK-P9: ld r3, .LC2@toc@l(r3)
; CHECK-P9: xxpermdi vs0, f0, f0, 2
; CHECK-P9: xxmrgld vs0, vs0, vs1
; CHECK-P9: stxvx vs0, 0, r3
; CHECK-P9: blr
[PPC64LE] More vector swap optimization TLC This makes one substantive change and a few stylistic changes to the VSX swap optimization pass. The substantive change is to permit LXSDX and LXSSPX instructions to participate in swap optimization computations. The previous change to insert a swap following a SUBREG_TO_REG widening operation makes this almost trivial. I experimented with also permitting STXSDX and STXSSPX instructions. This can be done using similar techniques: we could insert a swap prior to a narrowing COPY operation, and then permit these stores to participate. I prototyped this, but discovered that the pattern of a narrowing COPY followed by an STXSDX does not occur in any of our test-suite code. So instead, I added commentary indicating that this could be done. Other TLC: - I changed SH_COPYSCALAR to SH_COPYWIDEN to more clearly indicate the direction of the copy. - I factored the insertion of swap instructions into a separate function. Finally, I added a new test case to check that the scalar-to-vector loads are working properly with swap optimization. llvm-svn: 242838
2015-07-22 05:40:17 +08:00
entry:
%0 = load <2 x double>, <2 x double>* @x, align 16
%1 = load double, double* @y, align 8
%vecins = insertelement <2 x double> %0, double %1, i32 1
store <2 x double> %vecins, <2 x double>* @z, align 16
ret void
}