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llvm-project/llvm/test/CodeGen/MSP430/fp.ll

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Fix fallout from RegInfo => FrameLowering refactoring on MSP430. Patch by Job Noorman! llvm-svn: 166108
2012-10-18 01:37:11 +08:00
; RUN: llc -O0 -disable-fp-elim < %s | FileCheck %s
target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"
target triple = "msp430---elf"
define void @fp() nounwind {
entry:
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; CHECK-LABEL: fp:
[MSP430] Add MC layer Summary: This change implements assembler parser, code emitter, ELF object writer and disassembler for the MSP430 ISA. Also, more instruction forms are added to the target description. Reviewers: asl Reviewed By: asl Subscribers: pftbest, krisb, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D53661 llvm-svn: 346374
2018-11-08 08:03:45 +08:00
; CHECK: push r4
; CHECK: mov r1, r4
; CHECK: sub #2, r1
Fix fallout from RegInfo => FrameLowering refactoring on MSP430. Patch by Job Noorman! llvm-svn: 166108
2012-10-18 01:37:11 +08:00
%i = alloca i16, align 2
[MSP430] Add MC layer Summary: This change implements assembler parser, code emitter, ELF object writer and disassembler for the MSP430 ISA. Also, more instruction forms are added to the target description. Reviewers: asl Reviewed By: asl Subscribers: pftbest, krisb, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D53661 llvm-svn: 346374
2018-11-08 08:03:45 +08:00
; CHECK: clr -2(r4)
Fix fallout from RegInfo => FrameLowering refactoring on MSP430. Patch by Job Noorman! llvm-svn: 166108
2012-10-18 01:37:11 +08:00
store i16 0, i16* %i, align 2
[MSP430] Add MC layer Summary: This change implements assembler parser, code emitter, ELF object writer and disassembler for the MSP430 ISA. Also, more instruction forms are added to the target description. Reviewers: asl Reviewed By: asl Subscribers: pftbest, krisb, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D53661 llvm-svn: 346374
2018-11-08 08:03:45 +08:00
; CHECK: pop r4
Fix fallout from RegInfo => FrameLowering refactoring on MSP430. Patch by Job Noorman! llvm-svn: 166108
2012-10-18 01:37:11 +08:00
ret void
}
Mark FPB as a reserved register when needed. llvm-svn: 205421
2014-04-02 21:13:56 +08:00
; Due to FPB not being marked as reserved, the register allocator used to select
; r4 as the register for the "r" constraint below. This test verifies that this
; does not happen anymore. Note that the only reason an ISR is used here is that
; the register allocator selects r4 first instead of fifth in a normal function.
define msp430_intrcc void @fpb_alloced() #0 {
Fix broken FileCheck prefixes llvm-svn: 209538
2014-05-24 03:06:24 +08:00
; CHECK-LABEL: fpb_alloced:
Mark FPB as a reserved register when needed. llvm-svn: 205421
2014-04-02 21:13:56 +08:00
; CHECK-NOT: mov.b #0, r4
; CHECK: nop
call void asm sideeffect "nop", "r"(i8 0)
ret void
}