2017-10-20 05:37:38 +08:00
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//===-- RISCVSubtarget.h - Define Subtarget for the RISCV -------*- C++ -*-===//
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//
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2019-01-19 16:50:56 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2017-10-20 05:37:38 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the RISCV specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
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#define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
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#include "RISCVFrameLowering.h"
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#include "RISCVISelLowering.h"
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#include "RISCVInstrInfo.h"
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2019-03-09 17:28:06 +08:00
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#include "Utils/RISCVBaseInfo.h"
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[RISCV GlobalISel] Adding initial GlobalISel infrastructure
Summary:
Add an initial GlobalISel skeleton for RISCV. It can only run ir translator for `ret void`.
Patch by Andrew Wei
Reviewers: asb, sabuasal, apazos, lenary, simoncook, lewis-revill, edward-jones, rogfer01, xiangzhai, rovka, Petar.Avramovic, mgorny, dsanders
Reviewed By: dsanders
Subscribers: pzheng, s.egerton, dsanders, hiraditya, rbar, johnrusso, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, psnobl, benna, Jim, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65219
llvm-svn: 369467
2019-08-21 06:53:24 +08:00
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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2017-10-20 05:37:38 +08:00
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#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
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2017-11-17 09:07:10 +08:00
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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2017-10-20 05:37:38 +08:00
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#include "llvm/IR/DataLayout.h"
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#include "llvm/Target/TargetMachine.h"
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#define GET_SUBTARGETINFO_HEADER
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#include "RISCVGenSubtargetInfo.inc"
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namespace llvm {
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class StringRef;
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class RISCVSubtarget : public RISCVGenSubtargetInfo {
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virtual void anchor();
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2017-11-09 23:00:03 +08:00
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bool HasStdExtM = false;
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bool HasStdExtA = false;
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2017-12-07 18:26:05 +08:00
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bool HasStdExtF = false;
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2017-12-07 18:46:23 +08:00
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bool HasStdExtD = false;
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2017-12-07 20:50:32 +08:00
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bool HasStdExtC = false;
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2017-10-20 05:37:38 +08:00
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bool HasRV64 = false;
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2019-03-22 19:21:40 +08:00
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bool IsRV32E = false;
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2018-05-15 09:28:50 +08:00
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bool EnableLinkerRelax = false;
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2019-08-21 22:00:58 +08:00
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bool EnableRVCHintInstrs = false;
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2017-10-20 05:37:38 +08:00
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unsigned XLen = 32;
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MVT XLenVT = MVT::i32;
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2019-03-09 17:28:06 +08:00
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RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
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2017-10-20 05:37:38 +08:00
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RISCVFrameLowering FrameLowering;
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RISCVInstrInfo InstrInfo;
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RISCVRegisterInfo RegInfo;
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RISCVTargetLowering TLInfo;
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SelectionDAGTargetInfo TSInfo;
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/// Initializes using the passed in CPU and feature strings so that we can
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/// use initializer lists for subtarget initialization.
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2019-03-09 17:28:06 +08:00
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RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
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StringRef CPU, StringRef FS,
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StringRef ABIName);
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2017-10-20 05:37:38 +08:00
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public:
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// Initializes the data members to match that of the specified triple.
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2019-02-19 22:42:00 +08:00
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RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
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2019-03-09 17:28:06 +08:00
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StringRef ABIName, const TargetMachine &TM);
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2017-10-20 05:37:38 +08:00
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// Parses features string setting specified subtarget options. The
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// definition of this function is auto-generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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const RISCVFrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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}
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const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; }
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const RISCVRegisterInfo *getRegisterInfo() const override {
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return &RegInfo;
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}
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const RISCVTargetLowering *getTargetLowering() const override {
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return &TLInfo;
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}
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const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
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return &TSInfo;
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}
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2019-09-17 19:15:35 +08:00
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bool enableMachineScheduler() const override { return true; }
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2017-11-09 22:46:30 +08:00
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bool hasStdExtM() const { return HasStdExtM; }
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2017-11-09 23:00:03 +08:00
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bool hasStdExtA() const { return HasStdExtA; }
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2017-12-07 18:26:05 +08:00
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bool hasStdExtF() const { return HasStdExtF; }
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2017-12-07 18:46:23 +08:00
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bool hasStdExtD() const { return HasStdExtD; }
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2017-12-07 20:50:32 +08:00
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bool hasStdExtC() const { return HasStdExtC; }
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2017-10-20 05:37:38 +08:00
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bool is64Bit() const { return HasRV64; }
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2019-03-22 19:21:40 +08:00
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bool isRV32E() const { return IsRV32E; }
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2018-05-15 09:28:50 +08:00
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bool enableLinkerRelax() const { return EnableLinkerRelax; }
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2019-08-21 22:00:58 +08:00
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bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }
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2017-10-20 05:37:38 +08:00
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MVT getXLenVT() const { return XLenVT; }
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unsigned getXLen() const { return XLen; }
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2019-03-09 17:28:06 +08:00
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RISCVABI::ABI getTargetABI() const { return TargetABI; }
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[RISCV GlobalISel] Adding initial GlobalISel infrastructure
Summary:
Add an initial GlobalISel skeleton for RISCV. It can only run ir translator for `ret void`.
Patch by Andrew Wei
Reviewers: asb, sabuasal, apazos, lenary, simoncook, lewis-revill, edward-jones, rogfer01, xiangzhai, rovka, Petar.Avramovic, mgorny, dsanders
Reviewed By: dsanders
Subscribers: pzheng, s.egerton, dsanders, hiraditya, rbar, johnrusso, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, psnobl, benna, Jim, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65219
llvm-svn: 369467
2019-08-21 06:53:24 +08:00
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protected:
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// GlobalISel related APIs.
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std::unique_ptr<CallLowering> CallLoweringInfo;
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std::unique_ptr<InstructionSelector> InstSelector;
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std::unique_ptr<LegalizerInfo> Legalizer;
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std::unique_ptr<RegisterBankInfo> RegBankInfo;
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public:
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const CallLowering *getCallLowering() const override;
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InstructionSelector *getInstructionSelector() const override;
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const LegalizerInfo *getLegalizerInfo() const override;
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const RegisterBankInfo *getRegBankInfo() const override;
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2017-10-20 05:37:38 +08:00
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};
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} // End llvm namespace
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#endif
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