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llvm-project/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt

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[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux -mcpu=mips64r3 | FileCheck %s
# CHECK: .text
0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7
0x20 0x48 0xc7 0x00 # CHECK: add $9, $6, $7
0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
0x40 0x32 0x07 0x46 # CHECK: add.s $f9, $f6, $f7
0x67 0x45 0xc9 0x20 # CHECK: addi $9, $6, 17767
0x67 0xc5 0xc9 0x24 # CHECK: addiu $9, $6, -15001
0x21 0x48 0xc7 0x00 # CHECK: addu $9, $6, $7
0x24 0x48 0xc7 0x00 # CHECK: and $9, $6, $7
0x67 0x45 0xc9 0x30 # CHECK: andi $9, $6, 17767
0x4c 0x01 0x00 0x10 # CHECK: b 1332
0x4c 0x01 0x00 0x45 # CHECK: bc1f 1332
0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
0x4c 0x01 0x1d 0x45 # CHECK: bc1t $fcc7, 1332
0x4c 0x01 0x26 0x11 # CHECK: beq $9, $6, 1332
0x4c 0x01 0xc1 0x04 # CHECK: bgez $6, 1332
0x4c 0x01 0xd1 0x04 # CHECK: bgezal $6, 1332
0x4c 0x01 0xc0 0x1c # CHECK: bgtz $6, 1332
0x4c 0x01 0xc0 0x18 # CHECK: blez $6, 1332
0x4c 0x01 0x26 0x15 # CHECK: bne $9, $6, 1332
[mips] Correct the predicates for special nops, tlb ctrl instrs, software breakpoint and prefx. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44436 llvm-svn: 329905
2018-04-12 20:37:02 +08:00
0x40 0x01 0x00 0x00 # CHECK: pause
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
0x32 0x30 0x07 0x46 # CHECK: c.eq.s $f6, $f7
0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
0x30 0x30 0x07 0x46 # CHECK: c.f.s $f6, $f7
0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
0x3e 0x30 0x07 0x46 # CHECK: c.le.s $f6, $f7
0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
0x3c 0x30 0x07 0x46 # CHECK: c.lt.s $f6, $f7
0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
0x3d 0x30 0x07 0x46 # CHECK: c.nge.s $f6, $f7
0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
0x3b 0x30 0x07 0x46 # CHECK: c.ngl.s $f6, $f7
0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14
0x39 0x30 0x07 0x46 # CHECK: c.ngle.s $f6, $f7
0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
0x3f 0x30 0x07 0x46 # CHECK: c.ngt.s $f6, $f7
0x36 0x60 0x2e 0x46 # CHECK: c.ole.d $f12, $f14
0x36 0x30 0x07 0x46 # CHECK: c.ole.s $f6, $f7
0x34 0x60 0x2e 0x46 # CHECK: c.olt.d $f12, $f14
0x34 0x30 0x07 0x46 # CHECK: c.olt.s $f6, $f7
0x3a 0x60 0x2e 0x46 # CHECK: c.seq.d $f12, $f14
0x3a 0x30 0x07 0x46 # CHECK: c.seq.s $f6, $f7
0x38 0x60 0x2e 0x46 # CHECK: c.sf.d $f12, $f14
0x38 0x30 0x07 0x46 # CHECK: c.sf.s $f6, $f7
0x33 0x60 0x2e 0x46 # CHECK: c.ueq.d $f12, $f14
0x33 0xe0 0x12 0x46 # CHECK: c.ueq.s $f28, $f18
0x37 0x60 0x2e 0x46 # CHECK: c.ule.d $f12, $f14
0x37 0x30 0x07 0x46 # CHECK: c.ule.s $f6, $f7
0x35 0x60 0x2e 0x46 # CHECK: c.ult.d $f12, $f14
0x35 0x30 0x07 0x46 # CHECK: c.ult.s $f6, $f7
0x31 0x60 0x2e 0x46 # CHECK: c.un.d $f12, $f14
0x31 0x30 0x07 0x46 # CHECK: c.un.s $f6, $f7
0x4a 0x18 0x20 0x46 # CHECK: ceil.l.d $f1, $f3
0x8a 0x6c 0x00 0x46 # CHECK: ceil.l.s $f18, $f13
0x0e 0x73 0x20 0x46 # CHECK: ceil.w.d $f12, $f14
0x8e 0x39 0x00 0x46 # CHECK: ceil.w.s $f6, $f7
0x00 0x38 0x46 0x44 # CHECK: cfc1 $6, $7
0x21 0x30 0xe6 0x70 # CHECK: clo $6, $7
0x20 0x30 0xe6 0x70 # CHECK: clz $6, $7
0x00 0x38 0xc6 0x44 # CHECK: ctc1 $6, $7
0x21 0x81 0xa0 0x46 # CHECK: cvt.d.l $f4, $f16
0xa1 0x39 0x00 0x46 # CHECK: cvt.d.s $f6, $f7
0x21 0x73 0x80 0x46 # CHECK: cvt.d.w $f12, $f14
0x25 0x73 0x20 0x46 # CHECK: cvt.l.d $f12, $f14
0xa5 0x39 0x00 0x46 # CHECK: cvt.l.s $f6, $f7
0xe0 0xf3 0xa0 0x46 # CHECK: cvt.s.l $f15, $f30
0x20 0x73 0x20 0x46 # CHECK: cvt.s.d $f12, $f14
0xa0 0x39 0x80 0x46 # CHECK: cvt.s.w $f6, $f7
0x24 0x73 0x20 0x46 # CHECK: cvt.w.d $f12, $f14
0xa4 0x39 0x00 0x46 # CHECK: cvt.w.s $f6, $f7
0x2c 0x98 0x3f 0x00 # CHECK: dadd $19, $1, $ra
0xc7 0x93 0x9d 0x62 # CHECK: daddi $sp, $20, -27705
0xc7 0x93 0xbd 0x63 # CHECK: daddi $sp, $sp, -27705
0xc7 0x93 0x9d 0x62 # CHECK: daddi $sp, $20, -27705
0xc7 0x93 0x9d 0x62 # CHECK: daddi $sp, $20, -27705
0xc7 0x93 0xbd 0x63 # CHECK: daddi $sp, $sp, -27705
0x16 0xee 0xda 0x66 # CHECK: daddiu $26, $22, -4586
0x2d 0x98 0x3f 0x00 # CHECK: daddu $19, $1, $ra
0x9f 0x46 0x58 0x64 # CHECK: daddiu $24, $2, 18079
0x3f 0x69 0x73 0x66 # CHECK: daddiu $19, $19, 26943
0x25 0x90 0xd2 0x70 # CHECK: dclo $18, $6
0x24 0x80 0x30 0x73 # CHECK: dclz $16, $25
0x1e 0x00 0x53 0x03 # CHECK: ddiv $zero, $26, $19
0x1f 0x00 0x11 0x02 # CHECK: ddivu $zero, $16, $17
[mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0. Summary: Previously it (incorrectly) used GPR's. Patch by Simon Dardis. A couple small corrections by myself. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10567 llvm-svn: 240883
2015-06-27 23:39:19 +08:00
0x00 0x50 0x38 0x40 # CHECK: dmfc0 $24, $10, 0
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
0x00 0x68 0x2c 0x44 # CHECK: dmfc1 $12, $f13
[mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0. Summary: Previously it (incorrectly) used GPR's. Patch by Simon Dardis. A couple small corrections by myself. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10567 llvm-svn: 240883
2015-06-27 23:39:19 +08:00
0x00 0x50 0xa4 0x40 # CHECK: dmtc0 $4, $10, 0
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14
0x1c 0x00 0xe9 0x02 # CHECK: dmult $23, $9
0x1d 0x00 0xa6 0x00 # CHECK: dmultu $5, $6
0xb8 0x04 0x00 0x00 # CHECK: dsll $zero, $zero, 18
0xb8 0x04 0x14 0x00 # CHECK: dsll $zero, $20, 18
0x14 0x00 0x94 0x01 # CHECK: dsllv $zero, $20, $12
0xbc 0x04 0x00 0x00 # CHECK: dsll32 $zero, $zero, 18
0xbc 0x04 0x00 0x00 # CHECK: dsll32 $zero, $zero, 18
0x14 0x00 0x94 0x01 # CHECK: dsllv $zero, $20, $12
0xbb 0xe2 0x1c 0x00 # CHECK: dsra $gp, $gp, 10
0xbb 0xe2 0x12 0x00 # CHECK: dsra $gp, $18, 10
0x17 0xe0 0x72 0x02 # CHECK: dsrav $gp, $18, $19
0xbf 0xe2 0x1c 0x00 # CHECK: dsra32 $gp, $gp, 10
0xbf 0xe2 0x12 0x00 # CHECK: dsra32 $gp, $18, 10
0x17 0xe0 0x72 0x02 # CHECK: dsrav $gp, $18, $19
0xfa 0x9d 0x13 0x00 # CHECK: dsrl $19, $19, 23
0xfa 0x9d 0x06 0x00 # CHECK: dsrl $19, $6, 23
0x16 0x98 0x86 0x02 # CHECK: dsrlv $19, $6, $20
0xfe 0x9d 0x13 0x00 # CHECK: dsrl32 $19, $19, 23
0xfe 0x9d 0x06 0x00 # CHECK: dsrl32 $19, $6, 23
0x16 0x98 0x86 0x02 # CHECK: dsrlv $19, $6, $20
0x2e 0x38 0xc8 0x02 # CHECK: dsub $7, $22, $8
0xa4 0x18 0x0e 0x7c # CHECK: dsbh $3, $14
0x64 0x11 0x1d 0x7c # CHECK: dshd $2, $sp
0x39 0x6c 0x9d 0x62 # CHECK: daddi $sp, $20, 27705
0x39 0x6c 0xbd 0x63 # CHECK: daddi $sp, $sp, 27705
0x2f 0x28 0xba 0x00 # CHECK: dsubu $5, $5, $26
0x5f 0xec 0x6f 0x65 # CHECK: daddiu $15, $11, -5025
0xea 0x11 0xce 0x65 # CHECK: daddiu $14, $14, 4586
0x00 0x60 0x7e 0x41 # CHECK: di $fp
0x00 0x60 0x60 0x41 # CHECK: di
0xfa 0x0b 0x21 0x00 # CHECK: drotr $1, $1, 15
0xfa 0x0b 0x2e 0x00 # CHECK: drotr $1, $14, 15
0xfe 0x0b 0x21 0x00 # CHECK: drotr32 $1, $1, 15
0xfe 0x0b 0x2e 0x00 # CHECK: drotr32 $1, $14, 15
0x56 0x08 0xee 0x01 # CHECK: drotrv $1, $14, $15
0x20 0x60 0x6e 0x41 # CHECK: ei $14
0x20 0x60 0x60 0x41 # CHECK: ei
0x8b 0x3e 0x20 0x46 # CHECK: floor.l.d $f26, $f7
0x0b 0x2b 0x00 0x46 # CHECK: floor.l.s $f12, $f5
0x0f 0x73 0x20 0x46 # CHECK: floor.w.d $f12, $f14
0x8f 0x39 0x00 0x46 # CHECK: floor.w.s $f6, $f7
0x84 0x61 0x33 0x7d # CHECK: ins $19, $9, 6, 7
0x4c 0x01 0x00 0x08 # CHECK: j 1328
0x4c 0x01 0x00 0x0c # CHECK: jal 1328
0x4c 0x01 0x00 0x74 # CHECK: jalx 1328
0x09 0xf8 0xe0 0x00 # CHECK: jalr $7
0x09 0xfc 0x80 0x00 # CHECK: jalr.hb $4
0x09 0x24 0xa0 0x00 # CHECK: jalr.hb $4, $5
0x08 0x00 0xe0 0x00 # CHECK: jr $7
0xc6 0x23 0xa4 0x80 # CHECK: lb $4, 9158($5)
0x06 0x00 0xa4 0x90 # CHECK: lbu $4, 6($5)
0x1b 0x90 0x3d 0xde # CHECK: ld $sp, -28645($17)
0xb9 0xef 0x18 0x6b # CHECK: ldl $24, -4167($24)
0x6a 0x89 0x8e 0x6e # CHECK: ldr $14, -30358($20)
0xc6 0x23 0xe9 0xd4 # CHECK: ldc1 $f9, 9158($7)
0x01 0x02 0xf7 0x4d # CHECK: ldxc1 $f8, $23($15)
0x0c 0x00 0xa4 0x84 # CHECK: lh $4, 12($5)
0x0c 0x00 0xa4 0x84 # CHECK: lh $4, 12($5)
0xc6 0x23 0xe9 0xc0 # CHECK: ll $9, 9158($7)
0x70 0xc6 0xe0 0xd3 # CHECK: lld $zero, -14736($ra)
0x67 0x45 0x06 0x3c # CHECK: lui $6, 17767
0x05 0x00 0xa6 0x4c # CHECK: luxc1 $f0, $6($5)
0x18 0x00 0xa4 0x8c # CHECK: lw $4, 24($5)
0xc6 0x23 0xe9 0xc4 # CHECK: lwc1 $f9, 9158($7)
0x03 0x00 0x82 0x88 # CHECK: lwl $2, 3($4)
0x10 0x00 0xa3 0x98 # CHECK: lwr $3, 16($5)
0x00 0x05 0xcc 0x4d # CHECK: lwxc1 $f20, $12($14)
0xea 0xa1 0x73 0x9c # CHECK: lwu $19, -24086($3)
0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7
0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25
0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
[mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0. Summary: Previously it (incorrectly) used GPR's. Patch by Simon Dardis. A couple small corrections by myself. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10567 llvm-svn: 240883
2015-06-27 23:39:19 +08:00
0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
0x10 0x28 0x00 0x00 # CHECK: mfhi $5
0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
0x12 0x28 0x00 0x00 # CHECK: mflo $5
[mips] Remap move as or. Summary: This patch remaps the assembly idiom 'move' to 'or' instead of 'daddu' or 'addu'. The use of addu/daddu instead of or as move was highlighted as a performance issue during the analysis of a recent 64bit design. Originally move was encoded as 'or' by binutils but was changed for the r10k cpu family due to their pipeline which had 2 arithmetic units and a single logical unit, and so could issue multiple (d)addu based moves at the same time but only 1 logical move. This patch preserves the disassembly behaviour so that disassembling a old style (d)addu move still appears as move, but assembling move always gives an or Patch by Simon Dardis. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11796 llvm-svn: 244579
2015-08-11 16:56:25 +08:00
0x25 0x78 0xe0 0x03 # CEHCK: move $15, $ra
0x2d 0x78 0xe0 0x03 # CEHCK: move $15, $ra
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16
0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
[mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0. Summary: Previously it (incorrectly) used GPR's. Patch by Simon Dardis. A couple small corrections by myself. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10567 llvm-svn: 240883
2015-06-27 23:39:19 +08:00
0x01 0x78 0x89 0x40 # CHECK: mtc0 $9, $15, 1
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
0x11 0x00 0xe0 0x00 # CHECK: mthi $7
0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16
0x13 0x00 0xe0 0x00 # CHECK: mtlo $7
0x02 0x62 0x2e 0x46 # CHECK: mul.d $f8, $f12, $f14
0x42 0x32 0x07 0x46 # CHECK: mul.s $f9, $f6, $f7
0x02 0x48 0xc7 0x70 # CHECK: mul $9, $6, $7
0x18 0x00 0x65 0x00 # CHECK: mult $3, $5
0x19 0x00 0x65 0x00 # CHECK: multu $3, $5
0x07 0x73 0x20 0x46 # CHECK: neg.d $f12, $f14
0x87 0x39 0x00 0x46 # CHECK: neg.s $f6, $f7
0x30 0xc8 0xac 0x4c # CHECK: nmadd.s $f0, $f5, $f25, $f12
0x00 0x00 0x00 0x00 # CHECK: nop
0x27 0x48 0xc7 0x00 # CHECK: nor $9, $6, $7
0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4
0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5
0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
Recommit: "[mips] Add rsqrt, recip for MIPS" Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 283334
2016-10-06 00:11:01 +08:00
0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1
0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5
0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
Recommit: "[mips] Add rsqrt, recip for MIPS" Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 283334
2016-10-06 00:11:01 +08:00
0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
0xcd 0xdf 0xaf 0xf3 # CHECK: scd $15, -8243($sp)
0xcb 0x16 0x4c 0xfd # CHECK: sd $12, 5835($10)
0xc6 0x23 0xe9 0xf4 # CHECK: sdc1 $f9, 9158($7)
0x1f 0xae 0xc7 0xb3 # CHECK: sdl $7, -20961($fp)
0x39 0xb0 0x8b 0xb5 # CHECK: sdr $11, -20423($12)
0x09 0x40 0x24 0x4f # CHECK: sdxc1 $f8, $4($25)
0x20 0x34 0x07 0x7c # CHECK: seb $6, $7
0x20 0x36 0x07 0x7c # CHECK: seh $6, $7
0xc6 0x23 0xa4 0xa4 # CHECK: sh $4, 9158($5)
0xc0 0x21 0x03 0x00 # CHECK: sll $4, $3, 7
0x04 0x10 0xa3 0x00 # CHECK: sllv $2, $3, $5
0x2a 0x18 0x65 0x00 # CHECK: slt $3, $3, $5
0x67 0x00 0x63 0x28 # CHECK: slti $3, $3, 103
0x67 0x00 0x63 0x2c # CHECK: sltiu $3, $3, 103
0x2b 0x18 0x65 0x00 # CHECK: sltu $3, $3, $5
0x04 0x73 0x20 0x46 # CHECK: sqrt.d $f12, $f14
0x84 0x39 0x00 0x46 # CHECK: sqrt.s $f6, $f7
0xc3 0x21 0x03 0x00 # CHECK: sra $4, $3, 7
0x07 0x10 0xa3 0x00 # CHECK: srav $2, $3, $5
0xc2 0x21 0x03 0x00 # CHECK: srl $4, $3, 7
0x06 0x10 0xa3 0x00 # CHECK: srlv $2, $3, $5
0x01 0x62 0x2e 0x46 # CHECK: sub.d $f8, $f12, $f14
0x41 0x32 0x07 0x46 # CHECK: sub.s $f9, $f6, $f7
0x22 0x48 0xc7 0x00 # CHECK: sub $9, $6, $7
0x23 0x20 0x65 0x00 # CHECK: subu $4, $3, $5
0x0d 0x20 0xb8 0x4c # CHECK: suxc1 $f4, $24($5)
0x18 0x00 0xa4 0xac # CHECK: sw $4, 24($5)
0xc6 0x23 0xe9 0xe4 # CHECK: swc1 $f9, 9158($7)
0x10 0x00 0xa4 0xa8 # CHECK: swl $4, 16($5)
0x10 0x00 0xe6 0xb8 # CHECK: swr $6, 16($7)
0x08 0xd0 0xd2 0x4e # CHECK: swxc1 $f26, $18($22)
0xcf 0x01 0x00 0x00 # CHECK: sync 7
0xc9 0xbd 0x20 0x46 # CHECK: trunc.l.d $f23, $f23
0x09 0xff 0x00 0x46 # CHECK: trunc.l.s $f28, $f31
0x0d 0x73 0x20 0x46 # CHECK: trunc.w.d $f12, $f14
0x8d 0x39 0x00 0x46 # CHECK: trunc.w.s $f6, $f7
0xa0 0x30 0x07 0x7c # CHECK: wsbh $6, $7
0x26 0x18 0x65 0x00 # CHECK: xor $3, $3, $5
0x67 0x45 0xc9 0x38 # CHECK: xori $9, $6, 17767