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llvm-project/llvm/lib/Target/PowerPC/PPCScheduleE500.td

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Add PowerPC e500(v2) core scheduler and directives. Differential Revision: https://reviews.llvm.org/D44828 llvm-svn: 337345
2018-07-18 12:24:49 +08:00
//===-- PPCScheduleE500.td - e500 Scheduling Defs ------*- tablegen -*-===//
//
Update the file headers across all of the LLVM projects in the monorepo to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
2019-01-19 16:50:56 +08:00
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Add PowerPC e500(v2) core scheduler and directives. Differential Revision: https://reviews.llvm.org/D44828 llvm-svn: 337345
2018-07-18 12:24:49 +08:00
//
//===----------------------------------------------------------------------===//
//
// This file defines the itinerary class data for the Freescale e500 32-bit
// Power processor.
//
// All information is derived from the "e500 Core Reference Manual",
// Freescale Document Number E500MCRM, Rev. 1, 03/2012.
//
//===----------------------------------------------------------------------===//
// Relevant functional units in the Freescale e500 core:
//
// * Decode & Dispatch
// Can dispatch up to 2 instructions per clock cycle to either the GPR Issue
// queues (GIQx) or Branch issue queue (BIQ).
def E500_DIS0 : FuncUnit; // Dispatch stage - insn 1
def E500_DIS1 : FuncUnit; // Dispatch stage - insn 2
// * Execute
// 6 pipelined execution units: SU0, SU1, BU, LSU, MU.
// Some instructions can only execute in SU0 but not SU1.
def E500_SU0 : FuncUnit; // Simple unit 0
def E500_SU1 : FuncUnit; // Simple unit 1
def E500_BU : FuncUnit; // Branch unit
def E500_MU : FuncUnit; // MU pipeline
def E500_LSU_0 : FuncUnit; // LSU pipeline
def E500_GPR_Bypass : Bypass;
def E500_CR_Bypass : Bypass;
def E500_DivBypass : Bypass;
def PPCE500Itineraries : ProcessorItineraries<
[E500_DIS0, E500_DIS1, E500_SU0, E500_SU1, E500_BU,
E500_MU, E500_LSU_0],
[E500_CR_Bypass, E500_GPR_Bypass, E500_DivBypass], [
InstrItinData<IIC_IntSimple, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SU0, E500_SU1]>],
[4, 1, 1], // Latency = 1
[E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_IntGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SU0, E500_SU1]>],
[4, 1, 1], // Latency = 1
[E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_IntISEL, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SU0, E500_SU1]>],
[4, 1, 1, 1], // Latency = 1
[E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass,
E500_CR_Bypass]>,
InstrItinData<IIC_IntCompare, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SU0, E500_SU1]>],
[5, 1, 1], // Latency = 1 or 2
[E500_CR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_IntDivW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_MU], 0>,
InstrStage<14, [E500_MU]>],
[17, 1, 1], // Latency=4..35, Repeat= 4..35
[E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_IntMulHW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<4, [E500_MU]>],
[7, 1, 1], // Latency = 4, Repeat rate = 1
[E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_IntMulHWU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<4, [E500_MU]>],
[7, 1, 1], // Latency = 4, Repeat rate = 1
[E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_IntMulLI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<4, [E500_MU]>],
[7, 1, 1], // Latency = 4, Repeat rate = 1
[E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_IntRotate, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SU0, E500_SU1]>],
[4, 1, 1], // Latency = 1
[E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_IntShift, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SU0, E500_SU1]>],
[4, 1, 1], // Latency = 1
[E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_IntTrapW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<2, [E500_SU0]>],
[5, 1], // Latency = 2, Repeat rate = 2
[E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_BrB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_BU]>],
[4, 1], // Latency = 1
[NoBypass, E500_GPR_Bypass]>,
InstrItinData<IIC_BrCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_BU]>],
[4, 1, 1], // Latency = 1
[E500_CR_Bypass,
E500_CR_Bypass, E500_CR_Bypass]>,
InstrItinData<IIC_BrMCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_BU]>],
[4, 1], // Latency = 1
[E500_CR_Bypass, E500_CR_Bypass]>,
InstrItinData<IIC_BrMCRX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SU0, E500_SU1]>],
[4, 1, 1], // Latency = 1
[E500_CR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStDCBA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3, Repeat rate = 1
[E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStDCBF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStDCBI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStLoad, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SU0, E500_SU1], 0>,
InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass],
2>, // 2 micro-ops
InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SU0, E500_SU1], 0>,
InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass],
2>, // 2 micro-ops
InstrItinData<IIC_LdStStore, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3
[NoBypass, E500_GPR_Bypass]>,
[PowerPC] Add Itineraries for STWU/STWUX etc When doing some instruction scheduling work, we noticed some missing itineraries. Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, because we can still get same latency due to default values. With machine scheduler, however, itineraries will have impact to scheduling. eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class. And most of the instruction class with itineraries will have NumMicroOps default to 1. This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, then causing different scheduling or suboptimal scheduling further. This patch is for STWU/STWUX (IIC_LdStStoreUpd ) for P8. Since there are already multiple IIC for store update, this patch also merge IIC_LdStSTDU/IIC_LdStStoreUpd to IIC_LdStSTU IIC_LdStSTDUX to IIC_LdStSTUX and we add a new testcase in https://reviews.llvm.org/D54699 to show the difference. Differential Revision: https://reviews.llvm.org/D54700 llvm-svn: 347311
2018-11-20 23:11:42 +08:00
InstrItinData<IIC_LdStSTU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SU0, E500_SU1], 0>,
InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3
[NoBypass, E500_GPR_Bypass],
2>, // 2 micro-ops
InstrItinData<IIC_LdStSTUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
Add PowerPC e500(v2) core scheduler and directives. Differential Revision: https://reviews.llvm.org/D44828 llvm-svn: 337345
2018-07-18 12:24:49 +08:00
InstrStage<1, [E500_SU0, E500_SU1], 0>,
InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3
[NoBypass, E500_GPR_Bypass],
2>, // 2 micro-ops
InstrItinData<IIC_LdStICBI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3
[NoBypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStLHA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStLHAU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SU0, E500_SU1], 0>,
InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SU0, E500_SU1], 0>,
InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStLMW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>],
[7, 1], // Latency = r+3
[NoBypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStLWARX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<3, [E500_LSU_0]>],
[6, 1, 1], // Latency = 3, Repeat rate = 3
[E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3
[NoBypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStSync, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>]>,
InstrItinData<IIC_SprMFSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<4, [E500_SU0]>],
[7, 1],
[E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_SprMTMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<2, [E500_SU0, E500_SU1]>],
[5, 1], // Latency = 2, Repeat rate = 4
[E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_SprMTSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SU0]>],
[5, 1],
[NoBypass, E500_GPR_Bypass]>,
InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0], 0>]>,
InstrItinData<IIC_SprMFCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<5, [E500_SU0]>],
[8, 1],
[E500_GPR_Bypass, E500_CR_Bypass]>,
InstrItinData<IIC_SprMFCRF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<5, [E500_SU0]>],
[8, 1],
[E500_GPR_Bypass, E500_CR_Bypass]>,
InstrItinData<IIC_SprMFPMR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<4, [E500_SU0]>],
[7, 1], // Latency = 4, Repeat rate = 4
[E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<4, [E500_SU0]>],
[7, 1], // Latency = 4, Repeat rate = 4
[E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_SprMFSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SU0, E500_SU1]>],
[4, 1], // Latency = 1, Repeat rate = 1
[E500_GPR_Bypass, E500_CR_Bypass]>,
InstrItinData<IIC_SprMTPMR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SU0]>],
[4, 1], // Latency = 1, Repeat rate = 1
[E500_CR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_SprMFTB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<4, [E500_SU0]>],
[7, 1], // Latency = 4, Repeat rate = 4
[NoBypass, E500_GPR_Bypass]>,
InstrItinData<IIC_SprMTSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SU0, E500_SU1]>],
[4, 1], // Latency = 1, Repeat rate = 1
[E500_CR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SU0]>],
[4, 1],
[NoBypass, E500_GPR_Bypass]>,
Complete the SPE instruction set patterns This is the lead-up to having SPE codegen. Add the rest of the instructions, along with MC tests. Differential Revision: https://reviews.llvm.org/D44829 llvm-svn: 337346
2018-07-18 12:24:57 +08:00
InstrItinData<IIC_FPDGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<6, [E500_MU]>],
[9, 1, 1], // Latency = 6, Repeat rate = 1
[NoBypass]>,
InstrItinData<IIC_FPSGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<4, [E500_MU]>],
[7, 1, 1], // Latency = 4, Repeat rate = 1
[NoBypass]>,
Add PowerPC e500(v2) core scheduler and directives. Differential Revision: https://reviews.llvm.org/D44828 llvm-svn: 337345
2018-07-18 12:24:49 +08:00
InstrItinData<IIC_FPDivD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<32, [E500_MU]>],
[35, 1, 1], // Latency = 32, Repeat rate = 32
[E500_DivBypass]>,
InstrItinData<IIC_FPDivS, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<29, [E500_MU]>],
[32, 1, 1], // Latency = 29, Repeat rate = 29
[E500_DivBypass]>,
InstrItinData<IIC_VecGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SU0]>],
[4, 1, 1], // Latency = 1, Repeat rate = 1
[NoBypass]>,
InstrItinData<IIC_VecComplex, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<4, [E500_MU]>],
[7, 1, 1], // Latency = 4, Repeat rate = 1
[NoBypass]>
]>;
// ===---------------------------------------------------------------------===//
// e500 machine model for scheduling and other instruction cost heuristics.
def PPCE500Model : SchedMachineModel {
let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
let LoadLatency = 5; // Optimistic load latency assuming bypass.
// This is overriden by OperandCycles if the
// Itineraries are queried instead.
let CompleteModel = 0;
let Itineraries = PPCE500Itineraries;
}