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[mips] Add calling convention tests covering O32, N32, and N64. Summary: I had difficulty finding tests for the N32 and N64 ABI so I've added a collection of calling convention tests based on the document MIPS ABIs Described (MD00305), the MIPSpro N32 Handbook, and the SYSV ABI. Where the documents/implementations disagree, I've used GCC to resolve the conflict. A few interesting details: * For N32, LLVM uses 64-bit pointers when saving $ra despite pointers being 32-bit. I've yet to find a supporting statement in the ABI documentation but the current behaviour matches GCC. * For O32, the non-variable portion of a varargs argument list is also subject to the rule that floating-point is passed via GPR's (on N32/N64 only the variable portion is subject to this rule). This agrees with GCC's behaviour and the SYSV ABI but contradicts part of the MIPSpro N32 Handbook which talks about O32's behaviour. * The N32 implementation has the wrong callee-saved register list. (I already have a fix for this but will commit it as a follow-up). I've left RUN-TODO lines in for O32 on MIPS64. I don't plan to support this case for now but we should revisit it. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3339 llvm-svn: 206370
2014-04-16 17:59:46 +08:00
; RUN: llc -march=mips -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 --check-prefix=O32BE %s
; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 --check-prefix=O32LE %s
; RUN-TODO: llc -march=mips64 -relocation-model=static -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s
; RUN-TODO: llc -march=mips64el -relocation-model=static -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s
; RUN: llc -march=mips64 -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=N32 --check-prefix=NEW %s
; RUN: llc -march=mips64el -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=N32 --check-prefix=NEW %s
; RUN: llc -march=mips64 -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=N64 --check-prefix=NEW %s
; RUN: llc -march=mips64el -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=N64 --check-prefix=NEW %s
; Test the effect of varargs on floating point types in the non-variable part
; of the argument list as specified by section 2 of the MIPSpro N32 Handbook.
;
; N32/N64 are almost identical in this area so many of their checks have been
; combined into the 'NEW' prefix (the N stands for New).
;
; On O32, varargs prevents all FPU argument register usage. This contradicts
; the N32 handbook, but agrees with the SYSV ABI and GCC's behaviour.
@floats = global [11 x float] zeroinitializer
@doubles = global [11 x double] zeroinitializer
define void @double_args(double %a, ...)
nounwind {
entry:
%0 = getelementptr [11 x double]* @doubles, i32 0, i32 1
store volatile double %a, double* %0
%ap = alloca i8*
%ap2 = bitcast i8** %ap to i8*
call void @llvm.va_start(i8* %ap2)
%b = va_arg i8** %ap, double
%1 = getelementptr [11 x double]* @doubles, i32 0, i32 2
store volatile double %b, double* %1
ret void
}
; ALL-LABEL: double_args:
; We won't test the way the global address is calculated in this test. This is
; just to get the register number for the other checks.
; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles)
; SYM64-DAG: ld [[R2:\$[0-9]]], %got_disp(doubles)(
; O32 forbids using floating point registers for the non-variable portion.
; N32/N64 allow it.
; O32BE-DAG: mtc1 $5, [[FTMP1:\$f[0-9]*[02468]+]]
; O32BE-DAG: mtc1 $4, [[FTMP2:\$f[0-9]*[13579]+]]
; O32LE-DAG: mtc1 $4, [[FTMP1:\$f[0-9]*[02468]+]]
; O32LE-DAG: mtc1 $5, [[FTMP2:\$f[0-9]*[13579]+]]
; O32-DAG: sdc1 [[FTMP1]], 8([[R2]])
; NEW-DAG: sdc1 $f12, 8([[R2]])
; The varargs portion is dumped to stack
; O32-DAG: sw $6, 16($sp)
; O32-DAG: sw $7, 20($sp)
; NEW-DAG: sd $5, 8($sp)
; NEW-DAG: sd $6, 16($sp)
; NEW-DAG: sd $7, 24($sp)
; NEW-DAG: sd $8, 32($sp)
; NEW-DAG: sd $9, 40($sp)
; NEW-DAG: sd $10, 48($sp)
; NEW-DAG: sd $11, 56($sp)
; Get the varargs pointer
; O32 has 4 bytes padding, 4 bytes for the varargs pointer, and 8 bytes reserved
; for arguments 1 and 2.
; N32/N64 has 8 bytes for the varargs pointer, and no reserved area.
; O32-DAG: addiu [[VAPTR:\$[0-9]+]], $sp, 16
; O32-DAG: sw [[VAPTR]], 4($sp)
; N32-DAG: addiu [[VAPTR:\$[0-9]+]], $sp, 8
; N32-DAG: sw [[VAPTR]], 4($sp)
; N64-DAG: daddiu [[VAPTR:\$[0-9]+]], $sp, 8
; N64-DAG: sd [[VAPTR]], 0($sp)
; Increment the pointer then get the varargs arg
; LLVM will rebind the load to the stack pointer instead of the varargs pointer
; during lowering. This is fine and doesn't change the behaviour.
; O32-DAG: addiu [[VAPTR]], [[VAPTR]], 8
; O32-DAG: sw [[VAPTR]], 4($sp)
; N32-DAG: addiu [[VAPTR]], [[VAPTR]], 8
; N32-DAG: sw [[VAPTR]], 4($sp)
; N64-DAG: daddiu [[VAPTR]], [[VAPTR]], 8
; N64-DAG: sd [[VAPTR]], 0($sp)
; O32-DAG: ldc1 [[FTMP1:\$f[0-9]+]], 16($sp)
; NEW-DAG: ldc1 [[FTMP1:\$f[0-9]+]], 8($sp)
; ALL-DAG: sdc1 [[FTMP1]], 16([[R2]])
define void @float_args(float %a, ...) nounwind {
entry:
%0 = getelementptr [11 x float]* @floats, i32 0, i32 1
store volatile float %a, float* %0
%ap = alloca i8*
%ap2 = bitcast i8** %ap to i8*
call void @llvm.va_start(i8* %ap2)
%b = va_arg i8** %ap, float
%1 = getelementptr [11 x float]* @floats, i32 0, i32 2
store volatile float %b, float* %1
ret void
}
; ALL-LABEL: float_args:
; We won't test the way the global address is calculated in this test. This is
; just to get the register number for the other checks.
; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(floats)
; SYM64-DAG: ld [[R2:\$[0-9]]], %got_disp(floats)(
; The first four arguments are the same in O32/N32/N64.
; The non-variable portion should be unaffected.
; O32-DAG: sw $4, 4([[R2]])
; NEW-DAG: swc1 $f12, 4([[R2]])
; The varargs portion is dumped to stack
; O32-DAG: sw $5, 12($sp)
; O32-DAG: sw $6, 16($sp)
; O32-DAG: sw $7, 20($sp)
; NEW-DAG: sd $5, 8($sp)
; NEW-DAG: sd $6, 16($sp)
; NEW-DAG: sd $7, 24($sp)
; NEW-DAG: sd $8, 32($sp)
; NEW-DAG: sd $9, 40($sp)
; NEW-DAG: sd $10, 48($sp)
; NEW-DAG: sd $11, 56($sp)
; Get the varargs pointer
; O32 has 4 bytes padding, 4 bytes for the varargs pointer, and should have 8
; bytes reserved for arguments 1 and 2 (the first float arg) but as discussed in
; arguments-float.ll, GCC doesn't agree with MD00305 and treats floats as 4
; bytes so we only have 12 bytes total.
; N32/N64 has 8 bytes for the varargs pointer, and no reserved area.
; O32-DAG: addiu [[VAPTR:\$[0-9]+]], $sp, 12
; O32-DAG: sw [[VAPTR]], 4($sp)
; N32-DAG: addiu [[VAPTR:\$[0-9]+]], $sp, 8
; N32-DAG: sw [[VAPTR]], 4($sp)
; N64-DAG: daddiu [[VAPTR:\$[0-9]+]], $sp, 8
; N64-DAG: sd [[VAPTR]], 0($sp)
; Increment the pointer then get the varargs arg
; LLVM will rebind the load to the stack pointer instead of the varargs pointer
; during lowering. This is fine and doesn't change the behaviour.
; N32/N64 is using ori instead of addiu/daddiu but (although odd) this is fine
; since the stack is always aligned.
; O32-DAG: addiu [[VAPTR]], [[VAPTR]], 4
; O32-DAG: sw [[VAPTR]], 4($sp)
; N32-DAG: ori [[VAPTR]], [[VAPTR]], 4
; N32-DAG: sw [[VAPTR]], 4($sp)
; N64-DAG: ori [[VAPTR]], [[VAPTR]], 4
; N64-DAG: sd [[VAPTR]], 0($sp)
; O32-DAG: lwc1 [[FTMP1:\$f[0-9]+]], 12($sp)
; NEW-DAG: lwc1 [[FTMP1:\$f[0-9]+]], 8($sp)
; ALL-DAG: swc1 [[FTMP1]], 8([[R2]])
declare void @llvm.va_start(i8*)
declare void @llvm.va_copy(i8*, i8*)
declare void @llvm.va_end(i8*)