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llvm-project/llvm/lib/Target/RISCV/CMakeLists.txt

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[RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td For now, only add instruction definitions for basic ALU operations. Our initial target is a working MC layer rather than codegen, so appropriate SelectionDAG patterns will come later. Differential Revision: https://reviews.llvm.org/D23561 llvm-svn: 285769
2016-11-02 07:40:28 +08:00
set(LLVM_TARGET_DEFINITIONS RISCV.td)
tablegen(LLVM RISCVGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
[RISCV] Add bare-bones RISC-V MCTargetDesc This is enough to compile and link but doesn't yet do anything particularly useful. Once an ASM parser and printer are added in the next two patches, the whole thing can be usefully tested. Differential Revision: https://reviews.llvm.org/D23562 llvm-svn: 285770
2016-11-02 07:47:30 +08:00
tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
[RISCV] Add basic RISCVAsmParser This doesn't yet support parsing things like %pcrel_hi(foo), but will handle basic instructions with register or immediate operands. Differential Revision: https://reviews.llvm.org/D23563 llvm-svn: 310361
2017-08-08 22:32:35 +08:00
tablegen(LLVM RISCVGenAsmMatcher.inc -gen-asm-matcher)
[RISCV] Add RISCVInstPrinter and basic MC assembler tests With the addition of RISCVInstPrinter, it is now possible to test the basic operation of the RISCV MC layer. Differential Revision: https://reviews.llvm.org/D23564 llvm-svn: 310917
2017-08-15 21:08:29 +08:00
tablegen(LLVM RISCVGenAsmWriter.inc -gen-asm-writer)
[RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td For now, only add instruction definitions for basic ALU operations. Our initial target is a working MC layer rather than codegen, so appropriate SelectionDAG patterns will come later. Differential Revision: https://reviews.llvm.org/D23561 llvm-svn: 285769
2016-11-02 07:40:28 +08:00
add_public_tablegen_target(RISCVCommonTableGen)
[RISCV] Add stub backend This contains just enough for lib/Target/RISCV to compile. Notably a basic RISCVTargetMachine and RISCVTargetInfo. At this point you can attempt llc -march=riscv32 myinput.ll and will find it fails due to the lack of MCAsmInfo. See http://lists.llvm.org/pipermail/llvm-dev/2016-August/103748.html for further discussion Differential Revision: https://reviews.llvm.org/D23560 llvm-svn: 285712
2016-11-02 01:27:54 +08:00
add_llvm_target(RISCVCodeGen
RISCVTargetMachine.cpp
)
[RISCV] Add basic RISCVAsmParser This doesn't yet support parsing things like %pcrel_hi(foo), but will handle basic instructions with register or immediate operands. Differential Revision: https://reviews.llvm.org/D23563 llvm-svn: 310361
2017-08-08 22:32:35 +08:00
add_subdirectory(AsmParser)
[RISCV] Add RISCVInstPrinter and basic MC assembler tests With the addition of RISCVInstPrinter, it is now possible to test the basic operation of the RISCV MC layer. Differential Revision: https://reviews.llvm.org/D23564 llvm-svn: 310917
2017-08-15 21:08:29 +08:00
add_subdirectory(InstPrinter)
[RISCV] Add bare-bones RISC-V MCTargetDesc This is enough to compile and link but doesn't yet do anything particularly useful. Once an ASM parser and printer are added in the next two patches, the whole thing can be usefully tested. Differential Revision: https://reviews.llvm.org/D23562 llvm-svn: 285770
2016-11-02 07:47:30 +08:00
add_subdirectory(MCTargetDesc)
[RISCV] Add RISCVInstPrinter and basic MC assembler tests With the addition of RISCVInstPrinter, it is now possible to test the basic operation of the RISCV MC layer. Differential Revision: https://reviews.llvm.org/D23564 llvm-svn: 310917
2017-08-15 21:08:29 +08:00
add_subdirectory(TargetInfo)