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llvm-project/llvm/test/CodeGen/R600/rotr.ll

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R600/SI: Use -verify-machineinstrs for most tests We can't enable the verifier for tests with SI_IF and SI_ELSE, because these instructions are always followed by a COPY which copies their result to the next basic block. This violates the machine verifier's rule that non-terminators can not folow terminators. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 192366
2013-10-11 01:11:46 +08:00
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s
; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
R600: Swap the legality of rotl and rotr The hardware supports rotr and not rotl. llvm-svn: 182285
2013-05-20 23:02:19 +08:00
R600/SI: Add pattern for rotr Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 182286
2013-05-20 23:02:24 +08:00
; R600-CHECK: @rotr
; R600-CHECK: BIT_ALIGN_INT
; SI-CHECK: @rotr
; SI-CHECK: V_ALIGNBIT_B32
R600: Swap the legality of rotl and rotr The hardware supports rotr and not rotl. llvm-svn: 182285
2013-05-20 23:02:19 +08:00
define void @rotr(i32 addrspace(1)* %in, i32 %x, i32 %y) {
entry:
%0 = sub i32 32, %y
%1 = shl i32 %x, %0
%2 = lshr i32 %x, %y
%3 = or i32 %1, %2
store i32 %3, i32 addrspace(1)* %in
ret void
}
R600/SI: Add pattern for rotr Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 182286
2013-05-20 23:02:24 +08:00
; R600-CHECK: @rotl
; R600-CHECK: SUB_INT {{\** T[0-9]+\.[XYZW]}}, literal.x
; R600-CHECK-NEXT: 32
R600: Non vector only instruction can be scheduled on trans unit llvm-svn: 189980
2013-09-05 03:53:46 +08:00
; R600-CHECK: BIT_ALIGN_INT {{T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].Z, PV.{{[XYZW]}}
R600/SI: Add pattern for rotr Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 182286
2013-05-20 23:02:24 +08:00
; SI-CHECK: @rotl
R600/SI: Change formatting of printed registers. Print the range of registers used with a single letter prefix. This better matches what the shader compiler produces and is overall less obnoxious than concatenating all of the subregister names together. Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1, it will print s[0:1] and so on. There doesn't appear to be a straightforward way to get the actual register info in the InstPrinter, so this parses the generated name to print with the new syntax. The required test changes are pretty nasty, and register matching regexes are now worse. Since there isn't a way to add to a variable in FileCheck, some of the tests now don't check the exact number of registers used, but I don't think that will be a real problem. llvm-svn: 194443
2013-11-12 10:35:51 +08:00
; SI-CHECK: V_SUB_I32_e64 [[DST:v[0-9]+]], 32, {{[sv][0-9]+}}
; SI-CHECK: V_ALIGNBIT_B32 {{v[0-9]+, [sv][0-9]+, v[0-9]+}}, [[DST]]
R600: Swap the legality of rotl and rotr The hardware supports rotr and not rotl. llvm-svn: 182285
2013-05-20 23:02:19 +08:00
define void @rotl(i32 addrspace(1)* %in, i32 %x, i32 %y) {
entry:
%0 = shl i32 %x, %y
%1 = sub i32 32, %y
%2 = lshr i32 %x, %1
%3 = or i32 %0, %2
store i32 %3, i32 addrspace(1)* %in
ret void
}