2018-05-22 05:40:51 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+sse,-sse2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SSE,CHECK-SSE1
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; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+sse,+sse2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SSE,CHECK-SSE2
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; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+xop < %s | FileCheck %s --check-prefixes=CHECK,CHECK-XOP
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; ============================================================================ ;
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; Various cases with %x and/or %y being a constant
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; ============================================================================ ;
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define <4 x i32> @out_constant_varx_mone(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
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; CHECK-SSE1-LABEL: out_constant_varx_mone:
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; CHECK-SSE1: # %bb.0:
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2018-09-20 02:59:08 +08:00
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; CHECK-SSE1-NEXT: movq %rdi, %rax
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2018-05-22 05:40:51 +08:00
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; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
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2018-10-02 17:08:51 +08:00
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; CHECK-SSE1-NEXT: movaps {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
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2018-05-22 05:40:51 +08:00
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; CHECK-SSE1-NEXT: xorps %xmm0, %xmm1
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; CHECK-SSE1-NEXT: andps (%rsi), %xmm0
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; CHECK-SSE1-NEXT: orps %xmm1, %xmm0
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; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
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; CHECK-SSE1-NEXT: retq
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;
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; CHECK-SSE2-LABEL: out_constant_varx_mone:
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; CHECK-SSE2: # %bb.0:
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; CHECK-SSE2-NEXT: movdqa (%rdx), %xmm0
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; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm1
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; CHECK-SSE2-NEXT: pxor %xmm0, %xmm1
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; CHECK-SSE2-NEXT: pand (%rdi), %xmm0
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; CHECK-SSE2-NEXT: por %xmm1, %xmm0
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; CHECK-SSE2-NEXT: retq
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;
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; CHECK-XOP-LABEL: out_constant_varx_mone:
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; CHECK-XOP: # %bb.0:
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; CHECK-XOP-NEXT: vmovdqa (%rdx), %xmm0
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; CHECK-XOP-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
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; CHECK-XOP-NEXT: vpxor %xmm1, %xmm0, %xmm1
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; CHECK-XOP-NEXT: vpand (%rdi), %xmm0, %xmm0
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; CHECK-XOP-NEXT: vpor %xmm1, %xmm0, %xmm0
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; CHECK-XOP-NEXT: retq
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%x = load <4 x i32>, <4 x i32> *%px, align 16
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%y = load <4 x i32>, <4 x i32> *%py, align 16
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%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
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%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
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%mx = and <4 x i32> %mask, %x
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%my = and <4 x i32> %notmask, <i32 -1, i32 -1, i32 -1, i32 -1>
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%r = or <4 x i32> %mx, %my
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ret <4 x i32> %r
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}
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define <4 x i32> @in_constant_varx_mone(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
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; CHECK-SSE1-LABEL: in_constant_varx_mone:
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; CHECK-SSE1: # %bb.0:
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2018-09-20 02:59:08 +08:00
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; CHECK-SSE1-NEXT: movq %rdi, %rax
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2018-05-22 05:40:51 +08:00
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; CHECK-SSE1-NEXT: movaps (%rsi), %xmm0
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; CHECK-SSE1-NEXT: andnps (%rcx), %xmm0
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; CHECK-SSE1-NEXT: xorps {{.*}}(%rip), %xmm0
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; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
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; CHECK-SSE1-NEXT: retq
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;
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; CHECK-SSE2-LABEL: in_constant_varx_mone:
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; CHECK-SSE2: # %bb.0:
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2018-05-22 05:41:10 +08:00
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; CHECK-SSE2-NEXT: movdqa (%rdi), %xmm0
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2018-05-22 05:40:51 +08:00
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; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm1
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2018-05-22 05:41:10 +08:00
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; CHECK-SSE2-NEXT: pandn (%rdx), %xmm0
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; CHECK-SSE2-NEXT: pxor %xmm1, %xmm0
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2018-05-22 05:40:51 +08:00
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; CHECK-SSE2-NEXT: retq
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;
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; CHECK-XOP-LABEL: in_constant_varx_mone:
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; CHECK-XOP: # %bb.0:
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2018-05-22 05:41:10 +08:00
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; CHECK-XOP-NEXT: vmovdqa (%rdi), %xmm0
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2018-05-22 05:40:51 +08:00
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; CHECK-XOP-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
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2018-05-22 05:41:10 +08:00
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; CHECK-XOP-NEXT: vpandn (%rdx), %xmm0, %xmm0
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; CHECK-XOP-NEXT: vpxor %xmm1, %xmm0, %xmm0
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2018-05-22 05:40:51 +08:00
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; CHECK-XOP-NEXT: retq
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%x = load <4 x i32>, <4 x i32> *%px, align 16
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%y = load <4 x i32>, <4 x i32> *%py, align 16
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%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
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%n0 = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> ; %x
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%n1 = and <4 x i32> %n0, %mask
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%r = xor <4 x i32> %n1, <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %r
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}
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; This is not a canonical form. Testing for completeness only.
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define <4 x i32> @out_constant_varx_mone_invmask(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
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; CHECK-SSE1-LABEL: out_constant_varx_mone_invmask:
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; CHECK-SSE1: # %bb.0:
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2018-09-20 02:59:08 +08:00
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; CHECK-SSE1-NEXT: movq %rdi, %rax
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2019-03-17 23:45:38 +08:00
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; CHECK-SSE1-NEXT: movaps (%rsi), %xmm0
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; CHECK-SSE1-NEXT: orps (%rcx), %xmm0
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; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
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2018-05-22 05:40:51 +08:00
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; CHECK-SSE1-NEXT: retq
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;
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; CHECK-SSE2-LABEL: out_constant_varx_mone_invmask:
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; CHECK-SSE2: # %bb.0:
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2019-03-17 23:45:38 +08:00
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; CHECK-SSE2-NEXT: movaps (%rdi), %xmm0
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; CHECK-SSE2-NEXT: orps (%rdx), %xmm0
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2018-05-22 05:40:51 +08:00
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; CHECK-SSE2-NEXT: retq
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;
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; CHECK-XOP-LABEL: out_constant_varx_mone_invmask:
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; CHECK-XOP: # %bb.0:
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2019-03-17 23:45:38 +08:00
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; CHECK-XOP-NEXT: vmovaps (%rdi), %xmm0
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; CHECK-XOP-NEXT: vorps (%rdx), %xmm0, %xmm0
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2018-05-22 05:40:51 +08:00
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; CHECK-XOP-NEXT: retq
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%x = load <4 x i32>, <4 x i32> *%px, align 16
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%y = load <4 x i32>, <4 x i32> *%py, align 16
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%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
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%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
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%mx = and <4 x i32> %notmask, %x
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%my = and <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
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%r = or <4 x i32> %mx, %my
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ret <4 x i32> %r
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}
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; This is not a canonical form. Testing for completeness only.
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define <4 x i32> @in_constant_varx_mone_invmask(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
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; CHECK-SSE1-LABEL: in_constant_varx_mone_invmask:
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; CHECK-SSE1: # %bb.0:
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2018-09-20 02:59:08 +08:00
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; CHECK-SSE1-NEXT: movq %rdi, %rax
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2018-05-22 05:40:51 +08:00
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; CHECK-SSE1-NEXT: movaps (%rsi), %xmm0
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2018-10-02 17:08:51 +08:00
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; CHECK-SSE1-NEXT: movaps {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
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2018-05-22 05:40:51 +08:00
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; CHECK-SSE1-NEXT: movaps (%rcx), %xmm2
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; CHECK-SSE1-NEXT: xorps %xmm1, %xmm2
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; CHECK-SSE1-NEXT: andnps %xmm2, %xmm0
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; CHECK-SSE1-NEXT: xorps %xmm1, %xmm0
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; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
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; CHECK-SSE1-NEXT: retq
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;
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; CHECK-SSE2-LABEL: in_constant_varx_mone_invmask:
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; CHECK-SSE2: # %bb.0:
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2018-10-27 01:21:26 +08:00
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; CHECK-SSE2-NEXT: movdqa (%rdi), %xmm0
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2018-05-22 05:41:10 +08:00
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; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm1
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2018-10-27 01:21:26 +08:00
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; CHECK-SSE2-NEXT: movdqa (%rdx), %xmm2
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2018-05-22 05:41:10 +08:00
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; CHECK-SSE2-NEXT: pxor %xmm1, %xmm2
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; CHECK-SSE2-NEXT: pandn %xmm2, %xmm0
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2018-05-22 05:40:51 +08:00
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; CHECK-SSE2-NEXT: pxor %xmm1, %xmm0
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; CHECK-SSE2-NEXT: retq
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;
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; CHECK-XOP-LABEL: in_constant_varx_mone_invmask:
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; CHECK-XOP: # %bb.0:
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2018-10-27 01:21:26 +08:00
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; CHECK-XOP-NEXT: vmovdqa (%rdi), %xmm0
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2018-05-22 05:40:51 +08:00
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; CHECK-XOP-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
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2018-10-27 01:21:26 +08:00
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; CHECK-XOP-NEXT: vpxor (%rdx), %xmm1, %xmm2
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2018-05-22 05:41:10 +08:00
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; CHECK-XOP-NEXT: vpandn %xmm2, %xmm0, %xmm0
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2018-05-22 05:40:51 +08:00
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; CHECK-XOP-NEXT: vpxor %xmm1, %xmm0, %xmm0
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; CHECK-XOP-NEXT: retq
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%x = load <4 x i32>, <4 x i32> *%px, align 16
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%y = load <4 x i32>, <4 x i32> *%py, align 16
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%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
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%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
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%n0 = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> ; %x
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%n1 = and <4 x i32> %n0, %notmask
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%r = xor <4 x i32> %n1, <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %r
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}
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define <4 x i32> @out_constant_varx_42(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
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; CHECK-SSE1-LABEL: out_constant_varx_42:
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; CHECK-SSE1: # %bb.0:
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2018-09-20 02:59:08 +08:00
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; CHECK-SSE1-NEXT: movq %rdi, %rax
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2018-05-22 05:40:51 +08:00
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; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
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; CHECK-SSE1-NEXT: movaps (%rsi), %xmm1
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; CHECK-SSE1-NEXT: andps %xmm0, %xmm1
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; CHECK-SSE1-NEXT: andnps {{.*}}(%rip), %xmm0
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; CHECK-SSE1-NEXT: orps %xmm1, %xmm0
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; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
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; CHECK-SSE1-NEXT: retq
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;
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; CHECK-SSE2-LABEL: out_constant_varx_42:
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; CHECK-SSE2: # %bb.0:
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; CHECK-SSE2-NEXT: movaps (%rdx), %xmm0
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; CHECK-SSE2-NEXT: movaps (%rdi), %xmm1
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; CHECK-SSE2-NEXT: andps %xmm0, %xmm1
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; CHECK-SSE2-NEXT: andnps {{.*}}(%rip), %xmm0
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; CHECK-SSE2-NEXT: orps %xmm1, %xmm0
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; CHECK-SSE2-NEXT: retq
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;
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; CHECK-XOP-LABEL: out_constant_varx_42:
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; CHECK-XOP: # %bb.0:
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; CHECK-XOP-NEXT: vmovdqa (%rdi), %xmm0
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; CHECK-XOP-NEXT: vmovdqa (%rdx), %xmm1
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; CHECK-XOP-NEXT: vpcmov %xmm1, {{.*}}(%rip), %xmm0, %xmm0
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; CHECK-XOP-NEXT: retq
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%x = load <4 x i32>, <4 x i32> *%px, align 16
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%y = load <4 x i32>, <4 x i32> *%py, align 16
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%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
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%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
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%mx = and <4 x i32> %mask, %x
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%my = and <4 x i32> %notmask, <i32 42, i32 42, i32 42, i32 42>
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%r = or <4 x i32> %mx, %my
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ret <4 x i32> %r
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}
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define <4 x i32> @in_constant_varx_42(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
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; CHECK-SSE1-LABEL: in_constant_varx_42:
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; CHECK-SSE1: # %bb.0:
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2018-09-20 02:59:08 +08:00
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; CHECK-SSE1-NEXT: movq %rdi, %rax
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2018-05-22 05:41:02 +08:00
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; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
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2018-05-22 05:40:51 +08:00
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; CHECK-SSE1-NEXT: movaps (%rsi), %xmm1
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2018-05-22 05:41:02 +08:00
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; CHECK-SSE1-NEXT: andps %xmm0, %xmm1
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; CHECK-SSE1-NEXT: andnps {{.*}}(%rip), %xmm0
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; CHECK-SSE1-NEXT: orps %xmm1, %xmm0
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; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
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2018-05-22 05:40:51 +08:00
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; CHECK-SSE1-NEXT: retq
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;
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; CHECK-SSE2-LABEL: in_constant_varx_42:
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; CHECK-SSE2: # %bb.0:
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2018-05-22 05:41:02 +08:00
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; CHECK-SSE2-NEXT: movaps (%rdx), %xmm0
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; CHECK-SSE2-NEXT: movaps (%rdi), %xmm1
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; CHECK-SSE2-NEXT: andps %xmm0, %xmm1
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; CHECK-SSE2-NEXT: andnps {{.*}}(%rip), %xmm0
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; CHECK-SSE2-NEXT: orps %xmm1, %xmm0
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2018-05-22 05:40:51 +08:00
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; CHECK-SSE2-NEXT: retq
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;
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; CHECK-XOP-LABEL: in_constant_varx_42:
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; CHECK-XOP: # %bb.0:
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2018-05-22 05:41:02 +08:00
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; CHECK-XOP-NEXT: vmovdqa (%rdi), %xmm0
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; CHECK-XOP-NEXT: vmovdqa (%rdx), %xmm1
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|
; CHECK-XOP-NEXT: vpcmov %xmm1, {{.*}}(%rip), %xmm0, %xmm0
|
2018-05-22 05:40:51 +08:00
|
|
|
; CHECK-XOP-NEXT: retq
|
|
|
|
|
%x = load <4 x i32>, <4 x i32> *%px, align 16
|
|
|
|
|
%y = load <4 x i32>, <4 x i32> *%py, align 16
|
|
|
|
|
%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
|
|
|
|
|
%n0 = xor <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42> ; %x
|
|
|
|
|
%n1 = and <4 x i32> %n0, %mask
|
|
|
|
|
%r = xor <4 x i32> %n1, <i32 42, i32 42, i32 42, i32 42>
|
|
|
|
|
ret <4 x i32> %r
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; This is not a canonical form. Testing for completeness only.
|
|
|
|
|
define <4 x i32> @out_constant_varx_42_invmask(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
|
|
|
|
|
; CHECK-SSE1-LABEL: out_constant_varx_42_invmask:
|
|
|
|
|
; CHECK-SSE1: # %bb.0:
|
2018-09-20 02:59:08 +08:00
|
|
|
; CHECK-SSE1-NEXT: movq %rdi, %rax
|
2018-05-22 05:40:51 +08:00
|
|
|
; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
|
|
|
|
|
; CHECK-SSE1-NEXT: movaps %xmm0, %xmm1
|
|
|
|
|
; CHECK-SSE1-NEXT: andnps (%rsi), %xmm1
|
|
|
|
|
; CHECK-SSE1-NEXT: andps {{.*}}(%rip), %xmm0
|
|
|
|
|
; CHECK-SSE1-NEXT: orps %xmm1, %xmm0
|
|
|
|
|
; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
|
|
|
|
|
; CHECK-SSE1-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; CHECK-SSE2-LABEL: out_constant_varx_42_invmask:
|
|
|
|
|
; CHECK-SSE2: # %bb.0:
|
|
|
|
|
; CHECK-SSE2-NEXT: movaps (%rdx), %xmm0
|
|
|
|
|
; CHECK-SSE2-NEXT: movaps %xmm0, %xmm1
|
|
|
|
|
; CHECK-SSE2-NEXT: andnps (%rdi), %xmm1
|
|
|
|
|
; CHECK-SSE2-NEXT: andps {{.*}}(%rip), %xmm0
|
|
|
|
|
; CHECK-SSE2-NEXT: orps %xmm1, %xmm0
|
|
|
|
|
; CHECK-SSE2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; CHECK-XOP-LABEL: out_constant_varx_42_invmask:
|
|
|
|
|
; CHECK-XOP: # %bb.0:
|
|
|
|
|
; CHECK-XOP-NEXT: vmovdqa (%rdx), %xmm0
|
|
|
|
|
; CHECK-XOP-NEXT: vmovdqa {{.*#+}} xmm1 = [42,42,42,42]
|
|
|
|
|
; CHECK-XOP-NEXT: vpcmov %xmm0, (%rdi), %xmm1, %xmm0
|
|
|
|
|
; CHECK-XOP-NEXT: retq
|
|
|
|
|
%x = load <4 x i32>, <4 x i32> *%px, align 16
|
|
|
|
|
%y = load <4 x i32>, <4 x i32> *%py, align 16
|
|
|
|
|
%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
|
|
|
|
|
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
|
|
|
|
|
%mx = and <4 x i32> %notmask, %x
|
|
|
|
|
%my = and <4 x i32> %mask, <i32 42, i32 42, i32 42, i32 42>
|
|
|
|
|
%r = or <4 x i32> %mx, %my
|
|
|
|
|
ret <4 x i32> %r
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; This is not a canonical form. Testing for completeness only.
|
|
|
|
|
define <4 x i32> @in_constant_varx_42_invmask(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
|
|
|
|
|
; CHECK-SSE1-LABEL: in_constant_varx_42_invmask:
|
|
|
|
|
; CHECK-SSE1: # %bb.0:
|
2018-09-20 02:59:08 +08:00
|
|
|
; CHECK-SSE1-NEXT: movq %rdi, %rax
|
2018-05-22 05:40:51 +08:00
|
|
|
; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
|
2018-05-22 05:41:02 +08:00
|
|
|
; CHECK-SSE1-NEXT: movaps %xmm0, %xmm1
|
|
|
|
|
; CHECK-SSE1-NEXT: andnps (%rsi), %xmm1
|
|
|
|
|
; CHECK-SSE1-NEXT: andps {{.*}}(%rip), %xmm0
|
|
|
|
|
; CHECK-SSE1-NEXT: orps %xmm1, %xmm0
|
2018-05-22 05:40:51 +08:00
|
|
|
; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
|
|
|
|
|
; CHECK-SSE1-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; CHECK-SSE2-LABEL: in_constant_varx_42_invmask:
|
|
|
|
|
; CHECK-SSE2: # %bb.0:
|
|
|
|
|
; CHECK-SSE2-NEXT: movaps (%rdx), %xmm0
|
2018-05-22 05:41:02 +08:00
|
|
|
; CHECK-SSE2-NEXT: movaps %xmm0, %xmm1
|
|
|
|
|
; CHECK-SSE2-NEXT: andnps (%rdi), %xmm1
|
|
|
|
|
; CHECK-SSE2-NEXT: andps {{.*}}(%rip), %xmm0
|
|
|
|
|
; CHECK-SSE2-NEXT: orps %xmm1, %xmm0
|
2018-05-22 05:40:51 +08:00
|
|
|
; CHECK-SSE2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; CHECK-XOP-LABEL: in_constant_varx_42_invmask:
|
|
|
|
|
; CHECK-XOP: # %bb.0:
|
2018-05-22 05:41:02 +08:00
|
|
|
; CHECK-XOP-NEXT: vmovdqa (%rdx), %xmm0
|
|
|
|
|
; CHECK-XOP-NEXT: vmovdqa {{.*#+}} xmm1 = [42,42,42,42]
|
|
|
|
|
; CHECK-XOP-NEXT: vpcmov %xmm0, (%rdi), %xmm1, %xmm0
|
2018-05-22 05:40:51 +08:00
|
|
|
; CHECK-XOP-NEXT: retq
|
|
|
|
|
%x = load <4 x i32>, <4 x i32> *%px, align 16
|
|
|
|
|
%y = load <4 x i32>, <4 x i32> *%py, align 16
|
|
|
|
|
%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
|
|
|
|
|
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
|
|
|
|
|
%n0 = xor <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42> ; %x
|
|
|
|
|
%n1 = and <4 x i32> %n0, %notmask
|
|
|
|
|
%r = xor <4 x i32> %n1, <i32 42, i32 42, i32 42, i32 42>
|
|
|
|
|
ret <4 x i32> %r
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <4 x i32> @out_constant_mone_vary(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
|
|
|
|
|
; CHECK-SSE1-LABEL: out_constant_mone_vary:
|
|
|
|
|
; CHECK-SSE1: # %bb.0:
|
2018-09-20 02:59:08 +08:00
|
|
|
; CHECK-SSE1-NEXT: movq %rdi, %rax
|
2019-03-17 23:45:38 +08:00
|
|
|
; CHECK-SSE1-NEXT: movaps (%rdx), %xmm0
|
|
|
|
|
; CHECK-SSE1-NEXT: orps (%rcx), %xmm0
|
|
|
|
|
; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
|
2018-05-22 05:40:51 +08:00
|
|
|
; CHECK-SSE1-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; CHECK-SSE2-LABEL: out_constant_mone_vary:
|
|
|
|
|
; CHECK-SSE2: # %bb.0:
|
2019-03-17 23:45:38 +08:00
|
|
|
; CHECK-SSE2-NEXT: movaps (%rsi), %xmm0
|
|
|
|
|
; CHECK-SSE2-NEXT: orps (%rdx), %xmm0
|
2018-05-22 05:40:51 +08:00
|
|
|
; CHECK-SSE2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; CHECK-XOP-LABEL: out_constant_mone_vary:
|
|
|
|
|
; CHECK-XOP: # %bb.0:
|
2019-03-17 23:45:38 +08:00
|
|
|
; CHECK-XOP-NEXT: vmovaps (%rsi), %xmm0
|
|
|
|
|
; CHECK-XOP-NEXT: vorps (%rdx), %xmm0, %xmm0
|
2018-05-22 05:40:51 +08:00
|
|
|
; CHECK-XOP-NEXT: retq
|
|
|
|
|
%x = load <4 x i32>, <4 x i32> *%px, align 16
|
|
|
|
|
%y = load <4 x i32>, <4 x i32> *%py, align 16
|
|
|
|
|
%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
|
|
|
|
|
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
|
|
|
|
|
%mx = and <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
|
|
|
|
|
%my = and <4 x i32> %notmask, %y
|
|
|
|
|
%r = or <4 x i32> %mx, %my
|
|
|
|
|
ret <4 x i32> %r
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <4 x i32> @in_constant_mone_vary(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
|
|
|
|
|
; CHECK-SSE1-LABEL: in_constant_mone_vary:
|
|
|
|
|
; CHECK-SSE1: # %bb.0:
|
2018-09-20 02:59:08 +08:00
|
|
|
; CHECK-SSE1-NEXT: movq %rdi, %rax
|
2019-03-28 03:54:41 +08:00
|
|
|
; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
|
|
|
|
|
; CHECK-SSE1-NEXT: movaps %xmm0, %xmm1
|
|
|
|
|
; CHECK-SSE1-NEXT: andnps (%rdx), %xmm1
|
|
|
|
|
; CHECK-SSE1-NEXT: orps %xmm0, %xmm1
|
|
|
|
|
; CHECK-SSE1-NEXT: movaps %xmm1, (%rdi)
|
2018-05-22 05:40:51 +08:00
|
|
|
; CHECK-SSE1-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; CHECK-SSE2-LABEL: in_constant_mone_vary:
|
|
|
|
|
; CHECK-SSE2: # %bb.0:
|
2019-03-17 23:45:38 +08:00
|
|
|
; CHECK-SSE2-NEXT: movaps (%rsi), %xmm0
|
|
|
|
|
; CHECK-SSE2-NEXT: orps (%rdx), %xmm0
|
2018-05-22 05:40:51 +08:00
|
|
|
; CHECK-SSE2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; CHECK-XOP-LABEL: in_constant_mone_vary:
|
|
|
|
|
; CHECK-XOP: # %bb.0:
|
2019-03-17 23:45:38 +08:00
|
|
|
; CHECK-XOP-NEXT: vmovaps (%rsi), %xmm0
|
|
|
|
|
; CHECK-XOP-NEXT: vorps (%rdx), %xmm0, %xmm0
|
2018-05-22 05:40:51 +08:00
|
|
|
; CHECK-XOP-NEXT: retq
|
|
|
|
|
%x = load <4 x i32>, <4 x i32> *%px, align 16
|
|
|
|
|
%y = load <4 x i32>, <4 x i32> *%py, align 16
|
|
|
|
|
%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
|
|
|
|
|
%n0 = xor <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %y ; %x
|
|
|
|
|
%n1 = and <4 x i32> %n0, %mask
|
|
|
|
|
%r = xor <4 x i32> %n1, %y
|
|
|
|
|
ret <4 x i32> %r
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; This is not a canonical form. Testing for completeness only.
|
|
|
|
|
define <4 x i32> @out_constant_mone_vary_invmask(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
|
|
|
|
|
; CHECK-SSE1-LABEL: out_constant_mone_vary_invmask:
|
|
|
|
|
; CHECK-SSE1: # %bb.0:
|
2018-09-20 02:59:08 +08:00
|
|
|
; CHECK-SSE1-NEXT: movq %rdi, %rax
|
2018-05-22 05:40:51 +08:00
|
|
|
; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
|
2018-10-02 17:08:51 +08:00
|
|
|
; CHECK-SSE1-NEXT: movaps {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
|
2018-05-22 05:40:51 +08:00
|
|
|
; CHECK-SSE1-NEXT: xorps %xmm0, %xmm1
|
|
|
|
|
; CHECK-SSE1-NEXT: andps (%rdx), %xmm0
|
|
|
|
|
; CHECK-SSE1-NEXT: orps %xmm1, %xmm0
|
|
|
|
|
; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
|
|
|
|
|
; CHECK-SSE1-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; CHECK-SSE2-LABEL: out_constant_mone_vary_invmask:
|
|
|
|
|
; CHECK-SSE2: # %bb.0:
|
|
|
|
|
; CHECK-SSE2-NEXT: movdqa (%rdx), %xmm0
|
|
|
|
|
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm1
|
|
|
|
|
; CHECK-SSE2-NEXT: pxor %xmm0, %xmm1
|
|
|
|
|
; CHECK-SSE2-NEXT: pand (%rsi), %xmm0
|
|
|
|
|
; CHECK-SSE2-NEXT: por %xmm1, %xmm0
|
|
|
|
|
; CHECK-SSE2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; CHECK-XOP-LABEL: out_constant_mone_vary_invmask:
|
|
|
|
|
; CHECK-XOP: # %bb.0:
|
|
|
|
|
; CHECK-XOP-NEXT: vmovdqa (%rdx), %xmm0
|
|
|
|
|
; CHECK-XOP-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
|
|
|
|
|
; CHECK-XOP-NEXT: vpxor %xmm1, %xmm0, %xmm1
|
|
|
|
|
; CHECK-XOP-NEXT: vpand (%rsi), %xmm0, %xmm0
|
|
|
|
|
; CHECK-XOP-NEXT: vpor %xmm0, %xmm1, %xmm0
|
|
|
|
|
; CHECK-XOP-NEXT: retq
|
|
|
|
|
%x = load <4 x i32>, <4 x i32> *%px, align 16
|
|
|
|
|
%y = load <4 x i32>, <4 x i32> *%py, align 16
|
|
|
|
|
%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
|
|
|
|
|
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
|
|
|
|
|
%mx = and <4 x i32> %notmask, <i32 -1, i32 -1, i32 -1, i32 -1>
|
|
|
|
|
%my = and <4 x i32> %mask, %y
|
|
|
|
|
%r = or <4 x i32> %mx, %my
|
|
|
|
|
ret <4 x i32> %r
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; This is not a canonical form. Testing for completeness only.
|
|
|
|
|
define <4 x i32> @in_constant_mone_vary_invmask(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
|
|
|
|
|
; CHECK-SSE1-LABEL: in_constant_mone_vary_invmask:
|
|
|
|
|
; CHECK-SSE1: # %bb.0:
|
2018-09-20 02:59:08 +08:00
|
|
|
; CHECK-SSE1-NEXT: movq %rdi, %rax
|
2018-05-22 05:41:02 +08:00
|
|
|
; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
|
2019-03-28 03:54:41 +08:00
|
|
|
; CHECK-SSE1-NEXT: movaps {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
|
|
|
|
|
; CHECK-SSE1-NEXT: xorps %xmm0, %xmm1
|
|
|
|
|
; CHECK-SSE1-NEXT: andps (%rdx), %xmm0
|
|
|
|
|
; CHECK-SSE1-NEXT: orps %xmm1, %xmm0
|
2018-05-22 05:41:02 +08:00
|
|
|
; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
|
2018-05-22 05:40:51 +08:00
|
|
|
; CHECK-SSE1-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; CHECK-SSE2-LABEL: in_constant_mone_vary_invmask:
|
|
|
|
|
; CHECK-SSE2: # %bb.0:
|
2019-03-28 03:54:41 +08:00
|
|
|
; CHECK-SSE2-NEXT: movdqa (%rdx), %xmm0
|
|
|
|
|
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm1
|
|
|
|
|
; CHECK-SSE2-NEXT: pxor %xmm0, %xmm1
|
|
|
|
|
; CHECK-SSE2-NEXT: pand (%rsi), %xmm0
|
|
|
|
|
; CHECK-SSE2-NEXT: por %xmm1, %xmm0
|
2018-05-22 05:40:51 +08:00
|
|
|
; CHECK-SSE2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; CHECK-XOP-LABEL: in_constant_mone_vary_invmask:
|
|
|
|
|
; CHECK-XOP: # %bb.0:
|
2019-03-28 03:54:41 +08:00
|
|
|
; CHECK-XOP-NEXT: vmovdqa (%rdx), %xmm0
|
|
|
|
|
; CHECK-XOP-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
|
|
|
|
|
; CHECK-XOP-NEXT: vpxor %xmm1, %xmm0, %xmm1
|
|
|
|
|
; CHECK-XOP-NEXT: vpand (%rsi), %xmm0, %xmm0
|
|
|
|
|
; CHECK-XOP-NEXT: vpor %xmm0, %xmm1, %xmm0
|
2018-05-22 05:40:51 +08:00
|
|
|
; CHECK-XOP-NEXT: retq
|
|
|
|
|
%x = load <4 x i32>, <4 x i32> *%px, align 16
|
|
|
|
|
%y = load <4 x i32>, <4 x i32> *%py, align 16
|
|
|
|
|
%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
|
|
|
|
|
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
|
|
|
|
|
%n0 = xor <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %y ; %x
|
|
|
|
|
%n1 = and <4 x i32> %n0, %notmask
|
|
|
|
|
%r = xor <4 x i32> %n1, %y
|
|
|
|
|
ret <4 x i32> %r
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <4 x i32> @out_constant_42_vary(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
|
|
|
|
|
; CHECK-SSE1-LABEL: out_constant_42_vary:
|
|
|
|
|
; CHECK-SSE1: # %bb.0:
|
2018-09-20 02:59:08 +08:00
|
|
|
; CHECK-SSE1-NEXT: movq %rdi, %rax
|
2018-05-22 05:40:51 +08:00
|
|
|
; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
|
2018-10-02 17:08:51 +08:00
|
|
|
; CHECK-SSE1-NEXT: movaps {{.*#+}} xmm1 = [5.88545355E-44,5.88545355E-44,5.88545355E-44,5.88545355E-44]
|
2018-05-22 05:40:51 +08:00
|
|
|
; CHECK-SSE1-NEXT: andps %xmm0, %xmm1
|
|
|
|
|
; CHECK-SSE1-NEXT: andnps (%rdx), %xmm0
|
|
|
|
|
; CHECK-SSE1-NEXT: orps %xmm1, %xmm0
|
|
|
|
|
; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
|
|
|
|
|
; CHECK-SSE1-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; CHECK-SSE2-LABEL: out_constant_42_vary:
|
|
|
|
|
; CHECK-SSE2: # %bb.0:
|
|
|
|
|
; CHECK-SSE2-NEXT: movaps (%rdx), %xmm0
|
|
|
|
|
; CHECK-SSE2-NEXT: movaps {{.*#+}} xmm1 = [42,42,42,42]
|
|
|
|
|
; CHECK-SSE2-NEXT: andps %xmm0, %xmm1
|
|
|
|
|
; CHECK-SSE2-NEXT: andnps (%rsi), %xmm0
|
|
|
|
|
; CHECK-SSE2-NEXT: orps %xmm1, %xmm0
|
|
|
|
|
; CHECK-SSE2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; CHECK-XOP-LABEL: out_constant_42_vary:
|
|
|
|
|
; CHECK-XOP: # %bb.0:
|
|
|
|
|
; CHECK-XOP-NEXT: vmovdqa (%rdx), %xmm0
|
|
|
|
|
; CHECK-XOP-NEXT: vmovdqa {{.*#+}} xmm1 = [42,42,42,42]
|
|
|
|
|
; CHECK-XOP-NEXT: vpcmov %xmm0, (%rsi), %xmm1, %xmm0
|
|
|
|
|
; CHECK-XOP-NEXT: retq
|
|
|
|
|
%x = load <4 x i32>, <4 x i32> *%px, align 16
|
|
|
|
|
%y = load <4 x i32>, <4 x i32> *%py, align 16
|
|
|
|
|
%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
|
|
|
|
|
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
|
|
|
|
|
%mx = and <4 x i32> %mask, <i32 42, i32 42, i32 42, i32 42>
|
|
|
|
|
%my = and <4 x i32> %notmask, %y
|
|
|
|
|
%r = or <4 x i32> %mx, %my
|
|
|
|
|
ret <4 x i32> %r
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <4 x i32> @in_constant_42_vary(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
|
|
|
|
|
; CHECK-SSE1-LABEL: in_constant_42_vary:
|
|
|
|
|
; CHECK-SSE1: # %bb.0:
|
2018-09-20 02:59:08 +08:00
|
|
|
; CHECK-SSE1-NEXT: movq %rdi, %rax
|
2018-05-22 05:41:02 +08:00
|
|
|
; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
|
|
|
|
|
; CHECK-SSE1-NEXT: movaps %xmm0, %xmm1
|
|
|
|
|
; CHECK-SSE1-NEXT: andnps (%rdx), %xmm1
|
|
|
|
|
; CHECK-SSE1-NEXT: andps {{.*}}(%rip), %xmm0
|
|
|
|
|
; CHECK-SSE1-NEXT: orps %xmm1, %xmm0
|
|
|
|
|
; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
|
2018-05-22 05:40:51 +08:00
|
|
|
; CHECK-SSE1-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; CHECK-SSE2-LABEL: in_constant_42_vary:
|
|
|
|
|
; CHECK-SSE2: # %bb.0:
|
2018-05-22 05:41:02 +08:00
|
|
|
; CHECK-SSE2-NEXT: movaps (%rdx), %xmm0
|
|
|
|
|
; CHECK-SSE2-NEXT: movaps %xmm0, %xmm1
|
|
|
|
|
; CHECK-SSE2-NEXT: andnps (%rsi), %xmm1
|
|
|
|
|
; CHECK-SSE2-NEXT: andps {{.*}}(%rip), %xmm0
|
|
|
|
|
; CHECK-SSE2-NEXT: orps %xmm1, %xmm0
|
2018-05-22 05:40:51 +08:00
|
|
|
; CHECK-SSE2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; CHECK-XOP-LABEL: in_constant_42_vary:
|
|
|
|
|
; CHECK-XOP: # %bb.0:
|
2018-05-22 05:41:02 +08:00
|
|
|
; CHECK-XOP-NEXT: vmovdqa (%rdx), %xmm0
|
|
|
|
|
; CHECK-XOP-NEXT: vmovdqa {{.*#+}} xmm1 = [42,42,42,42]
|
|
|
|
|
; CHECK-XOP-NEXT: vpcmov %xmm0, (%rsi), %xmm1, %xmm0
|
2018-05-22 05:40:51 +08:00
|
|
|
; CHECK-XOP-NEXT: retq
|
|
|
|
|
%x = load <4 x i32>, <4 x i32> *%px, align 16
|
|
|
|
|
%y = load <4 x i32>, <4 x i32> *%py, align 16
|
|
|
|
|
%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
|
|
|
|
|
%n0 = xor <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %y ; %x
|
|
|
|
|
%n1 = and <4 x i32> %n0, %mask
|
|
|
|
|
%r = xor <4 x i32> %n1, %y
|
|
|
|
|
ret <4 x i32> %r
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; This is not a canonical form. Testing for completeness only.
|
|
|
|
|
define <4 x i32> @out_constant_42_vary_invmask(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
|
|
|
|
|
; CHECK-SSE1-LABEL: out_constant_42_vary_invmask:
|
|
|
|
|
; CHECK-SSE1: # %bb.0:
|
2018-09-20 02:59:08 +08:00
|
|
|
; CHECK-SSE1-NEXT: movq %rdi, %rax
|
2018-05-22 05:40:51 +08:00
|
|
|
; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
|
|
|
|
|
; CHECK-SSE1-NEXT: movaps %xmm0, %xmm1
|
|
|
|
|
; CHECK-SSE1-NEXT: andnps {{.*}}(%rip), %xmm1
|
|
|
|
|
; CHECK-SSE1-NEXT: andps (%rdx), %xmm0
|
|
|
|
|
; CHECK-SSE1-NEXT: orps %xmm1, %xmm0
|
|
|
|
|
; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
|
|
|
|
|
; CHECK-SSE1-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; CHECK-SSE2-LABEL: out_constant_42_vary_invmask:
|
|
|
|
|
; CHECK-SSE2: # %bb.0:
|
|
|
|
|
; CHECK-SSE2-NEXT: movaps (%rdx), %xmm0
|
|
|
|
|
; CHECK-SSE2-NEXT: movaps %xmm0, %xmm1
|
|
|
|
|
; CHECK-SSE2-NEXT: andnps {{.*}}(%rip), %xmm1
|
|
|
|
|
; CHECK-SSE2-NEXT: andps (%rsi), %xmm0
|
|
|
|
|
; CHECK-SSE2-NEXT: orps %xmm1, %xmm0
|
|
|
|
|
; CHECK-SSE2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; CHECK-XOP-LABEL: out_constant_42_vary_invmask:
|
|
|
|
|
; CHECK-XOP: # %bb.0:
|
|
|
|
|
; CHECK-XOP-NEXT: vmovdqa (%rsi), %xmm0
|
|
|
|
|
; CHECK-XOP-NEXT: vmovdqa (%rdx), %xmm1
|
|
|
|
|
; CHECK-XOP-NEXT: vpcmov %xmm1, {{.*}}(%rip), %xmm0, %xmm0
|
|
|
|
|
; CHECK-XOP-NEXT: retq
|
|
|
|
|
%x = load <4 x i32>, <4 x i32> *%px, align 16
|
|
|
|
|
%y = load <4 x i32>, <4 x i32> *%py, align 16
|
|
|
|
|
%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
|
|
|
|
|
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
|
|
|
|
|
%mx = and <4 x i32> %notmask, <i32 42, i32 42, i32 42, i32 42>
|
|
|
|
|
%my = and <4 x i32> %mask, %y
|
|
|
|
|
%r = or <4 x i32> %mx, %my
|
|
|
|
|
ret <4 x i32> %r
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; This is not a canonical form. Testing for completeness only.
|
|
|
|
|
define <4 x i32> @in_constant_42_vary_invmask(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
|
|
|
|
|
; CHECK-SSE1-LABEL: in_constant_42_vary_invmask:
|
|
|
|
|
; CHECK-SSE1: # %bb.0:
|
2018-09-20 02:59:08 +08:00
|
|
|
; CHECK-SSE1-NEXT: movq %rdi, %rax
|
2018-05-22 05:41:02 +08:00
|
|
|
; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
|
|
|
|
|
; CHECK-SSE1-NEXT: movaps (%rdx), %xmm1
|
|
|
|
|
; CHECK-SSE1-NEXT: andps %xmm0, %xmm1
|
|
|
|
|
; CHECK-SSE1-NEXT: andnps {{.*}}(%rip), %xmm0
|
|
|
|
|
; CHECK-SSE1-NEXT: orps %xmm1, %xmm0
|
|
|
|
|
; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
|
2018-05-22 05:40:51 +08:00
|
|
|
; CHECK-SSE1-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; CHECK-SSE2-LABEL: in_constant_42_vary_invmask:
|
|
|
|
|
; CHECK-SSE2: # %bb.0:
|
|
|
|
|
; CHECK-SSE2-NEXT: movaps (%rdx), %xmm0
|
2018-05-22 05:41:02 +08:00
|
|
|
; CHECK-SSE2-NEXT: movaps (%rsi), %xmm1
|
|
|
|
|
; CHECK-SSE2-NEXT: andps %xmm0, %xmm1
|
|
|
|
|
; CHECK-SSE2-NEXT: andnps {{.*}}(%rip), %xmm0
|
|
|
|
|
; CHECK-SSE2-NEXT: orps %xmm1, %xmm0
|
2018-05-22 05:40:51 +08:00
|
|
|
; CHECK-SSE2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; CHECK-XOP-LABEL: in_constant_42_vary_invmask:
|
|
|
|
|
; CHECK-XOP: # %bb.0:
|
2018-05-22 05:41:02 +08:00
|
|
|
; CHECK-XOP-NEXT: vmovdqa (%rsi), %xmm0
|
|
|
|
|
; CHECK-XOP-NEXT: vmovdqa (%rdx), %xmm1
|
|
|
|
|
; CHECK-XOP-NEXT: vpcmov %xmm1, {{.*}}(%rip), %xmm0, %xmm0
|
2018-05-22 05:40:51 +08:00
|
|
|
; CHECK-XOP-NEXT: retq
|
|
|
|
|
%x = load <4 x i32>, <4 x i32> *%px, align 16
|
|
|
|
|
%y = load <4 x i32>, <4 x i32> *%py, align 16
|
|
|
|
|
%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
|
|
|
|
|
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
|
|
|
|
|
%n0 = xor <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %y ; %x
|
|
|
|
|
%n1 = and <4 x i32> %n0, %notmask
|
|
|
|
|
%r = xor <4 x i32> %n1, %y
|
|
|
|
|
ret <4 x i32> %r
|
|
|
|
|
}
|
