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llvm-project/llvm/test/CodeGen/X86/sse42-intrinsics-x86_64.ll

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[X86] Remove sse4.2 intrinsic tests from the avx intrinsics test file. Fix some other consistency issues. They are all covered by the SSE4.2 intrinsics test with SSE4.2, AVX, and AVX512 command lines. Merge sse42.ll into the other intrinsics test. Rename sse42_64.ll to be named like other intrinsic tests. llvm-svn: 295707
2017-02-21 16:06:05 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx,+sse4.2 -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,SSE
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,AVX,AVX1
[X86][SSE4] Tweak rL333828 sse41/sse42 cleanup to recover SKX/EVEX2VEX testing Just testing for avx512f was missing the tests for EVEX TO VEX Compression encoding etc. llvm-svn: 333830
2018-06-03 02:01:09 +08:00
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
[X86] Remove sse4.2 intrinsic tests from the avx intrinsics test file. Fix some other consistency issues. They are all covered by the SSE4.2 intrinsics test with SSE4.2, AVX, and AVX512 command lines. Merge sse42.ll into the other intrinsics test. Rename sse42_64.ll to be named like other intrinsic tests. llvm-svn: 295707
2017-02-21 16:06:05 +08:00
declare i64 @llvm.x86.sse42.crc32.64.8(i64, i8) nounwind
declare i64 @llvm.x86.sse42.crc32.64.64(i64, i64) nounwind
define i64 @crc32_64_8(i64 %a, i8 %b) nounwind {
; CHECK-LABEL: crc32_64_8:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: ## %bb.0:
[X86] Remove sse4.2 intrinsic tests from the avx intrinsics test file. Fix some other consistency issues. They are all covered by the SSE4.2 intrinsics test with SSE4.2, AVX, and AVX512 command lines. Merge sse42.ll into the other intrinsics test. Rename sse42_64.ll to be named like other intrinsic tests. llvm-svn: 295707
2017-02-21 16:06:05 +08:00
; CHECK-NEXT: movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; CHECK-NEXT: crc32b %sil, %eax ## encoding: [0xf2,0x40,0x0f,0x38,0xf0,0xc6]
[X86] Remove sse4.2 intrinsic tests from the avx intrinsics test file. Fix some other consistency issues. They are all covered by the SSE4.2 intrinsics test with SSE4.2, AVX, and AVX512 command lines. Merge sse42.ll into the other intrinsics test. Rename sse42_64.ll to be named like other intrinsic tests. llvm-svn: 295707
2017-02-21 16:06:05 +08:00
; CHECK-NEXT: retq ## encoding: [0xc3]
%tmp = call i64 @llvm.x86.sse42.crc32.64.8(i64 %a, i8 %b)
ret i64 %tmp
}
define i64 @crc32_64_64(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: crc32_64_64:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: ## %bb.0:
[X86] Remove sse4.2 intrinsic tests from the avx intrinsics test file. Fix some other consistency issues. They are all covered by the SSE4.2 intrinsics test with SSE4.2, AVX, and AVX512 command lines. Merge sse42.ll into the other intrinsics test. Rename sse42_64.ll to be named like other intrinsic tests. llvm-svn: 295707
2017-02-21 16:06:05 +08:00
; CHECK-NEXT: movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; CHECK-NEXT: crc32q %rsi, %rax ## encoding: [0xf2,0x48,0x0f,0x38,0xf1,0xc6]
[X86] Remove sse4.2 intrinsic tests from the avx intrinsics test file. Fix some other consistency issues. They are all covered by the SSE4.2 intrinsics test with SSE4.2, AVX, and AVX512 command lines. Merge sse42.ll into the other intrinsics test. Rename sse42_64.ll to be named like other intrinsic tests. llvm-svn: 295707
2017-02-21 16:06:05 +08:00
; CHECK-NEXT: retq ## encoding: [0xc3]
%tmp = call i64 @llvm.x86.sse42.crc32.64.64(i64 %a, i64 %b)
ret i64 %tmp
}