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llvm-project/llvm/test/CodeGen/ARM/cxx-tlscc.ll

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CXX_FAST_TLS calling convention: Add support for ARM on Darwin. rdar://9001553 llvm-svn: 257417
2016-01-12 07:50:43 +08:00
; RUN: llc < %s -mtriple=armv7k-apple-watchos2.0 | FileCheck %s
[LLVM] Remove unwanted --check-prefix=CHECK from unit tests. NFC. Summary: Removed unwanted --check-prefix=CHECK from numerous unit tests. Reviewers: t.p.northover, dblaikie, uweigand, MatzeB, tstellarAMD, mcrosier Subscribers: mcrosier, dsanders Differential Revision: http://reviews.llvm.org/D19279 llvm-svn: 266834
2016-04-20 07:51:52 +08:00
; RUN: llc < %s -mtriple=armv7k-apple-watchos2.0 -enable-shrink-wrap=true | FileCheck %s
CXX_FAST_TLS calling convention: Add support for ARM on Darwin. rdar://9001553 llvm-svn: 257417
2016-01-12 07:50:43 +08:00
; RUN: llc < %s -mtriple=armv7-apple-ios8.0 | FileCheck %s
[LLVM] Remove unwanted --check-prefix=CHECK from unit tests. NFC. Summary: Removed unwanted --check-prefix=CHECK from numerous unit tests. Reviewers: t.p.northover, dblaikie, uweigand, MatzeB, tstellarAMD, mcrosier Subscribers: mcrosier, dsanders Differential Revision: http://reviews.llvm.org/D19279 llvm-svn: 266834
2016-04-20 07:51:52 +08:00
; RUN: llc < %s -mtriple=armv7-apple-ios8.0 -enable-shrink-wrap=true | FileCheck %s
CXX_FAST_TLS calling convention: Add support for ARM on Darwin. rdar://9001553 llvm-svn: 257417
2016-01-12 07:50:43 +08:00
[CXX_FAST_TLS] fix issues with O0 on ARM, AArch64 and X86. Since at O0, explicit copies via SplitCSR may not be removed even if they are unnecessary, we choose not to use SplitCSR at O0. llvm-svn: 263855
2016-03-19 07:38:49 +08:00
; RUN: llc < %s -mtriple=armv7k-apple-watchos2.0 -O0 | FileCheck --check-prefix=CHECK-O0 --check-prefix=WATCH-O0 %s
; RUN: llc < %s -mtriple=armv7-apple-ios8.0 -O0 | FileCheck --check-prefix=CHECK-O0 --check-prefix=IOS-O0 %s
[CXX_FAST_TLS] Fix issues in ARM. We need to be careful on which registers can be explicitly handled via copies. Prologue, Epilogue use physical registers and if one belongs to the set of CSRsViaCopy, it will no longer be CSRed, since PEI overwrites it after the explicit copies. llvm-svn: 263857
2016-03-19 07:44:37 +08:00
; RUN: llc < %s -mtriple=thumbv7-apple-ios8.0 | FileCheck --check-prefix=THUMB %s
CXX_FAST_TLS calling convention: Add support for ARM on Darwin. rdar://9001553 llvm-svn: 257417
2016-01-12 07:50:43 +08:00
%struct.S = type { i8 }
@sg = internal thread_local global %struct.S zeroinitializer, align 1
@__dso_handle = external global i8
@__tls_guard = internal thread_local unnamed_addr global i1 false
CXX_FAST_TLS calling convention: fix issue on ARM. When we have a single basic block, the explicit copy-back instructions should be inserted right before the terminator. Before this fix, they were wrongly placed at the beginning of the basic block. PR26136 llvm-svn: 257930
2016-01-16 04:24:11 +08:00
@sum1 = internal thread_local global i32 0, align 4
CXX_FAST_TLS calling convention: Add support for ARM on Darwin. rdar://9001553 llvm-svn: 257417
2016-01-12 07:50:43 +08:00
[CXX_FAST_TLS] fix issues with O0 on ARM, AArch64 and X86. Since at O0, explicit copies via SplitCSR may not be removed even if they are unnecessary, we choose not to use SplitCSR at O0. llvm-svn: 263855
2016-03-19 07:38:49 +08:00
%class.C = type { i32 }
@tC = internal thread_local global %class.C zeroinitializer, align 4
CXX_FAST_TLS calling convention: Add support for ARM on Darwin. rdar://9001553 llvm-svn: 257417
2016-01-12 07:50:43 +08:00
declare %struct.S* @_ZN1SC1Ev(%struct.S* returned)
declare %struct.S* @_ZN1SD1Ev(%struct.S* returned)
declare i32 @_tlv_atexit(void (i8*)*, i8*, i8*)
[CXX_FAST_TLS] Fix issues in ARM. We need to be careful on which registers can be explicitly handled via copies. Prologue, Epilogue use physical registers and if one belongs to the set of CSRsViaCopy, it will no longer be CSRed, since PEI overwrites it after the explicit copies. llvm-svn: 263857
2016-03-19 07:44:37 +08:00
; Make sure Epilog does not overwrite an explicitly-handled CSR in CXX_FAST_TLS.
; THUMB-LABEL: _ZTW2sg
; THUMB: push {{.*}}lr
; THUMB: blx
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8). The benchmarking summarized in http://lists.llvm.org/pipermail/llvm-dev/2017-May/113525.html showed this is beneficial for a wide range of cores. As is to be expected, quite a few small adaptations are needed to the regressions tests, as the difference in scheduling results in: - Quite a few small instruction schedule differences. - A few changes in register allocation decisions caused by different instruction schedules. - A few changes in IfConversion decisions, due to a difference in instruction schedule and/or the estimated cost of a branch mispredict. llvm-svn: 306514
2017-06-28 15:07:03 +08:00
; THUMB: bne{{(.w)?}} [[TH_end:.?LBB0_[0-9]+]]
[CXX_FAST_TLS] Fix issues in ARM. We need to be careful on which registers can be explicitly handled via copies. Prologue, Epilogue use physical registers and if one belongs to the set of CSRsViaCopy, it will no longer be CSRed, since PEI overwrites it after the explicit copies. llvm-svn: 263857
2016-03-19 07:44:37 +08:00
; THUMB: blx
; THUMB: tlv_atexit
; THUMB: [[TH_end]]:
; THUMB: blx
; THUMB: r4
; THUMB: pop {{.*}}r4
Migrate function attribute "no-frame-pointer-elim" to "frame-pointer"="all" as cleanups after D56351
2019-12-25 07:52:21 +08:00
define cxx_fast_tlscc nonnull %struct.S* @_ZTW2sg() nounwind "frame-pointer"="all" {
CXX_FAST_TLS calling convention: Add support for ARM on Darwin. rdar://9001553 llvm-svn: 257417
2016-01-12 07:50:43 +08:00
%.b.i = load i1, i1* @__tls_guard, align 1
br i1 %.b.i, label %__tls_init.exit, label %init.i
init.i:
store i1 true, i1* @__tls_guard, align 1
%call.i.i = tail call %struct.S* @_ZN1SC1Ev(%struct.S* nonnull @sg)
%1 = tail call i32 @_tlv_atexit(void (i8*)* nonnull bitcast (%struct.S* (%struct.S*)* @_ZN1SD1Ev to void (i8*)*), i8* nonnull getelementptr inbounds (%struct.S, %struct.S* @sg, i64 0, i32 0), i8* nonnull @__dso_handle)
br label %__tls_init.exit
__tls_init.exit:
ret %struct.S* @sg
}
; CHECK-LABEL: _ZTW2sg
[CXX_FAST_TLS] Fix issues in ARM. We need to be careful on which registers can be explicitly handled via copies. Prologue, Epilogue use physical registers and if one belongs to the set of CSRsViaCopy, it will no longer be CSRed, since PEI overwrites it after the explicit copies. llvm-svn: 263857
2016-03-19 07:44:37 +08:00
; CHECK: push {r4, r5, r7, lr}
; CHECK: push {r11, r12}
CXX_FAST_TLS calling convention: performance improvement for ARM. This is the same change on ARM as r255821 on AArch64. rdar://9001553 llvm-svn: 257424
2016-01-12 08:47:18 +08:00
; CHECK-NOT: vpush {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31}
; CHECK-NOT: vpush {d0, d1, d2, d3, d4, d5, d6, d7}
CXX_FAST_TLS calling convention: Add support for ARM on Darwin. rdar://9001553 llvm-svn: 257417
2016-01-12 07:50:43 +08:00
; CHECK: blx
; CHECK: bne [[BB_end:.?LBB0_[0-9]+]]
[CXX_FAST_TLS] fix issues with O0 on ARM, AArch64 and X86. Since at O0, explicit copies via SplitCSR may not be removed even if they are unnecessary, we choose not to use SplitCSR at O0. llvm-svn: 263855
2016-03-19 07:38:49 +08:00
; CHECK: blx
CXX_FAST_TLS calling convention: Add support for ARM on Darwin. rdar://9001553 llvm-svn: 257417
2016-01-12 07:50:43 +08:00
; CHECK: tlv_atexit
; CHECK: [[BB_end]]:
; CHECK: blx
CXX_FAST_TLS calling convention: performance improvement for ARM. This is the same change on ARM as r255821 on AArch64. rdar://9001553 llvm-svn: 257424
2016-01-12 08:47:18 +08:00
; CHECK-NOT: vpop {d0, d1, d2, d3, d4, d5, d6, d7}
; CHECK-NOT: vpop {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31}
; CHECK-NOT: pop {r9, r12}
; CHECK-NOT: pop {r1, r2, r3, r4, r7, pc}
[CXX_FAST_TLS] Fix issues in ARM. We need to be careful on which registers can be explicitly handled via copies. Prologue, Epilogue use physical registers and if one belongs to the set of CSRsViaCopy, it will no longer be CSRed, since PEI overwrites it after the explicit copies. llvm-svn: 263857
2016-03-19 07:44:37 +08:00
; CHECK: pop {r4, r5, r7, pc}
CXX_FAST_TLS calling convention: fix issue on ARM. When we have a single basic block, the explicit copy-back instructions should be inserted right before the terminator. Before this fix, they were wrongly placed at the beginning of the basic block. PR26136 llvm-svn: 257930
2016-01-16 04:24:11 +08:00
[CXX_FAST_TLS] fix issues with O0 on ARM, AArch64 and X86. Since at O0, explicit copies via SplitCSR may not be removed even if they are unnecessary, we choose not to use SplitCSR at O0. llvm-svn: 263855
2016-03-19 07:38:49 +08:00
; CHECK-O0-LABEL: _ZTW2sg
; WATCH-O0: push {r1, r2, r3, r6, r7, lr}
; IOS-O0: push {r1, r2, r3, r7, lr}
; CHECK-O0: push {r9, r12}
; CHECK-O0: vpush {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31}
; CHECK-O0: vpush {d0, d1, d2, d3, d4, d5, d6, d7}
; CHECK-O0: blx
; CHECK-O0: bne [[BB_end:.?LBB0_[0-9]+]]
; CHECK-O0: blx
; CHECK-O0: tlv_atexit
; CHECK-O0: [[BB_end]]:
; CHECK-O0: blx
; CHECK-O0: vpop {d0, d1, d2, d3, d4, d5, d6, d7}
; CHECK-O0: vpop {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31}
; CHECK-O0: pop {r9, r12}
; WATCH-O0: pop {r1, r2, r3, r6, r7, pc}
; IOS-O0: pop {r1, r2, r3, r7, pc}
CXX_FAST_TLS calling convention: fix issue on ARM. When we have a single basic block, the explicit copy-back instructions should be inserted right before the terminator. Before this fix, they were wrongly placed at the beginning of the basic block. PR26136 llvm-svn: 257930
2016-01-16 04:24:11 +08:00
; CHECK-LABEL: _ZTW4sum1
; CHECK-NOT: push {r1, r2, r3, r4, r7, lr}
; CHECK-NOT: push {r9, r12}
; CHECK-NOT: vpush {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31}
; CHECK-NOT: vpush {d0, d1, d2, d3, d4, d5, d6, d7}
; CHECK: blx
[CXX_FAST_TLS] fix issues with O0 on ARM, AArch64 and X86. Since at O0, explicit copies via SplitCSR may not be removed even if they are unnecessary, we choose not to use SplitCSR at O0. llvm-svn: 263855
2016-03-19 07:38:49 +08:00
; CHECK-O0-LABEL: _ZTW4sum1
; CHECK-O0-NOT: vpush
; CHECK-O0-NOT: vstr
; CHECK-O0-NOT: vpop
; CHECK-O0-NOT: vldr
; CHECK-O0: pop
Migrate function attribute "no-frame-pointer-elim" to "frame-pointer"="all" as cleanups after D56351
2019-12-25 07:52:21 +08:00
define cxx_fast_tlscc nonnull i32* @_ZTW4sum1() nounwind "frame-pointer"="all" {
CXX_FAST_TLS calling convention: fix issue on ARM. When we have a single basic block, the explicit copy-back instructions should be inserted right before the terminator. Before this fix, they were wrongly placed at the beginning of the basic block. PR26136 llvm-svn: 257930
2016-01-16 04:24:11 +08:00
ret i32* @sum1
}
[CXX_FAST_TLS] fix issues with O0 on ARM, AArch64 and X86. Since at O0, explicit copies via SplitCSR may not be removed even if they are unnecessary, we choose not to use SplitCSR at O0. llvm-svn: 263855
2016-03-19 07:38:49 +08:00
; Make sure at O0, we don't generate spilling/reloading of the CSRs.
; CHECK-O0-LABEL: tls_test2
; CHECK-O0: push
; CHECK-O0-NOT: vpush
; CHECK-O0-NOT: vstr
; CHECK-O0: tls_helper
; CHECK-O0-NOT: vpop
; CHECK-O0-NOT: vldr
; CHECK-O0: pop
declare cxx_fast_tlscc void @tls_helper()
Migrate function attribute "no-frame-pointer-elim" to "frame-pointer"="all" as cleanups after D56351
2019-12-25 07:52:21 +08:00
define cxx_fast_tlscc %class.C* @tls_test2() #1 "frame-pointer"="all" {
[CXX_FAST_TLS] fix issues with O0 on ARM, AArch64 and X86. Since at O0, explicit copies via SplitCSR may not be removed even if they are unnecessary, we choose not to use SplitCSR at O0. llvm-svn: 263855
2016-03-19 07:38:49 +08:00
call cxx_fast_tlscc void @tls_helper()
ret %class.C* @tC
}
[CXX_FAST_TLS] Disable tail call when calling conventions are mismatched. Since CXX_FAST_TLS has a bigger set of CSRs, we don't tail call when caller and callee have mismatched calling conventions. llvm-svn: 263856
2016-03-19 07:41:51 +08:00
; Make sure we do not allow tail call when caller and callee have different
; calling conventions.
declare %class.C* @_ZN1CD1Ev(%class.C* readnone returned %this)
; CHECK-LABEL: tls_test
; CHECK: bl __tlv_atexit
Migrate function attribute "no-frame-pointer-elim" to "frame-pointer"="all" as cleanups after D56351
2019-12-25 07:52:21 +08:00
define cxx_fast_tlscc void @__tls_test() "frame-pointer"="all" {
[CXX_FAST_TLS] Disable tail call when calling conventions are mismatched. Since CXX_FAST_TLS has a bigger set of CSRs, we don't tail call when caller and callee have mismatched calling conventions. llvm-svn: 263856
2016-03-19 07:41:51 +08:00
entry:
store i32 0, i32* getelementptr inbounds (%class.C, %class.C* @tC, i64 0, i32 0), align 4
%0 = tail call i32 @_tlv_atexit(void (i8*)* bitcast (%class.C* (%class.C*)* @_ZN1CD1Ev to void (i8*)*), i8* bitcast (%class.C* @tC to i8*), i8* nonnull @__dso_handle) #1
ret void
}
ARM, AArch64, X86: Check preserved registers for tail calls. We can only perform a tail call to a callee that preserves all the registers that the caller needs to preserve. This situation happens with calling conventions like preserver_mostcc or cxx_fast_tls. It was explicitely handled for fast_tls and failing for preserve_most. This patch generalizes the check to any calling convention. Related to rdar://24207743 Differential Revision: http://reviews.llvm.org/D18680 llvm-svn: 265329
2016-04-05 02:56:13 +08:00
declare void @somefunc()
Migrate function attribute "no-frame-pointer-elim" to "frame-pointer"="all" as cleanups after D56351
2019-12-25 07:52:21 +08:00
define cxx_fast_tlscc void @test_ccmismatch_notail() "frame-pointer"="all" {
ARM, AArch64, X86: Check preserved registers for tail calls. We can only perform a tail call to a callee that preserves all the registers that the caller needs to preserve. This situation happens with calling conventions like preserver_mostcc or cxx_fast_tls. It was explicitely handled for fast_tls and failing for preserve_most. This patch generalizes the check to any calling convention. Related to rdar://24207743 Differential Revision: http://reviews.llvm.org/D18680 llvm-svn: 265329
2016-04-05 02:56:13 +08:00
; A tail call is not possible here because somefunc does not preserve enough
; registers.
; CHECK-LABEL: test_ccmismatch_notail:
; CHECK-NOT: b _somefunc
; CHECK: bl _somefunc
tail call void @somefunc()
ret void
}
declare cxx_fast_tlscc void @some_fast_tls_func()
Migrate function attribute "no-frame-pointer-elim" to "frame-pointer"="all" as cleanups after D56351
2019-12-25 07:52:21 +08:00
define void @test_ccmismatch_tail() "frame-pointer"="all" {
ARM, AArch64, X86: Check preserved registers for tail calls. We can only perform a tail call to a callee that preserves all the registers that the caller needs to preserve. This situation happens with calling conventions like preserver_mostcc or cxx_fast_tls. It was explicitely handled for fast_tls and failing for preserve_most. This patch generalizes the check to any calling convention. Related to rdar://24207743 Differential Revision: http://reviews.llvm.org/D18680 llvm-svn: 265329
2016-04-05 02:56:13 +08:00
; We can perform a tail call here because some_fast_tls_func preserves all
; necessary registers (and more).
; CHECK-LABEL: test_ccmismatch_tail:
; CHECK-NOT: bl _some_fast_tls_func
; CHECK: b _some_fast_tls_func
tail call cxx_fast_tlscc void @some_fast_tls_func()
ret void
}
Migrate function attribute "no-frame-pointer-elim" to "frame-pointer"="all" as cleanups after D56351
2019-12-25 07:52:21 +08:00
attributes #0 = { nounwind "frame-pointer"="all" }
[CXX_FAST_TLS] fix issues with O0 on ARM, AArch64 and X86. Since at O0, explicit copies via SplitCSR may not be removed even if they are unnecessary, we choose not to use SplitCSR at O0. llvm-svn: 263855
2016-03-19 07:38:49 +08:00
attributes #1 = { nounwind }