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llvm-project/llvm/test/CodeGen/X86/2010-01-18-DbgValue.ll

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Restore arch on these test, they fail on arm. llvm-svn: 111109
2010-08-16 04:42:56 +08:00
; RUN: llc -march=x86 -O0 < %s | FileCheck %s
Generate DEBUG_VALUE comments on x86. The (limited) dbg.declare's we currently generate go through both register allocators without perturbing the results. llvm-svn: 94480
2010-01-26 08:09:58 +08:00
; Currently, dbg.declare generates a DEBUG_VALUE comment. Eventually it will
; generate DWARF and this test will need to be modified or removed.
Update tests. Now DBG_VALUE instruction is created only if alloca corresponding to llvm.dbg.declare is missing. llvm-svn: 102524
2010-04-29 04:27:48 +08:00
%struct.Pt = type { double, double }
%struct.Rect = type { %struct.Pt, %struct.Pt }
define double @foo(%struct.Rect* byval %my_r0) nounwind ssp {
Generate DEBUG_VALUE comments on x86. The (limited) dbg.declare's we currently generate go through both register allocators without perturbing the results. llvm-svn: 94480
2010-01-26 08:09:58 +08:00
entry:
Update tests. Now DBG_VALUE instruction is created only if alloca corresponding to llvm.dbg.declare is missing. llvm-svn: 102524
2010-04-29 04:27:48 +08:00
;CHECK: DEBUG_VALUE
%retval = alloca double ; <double*> [#uses=2]
%0 = alloca double ; <double*> [#uses=2]
Generate DEBUG_VALUE comments on x86. The (limited) dbg.declare's we currently generate go through both register allocators without perturbing the results. llvm-svn: 94480
2010-01-26 08:09:58 +08:00
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
Update tests. Now DBG_VALUE instruction is created only if alloca corresponding to llvm.dbg.declare is missing. llvm-svn: 102524
2010-04-29 04:27:48 +08:00
call void @llvm.dbg.declare(metadata !{%struct.Rect* %my_r0}, metadata !0), !dbg !15
%1 = getelementptr inbounds %struct.Rect* %my_r0, i32 0, i32 0, !dbg !16 ; <%struct.Pt*> [#uses=1]
%2 = getelementptr inbounds %struct.Pt* %1, i32 0, i32 0, !dbg !16 ; <double*> [#uses=1]
%3 = load double* %2, align 8, !dbg !16 ; <double> [#uses=1]
store double %3, double* %0, align 8, !dbg !16
%4 = load double* %0, align 8, !dbg !16 ; <double> [#uses=1]
store double %4, double* %retval, align 8, !dbg !16
br label %return, !dbg !16
Generate DEBUG_VALUE comments on x86. The (limited) dbg.declare's we currently generate go through both register allocators without perturbing the results. llvm-svn: 94480
2010-01-26 08:09:58 +08:00
return: ; preds = %entry
Update tests. Now DBG_VALUE instruction is created only if alloca corresponding to llvm.dbg.declare is missing. llvm-svn: 102524
2010-04-29 04:27:48 +08:00
%retval1 = load double* %retval, !dbg !16 ; <double> [#uses=1]
ret double %retval1, !dbg !16
Generate DEBUG_VALUE comments on x86. The (limited) dbg.declare's we currently generate go through both register allocators without perturbing the results. llvm-svn: 94480
2010-01-26 08:09:58 +08:00
}
declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
Update tests. Now DBG_VALUE instruction is created only if alloca corresponding to llvm.dbg.declare is missing. llvm-svn: 102524
2010-04-29 04:27:48 +08:00
!0 = metadata !{i32 524545, metadata !1, metadata !"my_r0", metadata !2, i32 11, metadata !7} ; [ DW_TAG_arg_variable ]
!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 11, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ]
!2 = metadata !{i32 524329, metadata !"b2.c", metadata !"/tmp/", metadata !3} ; [ DW_TAG_file_type ]
!3 = metadata !{i32 524305, i32 0, i32 1, metadata !"b2.c", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
!4 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ]
!5 = metadata !{metadata !6, metadata !7}
!6 = metadata !{i32 524324, metadata !2, metadata !"double", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ]
!7 = metadata !{i32 524307, metadata !2, metadata !"Rect", metadata !2, i32 6, i64 256, i64 64, i64 0, i32 0, null, metadata !8, i32 0, null} ; [ DW_TAG_structure_type ]
!8 = metadata !{metadata !9, metadata !14}
!9 = metadata !{i32 524301, metadata !7, metadata !"P1", metadata !2, i32 7, i64 128, i64 64, i64 0, i32 0, metadata !10} ; [ DW_TAG_member ]
!10 = metadata !{i32 524307, metadata !2, metadata !"Pt", metadata !2, i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_structure_type ]
!11 = metadata !{metadata !12, metadata !13}
!12 = metadata !{i32 524301, metadata !10, metadata !"x", metadata !2, i32 2, i64 64, i64 64, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ]
!13 = metadata !{i32 524301, metadata !10, metadata !"y", metadata !2, i32 3, i64 64, i64 64, i64 64, i32 0, metadata !6} ; [ DW_TAG_member ]
!14 = metadata !{i32 524301, metadata !7, metadata !"P2", metadata !2, i32 8, i64 128, i64 64, i64 128, i32 0, metadata !10} ; [ DW_TAG_member ]
!15 = metadata !{i32 11, i32 0, metadata !1, null}
!16 = metadata !{i32 12, i32 0, metadata !17, null}
!17 = metadata !{i32 524299, metadata !1, i32 11, i32 0} ; [ DW_TAG_lexical_block ]