2005-01-07 15:44:53 +08:00
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//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
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2005-04-22 06:55:34 +08:00
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//
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2005-01-07 15:44:53 +08:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-04-22 06:55:34 +08:00
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//
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2005-01-07 15:44:53 +08:00
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//===----------------------------------------------------------------------===//
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//
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// This implements the TargetLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetLowering.h"
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2009-08-23 04:48:53 +08:00
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#include "llvm/MC/MCAsmInfo.h"
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2010-01-26 13:58:28 +08:00
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#include "llvm/MC/MCExpr.h"
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2006-05-12 14:33:49 +08:00
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#include "llvm/Target/TargetData.h"
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2009-07-28 11:13:23 +08:00
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#include "llvm/Target/TargetLoweringObjectFile.h"
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2005-01-07 15:44:53 +08:00
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#include "llvm/Target/TargetMachine.h"
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2008-02-11 02:45:23 +08:00
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#include "llvm/Target/TargetRegisterInfo.h"
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2009-07-28 11:13:23 +08:00
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#include "llvm/Target/TargetSubtarget.h"
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Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.
Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.
This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.
Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.
This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.
llvm-svn: 49572
2008-04-12 12:36:06 +08:00
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#include "llvm/GlobalVariable.h"
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2006-03-31 08:28:56 +08:00
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#include "llvm/DerivedTypes.h"
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2008-05-13 03:56:52 +08:00
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#include "llvm/CodeGen/MachineFrameInfo.h"
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2010-01-26 07:26:13 +08:00
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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2010-01-26 14:28:43 +08:00
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#include "llvm/CodeGen/MachineFunction.h"
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2005-01-07 15:44:53 +08:00
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#include "llvm/CodeGen/SelectionDAG.h"
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2007-09-07 12:06:50 +08:00
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#include "llvm/ADT/STLExtras.h"
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2009-07-12 04:10:48 +08:00
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#include "llvm/Support/ErrorHandling.h"
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2006-01-30 12:09:27 +08:00
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#include "llvm/Support/MathExtras.h"
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2005-01-07 15:44:53 +08:00
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using namespace llvm;
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2009-02-27 21:37:18 +08:00
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namespace llvm {
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TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
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bool isLocal = GV->hasLocalLinkage();
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bool isDeclaration = GV->isDeclaration();
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// FIXME: what should we do for protected and internal visibility?
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// For variables, is internal different from hidden?
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bool isHidden = GV->hasHiddenVisibility();
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if (reloc == Reloc::PIC_) {
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if (isLocal || isHidden)
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return TLSModel::LocalDynamic;
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else
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return TLSModel::GeneralDynamic;
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} else {
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if (!isDeclaration || isHidden)
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return TLSModel::LocalExec;
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else
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return TLSModel::InitialExec;
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}
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}
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}
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2007-01-12 10:11:51 +08:00
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/// InitLibcallNames - Set default libcall names.
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///
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2007-01-13 06:51:10 +08:00
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static void InitLibcallNames(const char **Names) {
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2009-05-03 21:14:08 +08:00
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Names[RTLIB::SHL_I16] = "__ashlhi3";
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2007-01-12 10:11:51 +08:00
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Names[RTLIB::SHL_I32] = "__ashlsi3";
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Names[RTLIB::SHL_I64] = "__ashldi3";
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2008-07-12 00:52:29 +08:00
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Names[RTLIB::SHL_I128] = "__ashlti3";
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2009-05-03 21:14:08 +08:00
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Names[RTLIB::SRL_I16] = "__lshrhi3";
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2007-01-12 10:11:51 +08:00
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Names[RTLIB::SRL_I32] = "__lshrsi3";
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Names[RTLIB::SRL_I64] = "__lshrdi3";
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2008-07-12 00:52:29 +08:00
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Names[RTLIB::SRL_I128] = "__lshrti3";
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2009-05-03 21:14:08 +08:00
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Names[RTLIB::SRA_I16] = "__ashrhi3";
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2007-01-12 10:11:51 +08:00
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Names[RTLIB::SRA_I32] = "__ashrsi3";
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Names[RTLIB::SRA_I64] = "__ashrdi3";
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2008-07-12 00:52:29 +08:00
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Names[RTLIB::SRA_I128] = "__ashrti3";
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2009-11-08 01:14:39 +08:00
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Names[RTLIB::MUL_I8] = "__mulqi3";
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2009-05-03 21:14:08 +08:00
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Names[RTLIB::MUL_I16] = "__mulhi3";
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2007-01-12 10:11:51 +08:00
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Names[RTLIB::MUL_I32] = "__mulsi3";
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Names[RTLIB::MUL_I64] = "__muldi3";
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2008-07-10 23:35:05 +08:00
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Names[RTLIB::MUL_I128] = "__multi3";
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2009-11-08 01:14:39 +08:00
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Names[RTLIB::SDIV_I8] = "__divqi3";
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2009-05-03 21:18:16 +08:00
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Names[RTLIB::SDIV_I16] = "__divhi3";
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2007-01-12 10:11:51 +08:00
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Names[RTLIB::SDIV_I32] = "__divsi3";
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Names[RTLIB::SDIV_I64] = "__divdi3";
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2008-07-10 23:35:05 +08:00
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Names[RTLIB::SDIV_I128] = "__divti3";
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2009-11-08 01:14:39 +08:00
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Names[RTLIB::UDIV_I8] = "__udivqi3";
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2009-05-09 02:50:54 +08:00
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Names[RTLIB::UDIV_I16] = "__udivhi3";
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2007-01-12 10:11:51 +08:00
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Names[RTLIB::UDIV_I32] = "__udivsi3";
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Names[RTLIB::UDIV_I64] = "__udivdi3";
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2008-07-10 23:35:05 +08:00
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Names[RTLIB::UDIV_I128] = "__udivti3";
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2009-11-08 01:14:39 +08:00
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Names[RTLIB::SREM_I8] = "__modqi3";
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2009-05-03 21:18:16 +08:00
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Names[RTLIB::SREM_I16] = "__modhi3";
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2007-01-12 10:11:51 +08:00
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Names[RTLIB::SREM_I32] = "__modsi3";
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Names[RTLIB::SREM_I64] = "__moddi3";
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2008-07-10 23:35:05 +08:00
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Names[RTLIB::SREM_I128] = "__modti3";
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2009-11-08 01:14:39 +08:00
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Names[RTLIB::UREM_I8] = "__umodqi3";
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2009-05-03 21:19:57 +08:00
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Names[RTLIB::UREM_I16] = "__umodhi3";
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2007-01-12 10:11:51 +08:00
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Names[RTLIB::UREM_I32] = "__umodsi3";
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Names[RTLIB::UREM_I64] = "__umoddi3";
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2008-07-10 23:35:05 +08:00
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Names[RTLIB::UREM_I128] = "__umodti3";
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2007-01-12 10:11:51 +08:00
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Names[RTLIB::NEG_I32] = "__negsi2";
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Names[RTLIB::NEG_I64] = "__negdi2";
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Names[RTLIB::ADD_F32] = "__addsf3";
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Names[RTLIB::ADD_F64] = "__adddf3";
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2008-01-10 18:28:30 +08:00
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Names[RTLIB::ADD_F80] = "__addxf3";
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2007-10-06 04:04:43 +08:00
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Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
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2007-01-12 10:11:51 +08:00
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Names[RTLIB::SUB_F32] = "__subsf3";
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Names[RTLIB::SUB_F64] = "__subdf3";
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2008-01-10 18:28:30 +08:00
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Names[RTLIB::SUB_F80] = "__subxf3";
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2007-10-06 04:04:43 +08:00
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Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
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2007-01-12 10:11:51 +08:00
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Names[RTLIB::MUL_F32] = "__mulsf3";
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Names[RTLIB::MUL_F64] = "__muldf3";
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2008-01-10 18:28:30 +08:00
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Names[RTLIB::MUL_F80] = "__mulxf3";
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2007-10-06 04:04:43 +08:00
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Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
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2007-01-12 10:11:51 +08:00
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Names[RTLIB::DIV_F32] = "__divsf3";
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Names[RTLIB::DIV_F64] = "__divdf3";
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2008-01-10 18:28:30 +08:00
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Names[RTLIB::DIV_F80] = "__divxf3";
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2007-10-06 04:04:43 +08:00
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Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
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2007-01-12 10:11:51 +08:00
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Names[RTLIB::REM_F32] = "fmodf";
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Names[RTLIB::REM_F64] = "fmod";
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2008-01-10 18:28:30 +08:00
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Names[RTLIB::REM_F80] = "fmodl";
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2007-10-06 04:04:43 +08:00
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Names[RTLIB::REM_PPCF128] = "fmodl";
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2007-01-12 10:11:51 +08:00
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Names[RTLIB::POWI_F32] = "__powisf2";
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Names[RTLIB::POWI_F64] = "__powidf2";
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2007-10-06 04:04:43 +08:00
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Names[RTLIB::POWI_F80] = "__powixf2";
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Names[RTLIB::POWI_PPCF128] = "__powitf2";
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2007-01-12 10:11:51 +08:00
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Names[RTLIB::SQRT_F32] = "sqrtf";
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Names[RTLIB::SQRT_F64] = "sqrt";
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2007-10-06 04:04:43 +08:00
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Names[RTLIB::SQRT_F80] = "sqrtl";
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Names[RTLIB::SQRT_PPCF128] = "sqrtl";
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2008-09-04 08:47:13 +08:00
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Names[RTLIB::LOG_F32] = "logf";
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Names[RTLIB::LOG_F64] = "log";
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Names[RTLIB::LOG_F80] = "logl";
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Names[RTLIB::LOG_PPCF128] = "logl";
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Names[RTLIB::LOG2_F32] = "log2f";
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Names[RTLIB::LOG2_F64] = "log2";
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Names[RTLIB::LOG2_F80] = "log2l";
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Names[RTLIB::LOG2_PPCF128] = "log2l";
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Names[RTLIB::LOG10_F32] = "log10f";
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Names[RTLIB::LOG10_F64] = "log10";
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Names[RTLIB::LOG10_F80] = "log10l";
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Names[RTLIB::LOG10_PPCF128] = "log10l";
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Names[RTLIB::EXP_F32] = "expf";
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Names[RTLIB::EXP_F64] = "exp";
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Names[RTLIB::EXP_F80] = "expl";
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Names[RTLIB::EXP_PPCF128] = "expl";
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Names[RTLIB::EXP2_F32] = "exp2f";
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Names[RTLIB::EXP2_F64] = "exp2";
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Names[RTLIB::EXP2_F80] = "exp2l";
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Names[RTLIB::EXP2_PPCF128] = "exp2l";
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2007-01-12 10:11:51 +08:00
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Names[RTLIB::SIN_F32] = "sinf";
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Names[RTLIB::SIN_F64] = "sin";
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2008-01-10 18:28:30 +08:00
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Names[RTLIB::SIN_F80] = "sinl";
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Names[RTLIB::SIN_PPCF128] = "sinl";
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2007-01-12 10:11:51 +08:00
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Names[RTLIB::COS_F32] = "cosf";
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Names[RTLIB::COS_F64] = "cos";
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2008-01-10 18:28:30 +08:00
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Names[RTLIB::COS_F80] = "cosl";
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Names[RTLIB::COS_PPCF128] = "cosl";
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2007-10-12 07:09:10 +08:00
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Names[RTLIB::POW_F32] = "powf";
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Names[RTLIB::POW_F64] = "pow";
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Names[RTLIB::POW_F80] = "powl";
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Names[RTLIB::POW_PPCF128] = "powl";
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2008-08-22 02:38:14 +08:00
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Names[RTLIB::CEIL_F32] = "ceilf";
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Names[RTLIB::CEIL_F64] = "ceil";
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Names[RTLIB::CEIL_F80] = "ceill";
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Names[RTLIB::CEIL_PPCF128] = "ceill";
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Names[RTLIB::TRUNC_F32] = "truncf";
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Names[RTLIB::TRUNC_F64] = "trunc";
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Names[RTLIB::TRUNC_F80] = "truncl";
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Names[RTLIB::TRUNC_PPCF128] = "truncl";
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Names[RTLIB::RINT_F32] = "rintf";
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Names[RTLIB::RINT_F64] = "rint";
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Names[RTLIB::RINT_F80] = "rintl";
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Names[RTLIB::RINT_PPCF128] = "rintl";
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Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
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Names[RTLIB::NEARBYINT_F64] = "nearbyint";
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Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
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Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
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Names[RTLIB::FLOOR_F32] = "floorf";
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Names[RTLIB::FLOOR_F64] = "floor";
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Names[RTLIB::FLOOR_F80] = "floorl";
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Names[RTLIB::FLOOR_PPCF128] = "floorl";
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2007-01-12 10:11:51 +08:00
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Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
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Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
|
2008-08-08 03:01:24 +08:00
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Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
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Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
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Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
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Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
|
2009-06-16 18:22:58 +08:00
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Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfi8";
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Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfi16";
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2007-01-12 10:11:51 +08:00
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Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
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Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
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2008-03-11 07:03:31 +08:00
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Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
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2007-01-12 10:11:51 +08:00
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Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
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Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
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2008-03-11 07:03:31 +08:00
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Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
|
2008-07-10 23:33:02 +08:00
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Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
|
2007-10-06 04:04:43 +08:00
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Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
|
2008-03-11 07:03:31 +08:00
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Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
|
2008-06-26 04:24:48 +08:00
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Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
|
2007-10-06 04:04:43 +08:00
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Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
|
2008-03-11 07:03:31 +08:00
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Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
|
2009-06-16 18:22:58 +08:00
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Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfi8";
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Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfi16";
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2007-01-12 10:11:51 +08:00
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Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
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Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
|
2008-03-11 07:03:31 +08:00
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Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
|
2007-01-12 10:11:51 +08:00
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Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
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|
|
Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
|
2008-03-11 07:03:31 +08:00
|
|
|
Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
|
2007-10-06 04:04:43 +08:00
|
|
|
Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
|
|
|
|
|
Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
|
2008-03-11 07:03:31 +08:00
|
|
|
Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
|
2008-06-26 04:24:48 +08:00
|
|
|
Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
|
2007-10-06 04:04:43 +08:00
|
|
|
Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
|
2008-03-11 07:03:31 +08:00
|
|
|
Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
|
2007-01-12 10:11:51 +08:00
|
|
|
Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
|
|
|
|
|
Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
|
2008-07-12 00:57:02 +08:00
|
|
|
Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
|
|
|
|
|
Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
|
2007-01-12 10:11:51 +08:00
|
|
|
Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
|
|
|
|
|
Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
|
2007-10-06 04:04:43 +08:00
|
|
|
Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
|
|
|
|
|
Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
|
2008-03-05 09:08:17 +08:00
|
|
|
Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
|
|
|
|
|
Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
|
|
|
|
|
Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
|
|
|
|
|
Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
|
2007-01-12 10:11:51 +08:00
|
|
|
Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
|
|
|
|
|
Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
|
2008-07-12 01:00:14 +08:00
|
|
|
Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
|
|
|
|
|
Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
|
2007-01-12 10:11:51 +08:00
|
|
|
Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
|
|
|
|
|
Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
|
2008-07-12 01:00:14 +08:00
|
|
|
Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
|
|
|
|
|
Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
|
|
|
|
|
Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
|
|
|
|
|
Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
|
|
|
|
|
Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
|
|
|
|
|
Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
|
2007-01-12 10:11:51 +08:00
|
|
|
Names[RTLIB::OEQ_F32] = "__eqsf2";
|
|
|
|
|
Names[RTLIB::OEQ_F64] = "__eqdf2";
|
|
|
|
|
Names[RTLIB::UNE_F32] = "__nesf2";
|
|
|
|
|
Names[RTLIB::UNE_F64] = "__nedf2";
|
|
|
|
|
Names[RTLIB::OGE_F32] = "__gesf2";
|
|
|
|
|
Names[RTLIB::OGE_F64] = "__gedf2";
|
|
|
|
|
Names[RTLIB::OLT_F32] = "__ltsf2";
|
|
|
|
|
Names[RTLIB::OLT_F64] = "__ltdf2";
|
|
|
|
|
Names[RTLIB::OLE_F32] = "__lesf2";
|
|
|
|
|
Names[RTLIB::OLE_F64] = "__ledf2";
|
|
|
|
|
Names[RTLIB::OGT_F32] = "__gtsf2";
|
|
|
|
|
Names[RTLIB::OGT_F64] = "__gtdf2";
|
|
|
|
|
Names[RTLIB::UO_F32] = "__unordsf2";
|
|
|
|
|
Names[RTLIB::UO_F64] = "__unorddf2";
|
2007-01-31 17:29:11 +08:00
|
|
|
Names[RTLIB::O_F32] = "__unordsf2";
|
|
|
|
|
Names[RTLIB::O_F64] = "__unorddf2";
|
2009-07-30 17:12:56 +08:00
|
|
|
Names[RTLIB::MEMCPY] = "memcpy";
|
|
|
|
|
Names[RTLIB::MEMMOVE] = "memmove";
|
|
|
|
|
Names[RTLIB::MEMSET] = "memset";
|
2009-05-23 04:36:31 +08:00
|
|
|
Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
|
2007-01-31 17:29:11 +08:00
|
|
|
}
|
|
|
|
|
|
2009-08-15 04:10:52 +08:00
|
|
|
/// InitLibcallCallingConvs - Set default libcall CallingConvs.
|
|
|
|
|
///
|
|
|
|
|
static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
|
|
|
|
|
for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
|
|
|
|
|
CCs[i] = CallingConv::C;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2008-07-17 10:36:29 +08:00
|
|
|
/// getFPEXT - Return the FPEXT_*_* value for the given types, or
|
|
|
|
|
/// UNKNOWN_LIBCALL if there is none.
|
2009-08-11 06:56:29 +08:00
|
|
|
RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
|
2009-08-12 04:47:22 +08:00
|
|
|
if (OpVT == MVT::f32) {
|
|
|
|
|
if (RetVT == MVT::f64)
|
2008-07-17 10:36:29 +08:00
|
|
|
return FPEXT_F32_F64;
|
|
|
|
|
}
|
|
|
|
|
return UNKNOWN_LIBCALL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/// getFPROUND - Return the FPROUND_*_* value for the given types, or
|
|
|
|
|
/// UNKNOWN_LIBCALL if there is none.
|
2009-08-11 06:56:29 +08:00
|
|
|
RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
|
2009-08-12 04:47:22 +08:00
|
|
|
if (RetVT == MVT::f32) {
|
|
|
|
|
if (OpVT == MVT::f64)
|
2008-07-17 10:36:29 +08:00
|
|
|
return FPROUND_F64_F32;
|
2009-08-12 04:47:22 +08:00
|
|
|
if (OpVT == MVT::f80)
|
2008-08-08 03:01:24 +08:00
|
|
|
return FPROUND_F80_F32;
|
2009-08-12 04:47:22 +08:00
|
|
|
if (OpVT == MVT::ppcf128)
|
2008-08-08 03:01:24 +08:00
|
|
|
return FPROUND_PPCF128_F32;
|
2009-08-12 04:47:22 +08:00
|
|
|
} else if (RetVT == MVT::f64) {
|
|
|
|
|
if (OpVT == MVT::f80)
|
2008-08-08 03:01:24 +08:00
|
|
|
return FPROUND_F80_F64;
|
2009-08-12 04:47:22 +08:00
|
|
|
if (OpVT == MVT::ppcf128)
|
2008-08-08 03:01:24 +08:00
|
|
|
return FPROUND_PPCF128_F64;
|
2008-07-17 10:36:29 +08:00
|
|
|
}
|
|
|
|
|
return UNKNOWN_LIBCALL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
|
|
|
|
|
/// UNKNOWN_LIBCALL if there is none.
|
2009-08-11 06:56:29 +08:00
|
|
|
RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
|
2009-08-12 04:47:22 +08:00
|
|
|
if (OpVT == MVT::f32) {
|
|
|
|
|
if (RetVT == MVT::i8)
|
2009-06-16 17:03:58 +08:00
|
|
|
return FPTOSINT_F32_I8;
|
2009-08-12 04:47:22 +08:00
|
|
|
if (RetVT == MVT::i16)
|
2009-06-16 17:03:58 +08:00
|
|
|
return FPTOSINT_F32_I16;
|
2009-08-12 04:47:22 +08:00
|
|
|
if (RetVT == MVT::i32)
|
2008-07-17 10:36:29 +08:00
|
|
|
return FPTOSINT_F32_I32;
|
2009-08-12 04:47:22 +08:00
|
|
|
if (RetVT == MVT::i64)
|
2008-07-17 10:36:29 +08:00
|
|
|
return FPTOSINT_F32_I64;
|
2009-08-12 04:47:22 +08:00
|
|
|
if (RetVT == MVT::i128)
|
2008-07-17 10:36:29 +08:00
|
|
|
return FPTOSINT_F32_I128;
|
2009-08-12 04:47:22 +08:00
|
|
|
} else if (OpVT == MVT::f64) {
|
|
|
|
|
if (RetVT == MVT::i32)
|
2008-07-17 10:36:29 +08:00
|
|
|
return FPTOSINT_F64_I32;
|
2009-08-12 04:47:22 +08:00
|
|
|
if (RetVT == MVT::i64)
|
2008-07-17 10:36:29 +08:00
|
|
|
return FPTOSINT_F64_I64;
|
2009-08-12 04:47:22 +08:00
|
|
|
if (RetVT == MVT::i128)
|
2008-07-17 10:36:29 +08:00
|
|
|
return FPTOSINT_F64_I128;
|
2009-08-12 04:47:22 +08:00
|
|
|
} else if (OpVT == MVT::f80) {
|
|
|
|
|
if (RetVT == MVT::i32)
|
2008-07-17 10:36:29 +08:00
|
|
|
return FPTOSINT_F80_I32;
|
2009-08-12 04:47:22 +08:00
|
|
|
if (RetVT == MVT::i64)
|
2008-07-17 10:36:29 +08:00
|
|
|
return FPTOSINT_F80_I64;
|
2009-08-12 04:47:22 +08:00
|
|
|
if (RetVT == MVT::i128)
|
2008-07-17 10:36:29 +08:00
|
|
|
return FPTOSINT_F80_I128;
|
2009-08-12 04:47:22 +08:00
|
|
|
} else if (OpVT == MVT::ppcf128) {
|
|
|
|
|
if (RetVT == MVT::i32)
|
2008-07-17 10:36:29 +08:00
|
|
|
return FPTOSINT_PPCF128_I32;
|
2009-08-12 04:47:22 +08:00
|
|
|
if (RetVT == MVT::i64)
|
2008-07-17 10:36:29 +08:00
|
|
|
return FPTOSINT_PPCF128_I64;
|
2009-08-12 04:47:22 +08:00
|
|
|
if (RetVT == MVT::i128)
|
2008-07-17 10:36:29 +08:00
|
|
|
return FPTOSINT_PPCF128_I128;
|
|
|
|
|
}
|
|
|
|
|
return UNKNOWN_LIBCALL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
|
|
|
|
|
/// UNKNOWN_LIBCALL if there is none.
|
2009-08-11 06:56:29 +08:00
|
|
|
RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
|
2009-08-12 04:47:22 +08:00
|
|
|
if (OpVT == MVT::f32) {
|
|
|
|
|
if (RetVT == MVT::i8)
|
2009-06-16 17:03:58 +08:00
|
|
|
return FPTOUINT_F32_I8;
|
2009-08-12 04:47:22 +08:00
|
|
|
if (RetVT == MVT::i16)
|
2009-06-16 17:03:58 +08:00
|
|
|
return FPTOUINT_F32_I16;
|
2009-08-12 04:47:22 +08:00
|
|
|
if (RetVT == MVT::i32)
|
2008-07-17 10:36:29 +08:00
|
|
|
return FPTOUINT_F32_I32;
|
2009-08-12 04:47:22 +08:00
|
|
|
if (RetVT == MVT::i64)
|
2008-07-17 10:36:29 +08:00
|
|
|
return FPTOUINT_F32_I64;
|
2009-08-12 04:47:22 +08:00
|
|
|
if (RetVT == MVT::i128)
|
2008-07-17 10:36:29 +08:00
|
|
|
return FPTOUINT_F32_I128;
|
2009-08-12 04:47:22 +08:00
|
|
|
} else if (OpVT == MVT::f64) {
|
|
|
|
|
if (RetVT == MVT::i32)
|
2008-07-17 10:36:29 +08:00
|
|
|
return FPTOUINT_F64_I32;
|
2009-08-12 04:47:22 +08:00
|
|
|
if (RetVT == MVT::i64)
|
2008-07-17 10:36:29 +08:00
|
|
|
return FPTOUINT_F64_I64;
|
2009-08-12 04:47:22 +08:00
|
|
|
if (RetVT == MVT::i128)
|
2008-07-17 10:36:29 +08:00
|
|
|
return FPTOUINT_F64_I128;
|
2009-08-12 04:47:22 +08:00
|
|
|
} else if (OpVT == MVT::f80) {
|
|
|
|
|
if (RetVT == MVT::i32)
|
2008-07-17 10:36:29 +08:00
|
|
|
return FPTOUINT_F80_I32;
|
2009-08-12 04:47:22 +08:00
|
|
|
if (RetVT == MVT::i64)
|
2008-07-17 10:36:29 +08:00
|
|
|
return FPTOUINT_F80_I64;
|
2009-08-12 04:47:22 +08:00
|
|
|
if (RetVT == MVT::i128)
|
2008-07-17 10:36:29 +08:00
|
|
|
return FPTOUINT_F80_I128;
|
2009-08-12 04:47:22 +08:00
|
|
|
} else if (OpVT == MVT::ppcf128) {
|
|
|
|
|
if (RetVT == MVT::i32)
|
2008-07-17 10:36:29 +08:00
|
|
|
return FPTOUINT_PPCF128_I32;
|
2009-08-12 04:47:22 +08:00
|
|
|
if (RetVT == MVT::i64)
|
2008-07-17 10:36:29 +08:00
|
|
|
return FPTOUINT_PPCF128_I64;
|
2009-08-12 04:47:22 +08:00
|
|
|
if (RetVT == MVT::i128)
|
2008-07-17 10:36:29 +08:00
|
|
|
return FPTOUINT_PPCF128_I128;
|
|
|
|
|
}
|
|
|
|
|
return UNKNOWN_LIBCALL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
|
|
|
|
|
/// UNKNOWN_LIBCALL if there is none.
|
2009-08-11 06:56:29 +08:00
|
|
|
RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
|
2009-08-12 04:47:22 +08:00
|
|
|
if (OpVT == MVT::i32) {
|
|
|
|
|
if (RetVT == MVT::f32)
|
2008-07-17 10:36:29 +08:00
|
|
|
return SINTTOFP_I32_F32;
|
2009-08-12 04:47:22 +08:00
|
|
|
else if (RetVT == MVT::f64)
|
2008-07-17 10:36:29 +08:00
|
|
|
return SINTTOFP_I32_F64;
|
2009-08-12 04:47:22 +08:00
|
|
|
else if (RetVT == MVT::f80)
|
2008-07-17 10:36:29 +08:00
|
|
|
return SINTTOFP_I32_F80;
|
2009-08-12 04:47:22 +08:00
|
|
|
else if (RetVT == MVT::ppcf128)
|
2008-07-17 10:36:29 +08:00
|
|
|
return SINTTOFP_I32_PPCF128;
|
2009-08-12 04:47:22 +08:00
|
|
|
} else if (OpVT == MVT::i64) {
|
|
|
|
|
if (RetVT == MVT::f32)
|
2008-07-17 10:36:29 +08:00
|
|
|
return SINTTOFP_I64_F32;
|
2009-08-12 04:47:22 +08:00
|
|
|
else if (RetVT == MVT::f64)
|
2008-07-17 10:36:29 +08:00
|
|
|
return SINTTOFP_I64_F64;
|
2009-08-12 04:47:22 +08:00
|
|
|
else if (RetVT == MVT::f80)
|
2008-07-17 10:36:29 +08:00
|
|
|
return SINTTOFP_I64_F80;
|
2009-08-12 04:47:22 +08:00
|
|
|
else if (RetVT == MVT::ppcf128)
|
2008-07-17 10:36:29 +08:00
|
|
|
return SINTTOFP_I64_PPCF128;
|
2009-08-12 04:47:22 +08:00
|
|
|
} else if (OpVT == MVT::i128) {
|
|
|
|
|
if (RetVT == MVT::f32)
|
2008-07-17 10:36:29 +08:00
|
|
|
return SINTTOFP_I128_F32;
|
2009-08-12 04:47:22 +08:00
|
|
|
else if (RetVT == MVT::f64)
|
2008-07-17 10:36:29 +08:00
|
|
|
return SINTTOFP_I128_F64;
|
2009-08-12 04:47:22 +08:00
|
|
|
else if (RetVT == MVT::f80)
|
2008-07-17 10:36:29 +08:00
|
|
|
return SINTTOFP_I128_F80;
|
2009-08-12 04:47:22 +08:00
|
|
|
else if (RetVT == MVT::ppcf128)
|
2008-07-17 10:36:29 +08:00
|
|
|
return SINTTOFP_I128_PPCF128;
|
|
|
|
|
}
|
|
|
|
|
return UNKNOWN_LIBCALL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
|
|
|
|
|
/// UNKNOWN_LIBCALL if there is none.
|
2009-08-11 06:56:29 +08:00
|
|
|
RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
|
2009-08-12 04:47:22 +08:00
|
|
|
if (OpVT == MVT::i32) {
|
|
|
|
|
if (RetVT == MVT::f32)
|
2008-07-17 10:36:29 +08:00
|
|
|
return UINTTOFP_I32_F32;
|
2009-08-12 04:47:22 +08:00
|
|
|
else if (RetVT == MVT::f64)
|
2008-07-17 10:36:29 +08:00
|
|
|
return UINTTOFP_I32_F64;
|
2009-08-12 04:47:22 +08:00
|
|
|
else if (RetVT == MVT::f80)
|
2008-07-17 10:36:29 +08:00
|
|
|
return UINTTOFP_I32_F80;
|
2009-08-12 04:47:22 +08:00
|
|
|
else if (RetVT == MVT::ppcf128)
|
2008-07-17 10:36:29 +08:00
|
|
|
return UINTTOFP_I32_PPCF128;
|
2009-08-12 04:47:22 +08:00
|
|
|
} else if (OpVT == MVT::i64) {
|
|
|
|
|
if (RetVT == MVT::f32)
|
2008-07-17 10:36:29 +08:00
|
|
|
return UINTTOFP_I64_F32;
|
2009-08-12 04:47:22 +08:00
|
|
|
else if (RetVT == MVT::f64)
|
2008-07-17 10:36:29 +08:00
|
|
|
return UINTTOFP_I64_F64;
|
2009-08-12 04:47:22 +08:00
|
|
|
else if (RetVT == MVT::f80)
|
2008-07-17 10:36:29 +08:00
|
|
|
return UINTTOFP_I64_F80;
|
2009-08-12 04:47:22 +08:00
|
|
|
else if (RetVT == MVT::ppcf128)
|
2008-07-17 10:36:29 +08:00
|
|
|
return UINTTOFP_I64_PPCF128;
|
2009-08-12 04:47:22 +08:00
|
|
|
} else if (OpVT == MVT::i128) {
|
|
|
|
|
if (RetVT == MVT::f32)
|
2008-07-17 10:36:29 +08:00
|
|
|
return UINTTOFP_I128_F32;
|
2009-08-12 04:47:22 +08:00
|
|
|
else if (RetVT == MVT::f64)
|
2008-07-17 10:36:29 +08:00
|
|
|
return UINTTOFP_I128_F64;
|
2009-08-12 04:47:22 +08:00
|
|
|
else if (RetVT == MVT::f80)
|
2008-07-17 10:36:29 +08:00
|
|
|
return UINTTOFP_I128_F80;
|
2009-08-12 04:47:22 +08:00
|
|
|
else if (RetVT == MVT::ppcf128)
|
2008-07-17 10:36:29 +08:00
|
|
|
return UINTTOFP_I128_PPCF128;
|
|
|
|
|
}
|
|
|
|
|
return UNKNOWN_LIBCALL;
|
|
|
|
|
}
|
|
|
|
|
|
2007-01-31 17:29:11 +08:00
|
|
|
/// InitCmpLibcallCCs - Set default comparison libcall CC.
|
|
|
|
|
///
|
|
|
|
|
static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
|
|
|
|
|
memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
|
|
|
|
|
CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
|
|
|
|
|
CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
|
|
|
|
|
CCs[RTLIB::UNE_F32] = ISD::SETNE;
|
|
|
|
|
CCs[RTLIB::UNE_F64] = ISD::SETNE;
|
|
|
|
|
CCs[RTLIB::OGE_F32] = ISD::SETGE;
|
|
|
|
|
CCs[RTLIB::OGE_F64] = ISD::SETGE;
|
|
|
|
|
CCs[RTLIB::OLT_F32] = ISD::SETLT;
|
|
|
|
|
CCs[RTLIB::OLT_F64] = ISD::SETLT;
|
|
|
|
|
CCs[RTLIB::OLE_F32] = ISD::SETLE;
|
|
|
|
|
CCs[RTLIB::OLE_F64] = ISD::SETLE;
|
|
|
|
|
CCs[RTLIB::OGT_F32] = ISD::SETGT;
|
|
|
|
|
CCs[RTLIB::OGT_F64] = ISD::SETGT;
|
|
|
|
|
CCs[RTLIB::UO_F32] = ISD::SETNE;
|
|
|
|
|
CCs[RTLIB::UO_F64] = ISD::SETNE;
|
|
|
|
|
CCs[RTLIB::O_F32] = ISD::SETEQ;
|
|
|
|
|
CCs[RTLIB::O_F64] = ISD::SETEQ;
|
2007-01-12 10:11:51 +08:00
|
|
|
}
|
|
|
|
|
|
2009-07-28 11:13:23 +08:00
|
|
|
/// NOTE: The constructor takes ownership of TLOF.
|
|
|
|
|
TargetLowering::TargetLowering(TargetMachine &tm,TargetLoweringObjectFile *tlof)
|
|
|
|
|
: TM(tm), TD(TM.getTargetData()), TLOF(*tlof) {
|
2005-01-16 15:28:11 +08:00
|
|
|
// All operations default to being supported.
|
|
|
|
|
memset(OpActions, 0, sizeof(OpActions));
|
2008-10-15 05:26:46 +08:00
|
|
|
memset(LoadExtActions, 0, sizeof(LoadExtActions));
|
2008-01-18 03:59:44 +08:00
|
|
|
memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
|
2008-01-19 03:36:20 +08:00
|
|
|
memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
|
|
|
|
|
memset(ConvertActions, 0, sizeof(ConvertActions));
|
2008-10-15 10:05:31 +08:00
|
|
|
memset(CondCodeActions, 0, sizeof(CondCodeActions));
|
2007-07-10 04:49:44 +08:00
|
|
|
|
2007-12-23 04:47:56 +08:00
|
|
|
// Set default actions for various operations.
|
2009-08-12 04:47:22 +08:00
|
|
|
for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
|
2007-12-23 04:47:56 +08:00
|
|
|
// Default all indexed load / store to expand.
|
2006-11-10 02:56:43 +08:00
|
|
|
for (unsigned IM = (unsigned)ISD::PRE_INC;
|
|
|
|
|
IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
|
2009-08-12 04:47:22 +08:00
|
|
|
setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
|
|
|
|
|
setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
|
2006-11-10 02:56:43 +08:00
|
|
|
}
|
2007-12-23 04:47:56 +08:00
|
|
|
|
|
|
|
|
// These operations default to expand.
|
2009-08-12 04:47:22 +08:00
|
|
|
setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
|
|
|
|
|
setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
|
2006-11-10 02:56:43 +08:00
|
|
|
}
|
2008-03-11 03:38:10 +08:00
|
|
|
|
|
|
|
|
// Most targets ignore the @llvm.prefetch intrinsic.
|
2009-08-12 04:47:22 +08:00
|
|
|
setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
|
2008-02-14 16:57:00 +08:00
|
|
|
|
|
|
|
|
// ConstantFP nodes default to expand. Targets can either change this to
|
2009-10-28 03:56:55 +08:00
|
|
|
// Legal, in which case all fp constants are legal, or use isFPImmLegal()
|
2008-02-14 16:57:00 +08:00
|
|
|
// to optimize expansions for certain constants.
|
2009-08-12 04:47:22 +08:00
|
|
|
setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
|
|
|
|
|
setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
|
|
|
|
|
setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
|
2005-01-07 15:44:53 +08:00
|
|
|
|
2008-09-23 05:57:32 +08:00
|
|
|
// These library functions default to expand.
|
2009-08-12 04:47:22 +08:00
|
|
|
setOperationAction(ISD::FLOG , MVT::f64, Expand);
|
|
|
|
|
setOperationAction(ISD::FLOG2, MVT::f64, Expand);
|
|
|
|
|
setOperationAction(ISD::FLOG10,MVT::f64, Expand);
|
|
|
|
|
setOperationAction(ISD::FEXP , MVT::f64, Expand);
|
|
|
|
|
setOperationAction(ISD::FEXP2, MVT::f64, Expand);
|
|
|
|
|
setOperationAction(ISD::FLOG , MVT::f32, Expand);
|
|
|
|
|
setOperationAction(ISD::FLOG2, MVT::f32, Expand);
|
|
|
|
|
setOperationAction(ISD::FLOG10,MVT::f32, Expand);
|
|
|
|
|
setOperationAction(ISD::FEXP , MVT::f32, Expand);
|
|
|
|
|
setOperationAction(ISD::FEXP2, MVT::f32, Expand);
|
2008-09-23 05:57:32 +08:00
|
|
|
|
2008-01-16 05:58:08 +08:00
|
|
|
// Default ISD::TRAP to expand (which turns it into abort).
|
2009-08-12 04:47:22 +08:00
|
|
|
setOperationAction(ISD::TRAP, MVT::Other, Expand);
|
2008-01-16 05:58:08 +08:00
|
|
|
|
2006-05-03 09:29:57 +08:00
|
|
|
IsLittleEndian = TD->isLittleEndian();
|
2009-08-14 05:58:54 +08:00
|
|
|
ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
|
2009-08-12 04:47:22 +08:00
|
|
|
memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
|
2007-09-07 12:06:50 +08:00
|
|
|
memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
|
2006-02-14 16:38:30 +08:00
|
|
|
maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
|
2009-05-14 05:42:09 +08:00
|
|
|
benefitFromCodePlacementOpt = false;
|
2006-12-11 07:12:42 +08:00
|
|
|
UseUnderscoreSetJmp = false;
|
|
|
|
|
UseUnderscoreLongJmp = false;
|
2007-02-25 09:28:05 +08:00
|
|
|
SelectIsExpensive = false;
|
2005-10-21 08:02:42 +08:00
|
|
|
IntDivIsCheap = false;
|
|
|
|
|
Pow2DivIsCheap = false;
|
2006-01-26 02:57:15 +08:00
|
|
|
StackPointerRegisterToSaveRestore = 0;
|
2007-02-23 02:04:49 +08:00
|
|
|
ExceptionPointerRegister = 0;
|
|
|
|
|
ExceptionSelectorRegister = 0;
|
2008-11-23 23:47:28 +08:00
|
|
|
BooleanContents = UndefinedBooleanContent;
|
2006-01-26 02:52:42 +08:00
|
|
|
SchedPreferenceInfo = SchedulingForLatency;
|
2006-09-06 01:39:15 +08:00
|
|
|
JumpBufSize = 0;
|
2006-09-04 15:44:11 +08:00
|
|
|
JumpBufAlignment = 0;
|
2007-05-17 07:45:53 +08:00
|
|
|
IfCvtBlockSizeLimit = 2;
|
2008-02-28 08:43:03 +08:00
|
|
|
IfCvtDupBlockSizeLimit = 0;
|
|
|
|
|
PrefLoopAlignment = 0;
|
2007-01-12 10:11:51 +08:00
|
|
|
|
|
|
|
|
InitLibcallNames(LibcallRoutineNames);
|
2007-01-31 17:29:11 +08:00
|
|
|
InitCmpLibcallCCs(CmpLibcallCCs);
|
2009-08-15 04:10:52 +08:00
|
|
|
InitLibcallCallingConvs(LibcallCallingConvs);
|
2005-01-07 15:44:53 +08:00
|
|
|
}
|
|
|
|
|
|
2009-07-28 11:13:23 +08:00
|
|
|
TargetLowering::~TargetLowering() {
|
|
|
|
|
delete &TLOF;
|
|
|
|
|
}
|
2005-01-16 15:28:11 +08:00
|
|
|
|
2010-02-11 07:37:45 +08:00
|
|
|
/// canOpTrap - Returns true if the operation can trap for the value type.
|
|
|
|
|
/// VT must be a legal type.
|
|
|
|
|
bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
|
|
|
|
|
assert(isTypeLegal(VT));
|
|
|
|
|
switch (Op) {
|
|
|
|
|
default:
|
|
|
|
|
return false;
|
|
|
|
|
case ISD::FDIV:
|
|
|
|
|
case ISD::FREM:
|
|
|
|
|
case ISD::SDIV:
|
|
|
|
|
case ISD::UDIV:
|
|
|
|
|
case ISD::SREM:
|
|
|
|
|
case ISD::UREM:
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2009-08-12 08:36:31 +08:00
|
|
|
static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
|
|
|
|
|
unsigned &NumIntermediates,
|
|
|
|
|
EVT &RegisterVT,
|
|
|
|
|
TargetLowering* TLI) {
|
|
|
|
|
// Figure out the right, legal destination reg to copy into.
|
|
|
|
|
unsigned NumElts = VT.getVectorNumElements();
|
|
|
|
|
MVT EltTy = VT.getVectorElementType();
|
|
|
|
|
|
|
|
|
|
unsigned NumVectorRegs = 1;
|
|
|
|
|
|
|
|
|
|
// FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
|
|
|
|
|
// could break down into LHS/RHS like LegalizeDAG does.
|
|
|
|
|
if (!isPowerOf2_32(NumElts)) {
|
|
|
|
|
NumVectorRegs = NumElts;
|
|
|
|
|
NumElts = 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Divide the input until we get to a supported size. This will always
|
|
|
|
|
// end with a scalar if the target doesn't support vectors.
|
|
|
|
|
while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
|
|
|
|
|
NumElts >>= 1;
|
|
|
|
|
NumVectorRegs <<= 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
NumIntermediates = NumVectorRegs;
|
|
|
|
|
|
|
|
|
|
MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
|
|
|
|
|
if (!TLI->isTypeLegal(NewVT))
|
|
|
|
|
NewVT = EltTy;
|
|
|
|
|
IntermediateVT = NewVT;
|
|
|
|
|
|
|
|
|
|
EVT DestVT = TLI->getRegisterType(NewVT);
|
|
|
|
|
RegisterVT = DestVT;
|
|
|
|
|
if (EVT(DestVT).bitsLT(NewVT)) {
|
|
|
|
|
// Value is expanded, e.g. i64 -> i16.
|
|
|
|
|
return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
|
|
|
|
|
} else {
|
|
|
|
|
// Otherwise, promotion or legal types use the same number of registers as
|
|
|
|
|
// the vector decimated to the appropriate level.
|
|
|
|
|
return NumVectorRegs;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
|
2005-01-07 15:44:53 +08:00
|
|
|
/// computeRegisterProperties - Once all of the register classes are added,
|
|
|
|
|
/// this allows us to compute derived properties we expose.
|
|
|
|
|
void TargetLowering::computeRegisterProperties() {
|
2009-08-12 04:47:22 +08:00
|
|
|
assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
|
2005-01-16 09:10:58 +08:00
|
|
|
"Too many value types for ValueTypeActions to hold!");
|
|
|
|
|
|
2007-06-29 07:29:44 +08:00
|
|
|
// Everything defaults to needing one register.
|
2009-08-12 04:47:22 +08:00
|
|
|
for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
|
2007-06-21 22:42:22 +08:00
|
|
|
NumRegistersForVT[i] = 1;
|
2009-08-12 04:47:22 +08:00
|
|
|
RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
|
2007-06-29 07:29:44 +08:00
|
|
|
}
|
|
|
|
|
// ...except isVoid, which doesn't need any registers.
|
2009-08-12 04:47:22 +08:00
|
|
|
NumRegistersForVT[MVT::isVoid] = 0;
|
2005-04-22 06:55:34 +08:00
|
|
|
|
2005-01-07 15:44:53 +08:00
|
|
|
// Find the largest integer register class.
|
2009-08-12 04:47:22 +08:00
|
|
|
unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
|
2005-01-07 15:44:53 +08:00
|
|
|
for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
|
2009-08-12 04:47:22 +08:00
|
|
|
assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
|
2005-01-07 15:44:53 +08:00
|
|
|
|
|
|
|
|
// Every integer value type larger than this largest register takes twice as
|
|
|
|
|
// many registers to represent as the previous ValueType.
|
2008-06-06 20:08:01 +08:00
|
|
|
for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
|
2009-09-24 05:02:20 +08:00
|
|
|
EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
|
|
|
|
|
if (!ExpandedVT.isInteger())
|
2008-06-06 20:08:01 +08:00
|
|
|
break;
|
2007-06-21 22:42:22 +08:00
|
|
|
NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
|
2009-08-12 04:47:22 +08:00
|
|
|
RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
|
|
|
|
|
TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
|
2009-09-24 05:02:20 +08:00
|
|
|
ValueTypeActions.setTypeAction(ExpandedVT, Expand);
|
2007-06-29 07:29:44 +08:00
|
|
|
}
|
2005-01-07 15:44:53 +08:00
|
|
|
|
2007-06-29 07:29:44 +08:00
|
|
|
// Inspect all of the ValueType's smaller than the largest integer
|
|
|
|
|
// register to see which ones need promotion.
|
2008-06-06 20:08:01 +08:00
|
|
|
unsigned LegalIntReg = LargestIntReg;
|
|
|
|
|
for (unsigned IntReg = LargestIntReg - 1;
|
2009-08-12 04:47:22 +08:00
|
|
|
IntReg >= (unsigned)MVT::i1; --IntReg) {
|
|
|
|
|
EVT IVT = (MVT::SimpleValueType)IntReg;
|
2008-06-06 20:08:01 +08:00
|
|
|
if (isTypeLegal(IVT)) {
|
2007-06-29 07:29:44 +08:00
|
|
|
LegalIntReg = IntReg;
|
|
|
|
|
} else {
|
2008-06-06 20:08:01 +08:00
|
|
|
RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
|
2009-08-12 04:47:22 +08:00
|
|
|
(MVT::SimpleValueType)LegalIntReg;
|
2008-06-06 20:08:01 +08:00
|
|
|
ValueTypeActions.setTypeAction(IVT, Promote);
|
2007-06-29 07:29:44 +08:00
|
|
|
}
|
|
|
|
|
}
|
2005-04-22 06:55:34 +08:00
|
|
|
|
2007-10-06 04:04:43 +08:00
|
|
|
// ppcf128 type is really two f64's.
|
2009-08-12 04:47:22 +08:00
|
|
|
if (!isTypeLegal(MVT::ppcf128)) {
|
|
|
|
|
NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
|
|
|
|
|
RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
|
|
|
|
|
TransformToType[MVT::ppcf128] = MVT::f64;
|
|
|
|
|
ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
|
2007-10-06 04:04:43 +08:00
|
|
|
}
|
|
|
|
|
|
2007-06-29 07:29:44 +08:00
|
|
|
// Decide how to handle f64. If the target does not have native f64 support,
|
|
|
|
|
// expand it to i64 and we will be generating soft float library calls.
|
2009-08-12 04:47:22 +08:00
|
|
|
if (!isTypeLegal(MVT::f64)) {
|
|
|
|
|
NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
|
|
|
|
|
RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
|
|
|
|
|
TransformToType[MVT::f64] = MVT::i64;
|
|
|
|
|
ValueTypeActions.setTypeAction(MVT::f64, Expand);
|
2006-12-09 10:42:38 +08:00
|
|
|
}
|
2007-06-29 07:29:44 +08:00
|
|
|
|
|
|
|
|
// Decide how to handle f32. If the target does not have native support for
|
|
|
|
|
// f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
|
2009-08-12 04:47:22 +08:00
|
|
|
if (!isTypeLegal(MVT::f32)) {
|
|
|
|
|
if (isTypeLegal(MVT::f64)) {
|
|
|
|
|
NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
|
|
|
|
|
RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
|
|
|
|
|
TransformToType[MVT::f32] = MVT::f64;
|
|
|
|
|
ValueTypeActions.setTypeAction(MVT::f32, Promote);
|
2007-06-29 07:29:44 +08:00
|
|
|
} else {
|
2009-08-12 04:47:22 +08:00
|
|
|
NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
|
|
|
|
|
RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
|
|
|
|
|
TransformToType[MVT::f32] = MVT::i32;
|
|
|
|
|
ValueTypeActions.setTypeAction(MVT::f32, Expand);
|
2007-06-29 07:29:44 +08:00
|
|
|
}
|
2006-12-09 10:42:38 +08:00
|
|
|
}
|
2005-11-22 09:29:36 +08:00
|
|
|
|
2007-06-29 07:29:44 +08:00
|
|
|
// Loop over all of the vector value types to see which need transformations.
|
2009-08-12 04:47:22 +08:00
|
|
|
for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
|
|
|
|
|
i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
|
2009-08-12 08:36:31 +08:00
|
|
|
MVT VT = (MVT::SimpleValueType)i;
|
2008-06-06 20:08:01 +08:00
|
|
|
if (!isTypeLegal(VT)) {
|
2009-08-12 08:36:31 +08:00
|
|
|
MVT IntermediateVT;
|
|
|
|
|
EVT RegisterVT;
|
2007-06-29 07:29:44 +08:00
|
|
|
unsigned NumIntermediates;
|
|
|
|
|
NumRegistersForVT[i] =
|
2009-08-12 08:36:31 +08:00
|
|
|
getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
|
|
|
|
|
RegisterVT, this);
|
2007-06-29 07:29:44 +08:00
|
|
|
RegisterTypeForVT[i] = RegisterVT;
|
2008-12-19 04:03:17 +08:00
|
|
|
|
|
|
|
|
// Determine if there is a legal wider type.
|
|
|
|
|
bool IsLegalWiderType = false;
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT EltVT = VT.getVectorElementType();
|
2008-12-19 04:03:17 +08:00
|
|
|
unsigned NElts = VT.getVectorNumElements();
|
2009-08-12 04:47:22 +08:00
|
|
|
for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
|
|
|
|
|
EVT SVT = (MVT::SimpleValueType)nVT;
|
2008-12-19 04:03:17 +08:00
|
|
|
if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT &&
|
2010-01-24 08:24:43 +08:00
|
|
|
SVT.getVectorNumElements() > NElts && NElts != 1) {
|
2008-12-19 04:03:17 +08:00
|
|
|
TransformToType[i] = SVT;
|
|
|
|
|
ValueTypeActions.setTypeAction(VT, Promote);
|
|
|
|
|
IsLegalWiderType = true;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (!IsLegalWiderType) {
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT NVT = VT.getPow2VectorType();
|
2008-12-19 04:03:17 +08:00
|
|
|
if (NVT == VT) {
|
|
|
|
|
// Type is already a power of 2. The default action is to split.
|
2009-08-12 04:47:22 +08:00
|
|
|
TransformToType[i] = MVT::Other;
|
2008-12-19 04:03:17 +08:00
|
|
|
ValueTypeActions.setTypeAction(VT, Expand);
|
|
|
|
|
} else {
|
|
|
|
|
TransformToType[i] = NVT;
|
|
|
|
|
ValueTypeActions.setTypeAction(VT, Promote);
|
|
|
|
|
}
|
|
|
|
|
}
|
2007-06-26 00:23:39 +08:00
|
|
|
}
|
2006-03-17 03:50:01 +08:00
|
|
|
}
|
2005-01-16 09:10:58 +08:00
|
|
|
}
|
2005-01-16 15:28:11 +08:00
|
|
|
|
2005-12-20 14:22:03 +08:00
|
|
|
const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
2005-12-22 07:05:39 +08:00
|
|
|
|
2008-03-10 23:42:14 +08:00
|
|
|
|
2009-08-12 04:47:22 +08:00
|
|
|
MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
|
2009-08-14 05:58:54 +08:00
|
|
|
return PointerTy.SimpleTy;
|
2008-03-10 23:42:14 +08:00
|
|
|
}
|
|
|
|
|
|
2009-12-28 10:40:33 +08:00
|
|
|
MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
|
|
|
|
|
return MVT::i32; // return the default value
|
|
|
|
|
}
|
|
|
|
|
|
2007-06-26 00:23:39 +08:00
|
|
|
/// getVectorTypeBreakdown - Vector types are broken down into some number of
|
2009-08-12 04:47:22 +08:00
|
|
|
/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
|
|
|
|
|
/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
|
|
|
|
|
/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
|
2006-03-31 08:28:56 +08:00
|
|
|
///
|
2007-06-26 00:23:39 +08:00
|
|
|
/// This method returns the number of registers needed, and the VT for each
|
2007-06-29 07:29:44 +08:00
|
|
|
/// register. It also returns the VT and quantity of the intermediate values
|
|
|
|
|
/// before they are promoted/expanded.
|
2006-03-31 08:28:56 +08:00
|
|
|
///
|
2009-08-12 08:36:31 +08:00
|
|
|
unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT &IntermediateVT,
|
2007-06-29 07:29:44 +08:00
|
|
|
unsigned &NumIntermediates,
|
2009-08-12 08:36:31 +08:00
|
|
|
EVT &RegisterVT) const {
|
2006-03-31 08:28:56 +08:00
|
|
|
// Figure out the right, legal destination reg to copy into.
|
2008-06-06 20:08:01 +08:00
|
|
|
unsigned NumElts = VT.getVectorNumElements();
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT EltTy = VT.getVectorElementType();
|
2006-03-31 08:28:56 +08:00
|
|
|
|
|
|
|
|
unsigned NumVectorRegs = 1;
|
|
|
|
|
|
2007-11-28 03:28:48 +08:00
|
|
|
// FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
|
|
|
|
|
// could break down into LHS/RHS like LegalizeDAG does.
|
|
|
|
|
if (!isPowerOf2_32(NumElts)) {
|
|
|
|
|
NumVectorRegs = NumElts;
|
|
|
|
|
NumElts = 1;
|
|
|
|
|
}
|
|
|
|
|
|
2006-03-31 08:28:56 +08:00
|
|
|
// Divide the input until we get to a supported size. This will always
|
|
|
|
|
// end with a scalar if the target doesn't support vectors.
|
2009-08-12 08:36:31 +08:00
|
|
|
while (NumElts > 1 && !isTypeLegal(
|
|
|
|
|
EVT::getVectorVT(Context, EltTy, NumElts))) {
|
2006-03-31 08:28:56 +08:00
|
|
|
NumElts >>= 1;
|
|
|
|
|
NumVectorRegs <<= 1;
|
|
|
|
|
}
|
2007-06-29 07:29:44 +08:00
|
|
|
|
|
|
|
|
NumIntermediates = NumVectorRegs;
|
2006-03-31 08:28:56 +08:00
|
|
|
|
2009-08-12 08:36:31 +08:00
|
|
|
EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
|
2007-06-26 00:23:39 +08:00
|
|
|
if (!isTypeLegal(NewVT))
|
|
|
|
|
NewVT = EltTy;
|
2007-06-29 07:29:44 +08:00
|
|
|
IntermediateVT = NewVT;
|
2006-03-31 08:28:56 +08:00
|
|
|
|
2009-08-12 08:36:31 +08:00
|
|
|
EVT DestVT = getRegisterType(Context, NewVT);
|
2007-06-29 07:29:44 +08:00
|
|
|
RegisterVT = DestVT;
|
2008-06-09 04:54:56 +08:00
|
|
|
if (DestVT.bitsLT(NewVT)) {
|
2006-03-31 08:28:56 +08:00
|
|
|
// Value is expanded, e.g. i64 -> i16.
|
2008-06-06 20:08:01 +08:00
|
|
|
return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
|
2006-03-31 08:28:56 +08:00
|
|
|
} else {
|
|
|
|
|
// Otherwise, promotion or legal types use the same number of registers as
|
|
|
|
|
// the vector decimated to the appropriate level.
|
2006-03-31 08:46:36 +08:00
|
|
|
return NumVectorRegs;
|
2006-03-31 08:28:56 +08:00
|
|
|
}
|
|
|
|
|
|
2006-05-18 02:10:06 +08:00
|
|
|
return 1;
|
2006-03-31 08:28:56 +08:00
|
|
|
}
|
|
|
|
|
|
2008-10-30 16:01:45 +08:00
|
|
|
/// getWidenVectorType: given a vector type, returns the type to widen to
|
|
|
|
|
/// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
|
2009-08-12 04:47:22 +08:00
|
|
|
/// If there is no vector type that we want to widen to, returns MVT::Other
|
2008-11-06 13:31:54 +08:00
|
|
|
/// When and where to widen is target dependent based on the cost of
|
2008-10-30 16:01:45 +08:00
|
|
|
/// scalarizing vs using the wider vector type.
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT TargetLowering::getWidenVectorType(EVT VT) const {
|
2008-10-30 16:01:45 +08:00
|
|
|
assert(VT.isVector());
|
|
|
|
|
if (isTypeLegal(VT))
|
|
|
|
|
return VT;
|
|
|
|
|
|
|
|
|
|
// Default is not to widen until moved to LegalizeTypes
|
2009-08-12 04:47:22 +08:00
|
|
|
return MVT::Other;
|
2008-10-30 16:01:45 +08:00
|
|
|
}
|
|
|
|
|
|
2008-01-24 08:22:01 +08:00
|
|
|
/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
|
2008-02-29 06:31:51 +08:00
|
|
|
/// function arguments in the caller parameter area. This is the actual
|
|
|
|
|
/// alignment, not its logarithm.
|
2008-01-24 08:22:01 +08:00
|
|
|
unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
|
2008-02-29 06:31:51 +08:00
|
|
|
return TD->getCallFrameTypeAlignment(Ty);
|
2008-01-24 08:22:01 +08:00
|
|
|
}
|
|
|
|
|
|
2010-01-26 07:26:13 +08:00
|
|
|
/// getJumpTableEncoding - Return the entry encoding for a jump table in the
|
|
|
|
|
/// current function. The returned value is a member of the
|
|
|
|
|
/// MachineJumpTableInfo::JTEntryKind enum.
|
|
|
|
|
unsigned TargetLowering::getJumpTableEncoding() const {
|
|
|
|
|
// In non-pic modes, just use the address of a block.
|
|
|
|
|
if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
|
|
|
|
|
return MachineJumpTableInfo::EK_BlockAddress;
|
|
|
|
|
|
|
|
|
|
// In PIC mode, if the target supports a GPRel32 directive, use it.
|
|
|
|
|
if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
|
|
|
|
|
return MachineJumpTableInfo::EK_GPRel32BlockAddress;
|
|
|
|
|
|
|
|
|
|
// Otherwise, use a label difference.
|
|
|
|
|
return MachineJumpTableInfo::EK_LabelDifference32;
|
|
|
|
|
}
|
|
|
|
|
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
|
|
|
|
|
SelectionDAG &DAG) const {
|
2010-01-26 14:53:37 +08:00
|
|
|
// If our PIC model is GP relative, use the global offset table as the base.
|
|
|
|
|
if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress)
|
2009-02-07 08:55:49 +08:00
|
|
|
return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
|
Much improved pic jumptable codegen:
Then:
call "L1$pb"
"L1$pb":
popl %eax
...
LBB1_1: # entry
imull $4, %ecx, %ecx
leal LJTI1_0-"L1$pb"(%eax), %edx
addl LJTI1_0-"L1$pb"(%ecx,%eax), %edx
jmpl *%edx
.align 2
.set L1_0_set_3,LBB1_3-LJTI1_0
.set L1_0_set_2,LBB1_2-LJTI1_0
.set L1_0_set_5,LBB1_5-LJTI1_0
.set L1_0_set_4,LBB1_4-LJTI1_0
LJTI1_0:
.long L1_0_set_3
.long L1_0_set_2
Now:
call "L1$pb"
"L1$pb":
popl %eax
...
LBB1_1: # entry
addl LJTI1_0-"L1$pb"(%eax,%ecx,4), %eax
jmpl *%eax
.align 2
.set L1_0_set_3,LBB1_3-"L1$pb"
.set L1_0_set_2,LBB1_2-"L1$pb"
.set L1_0_set_5,LBB1_5-"L1$pb"
.set L1_0_set_4,LBB1_4-"L1$pb"
LJTI1_0:
.long L1_0_set_3
.long L1_0_set_2
llvm-svn: 43924
2007-11-09 09:32:10 +08:00
|
|
|
return Table;
|
|
|
|
|
}
|
|
|
|
|
|
2010-01-26 13:30:30 +08:00
|
|
|
/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
|
|
|
|
|
/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
|
|
|
|
|
/// MCExpr.
|
|
|
|
|
const MCExpr *
|
2010-01-26 14:28:43 +08:00
|
|
|
TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
|
|
|
|
|
unsigned JTI,MCContext &Ctx) const{
|
2010-01-26 13:58:28 +08:00
|
|
|
// The normal PIC reloc base is the label at the start of the jump table.
|
2010-01-26 14:28:43 +08:00
|
|
|
return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
|
2010-01-26 13:30:30 +08:00
|
|
|
}
|
|
|
|
|
|
Teach DAGCombine to fold constant offsets into GlobalAddress nodes,
and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)
This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.
This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.
Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.
The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.
llvm-svn: 57748
2008-10-18 10:06:02 +08:00
|
|
|
bool
|
|
|
|
|
TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
|
|
|
|
|
// Assume that everything is safe in static mode.
|
|
|
|
|
if (getTargetMachine().getRelocationModel() == Reloc::Static)
|
|
|
|
|
return true;
|
|
|
|
|
|
|
|
|
|
// In dynamic-no-pic mode, assume that known defined values are safe.
|
|
|
|
|
if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
|
|
|
|
|
GA &&
|
|
|
|
|
!GA->getGlobal()->isDeclaration() &&
|
Introduce new linkage types linkonce_odr, weak_odr, common_odr
and extern_weak_odr. These are the same as the non-odr versions,
except that they indicate that the global will only be overridden
by an *equivalent* global. In C, a function with weak linkage can
be overridden by a function which behaves completely differently.
This means that IP passes have to skip weak functions, since any
deductions made from the function definition might be wrong, since
the definition could be replaced by something completely different
at link time. This is not allowed in C++, thanks to the ODR
(One-Definition-Rule): if a function is replaced by another at
link-time, then the new function must be the same as the original
function. If a language knows that a function or other global can
only be overridden by an equivalent global, it can give it the
weak_odr linkage type, and the optimizers will understand that it
is alright to make deductions based on the function body. The
code generators on the other hand map weak and weak_odr linkage
to the same thing.
llvm-svn: 66339
2009-03-07 23:45:40 +08:00
|
|
|
!GA->getGlobal()->isWeakForLinker())
|
Teach DAGCombine to fold constant offsets into GlobalAddress nodes,
and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)
This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.
This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.
Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.
The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.
llvm-svn: 57748
2008-10-18 10:06:02 +08:00
|
|
|
return true;
|
|
|
|
|
|
|
|
|
|
// Otherwise assume nothing is safe.
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
2006-02-04 10:13:02 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// Optimization Methods
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
2006-02-17 05:11:51 +08:00
|
|
|
/// ShrinkDemandedConstant - Check to see if the specified operand of the
|
|
|
|
|
/// specified instruction is a constant integer. If so, check to see if there
|
|
|
|
|
/// are any bits set in the constant that are not demanded. If so, shrink the
|
|
|
|
|
/// constant and return true.
|
2008-07-28 05:46:04 +08:00
|
|
|
bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
|
2008-02-27 08:25:32 +08:00
|
|
|
const APInt &Demanded) {
|
2009-02-07 05:50:26 +08:00
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
2009-03-04 08:18:06 +08:00
|
|
|
|
2006-02-27 07:36:02 +08:00
|
|
|
// FIXME: ISD::SELECT, ISD::SELECT_CC
|
2009-01-29 09:59:02 +08:00
|
|
|
switch (Op.getOpcode()) {
|
2006-02-17 05:11:51 +08:00
|
|
|
default: break;
|
|
|
|
|
case ISD::XOR:
|
2009-03-04 08:18:06 +08:00
|
|
|
case ISD::AND:
|
|
|
|
|
case ISD::OR: {
|
|
|
|
|
ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
|
|
|
|
|
if (!C) return false;
|
|
|
|
|
|
|
|
|
|
if (Op.getOpcode() == ISD::XOR &&
|
|
|
|
|
(C->getAPIntValue() | (~Demanded)).isAllOnesValue())
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
// if we can expand it to have all bits set, do it
|
|
|
|
|
if (C->getAPIntValue().intersects(~Demanded)) {
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT VT = Op.getValueType();
|
2009-03-04 08:18:06 +08:00
|
|
|
SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
|
|
|
|
|
DAG.getConstant(Demanded &
|
|
|
|
|
C->getAPIntValue(),
|
|
|
|
|
VT));
|
|
|
|
|
return CombineTo(Op, New);
|
|
|
|
|
}
|
|
|
|
|
|
2006-02-17 05:11:51 +08:00
|
|
|
break;
|
|
|
|
|
}
|
2009-03-04 08:18:06 +08:00
|
|
|
}
|
|
|
|
|
|
2006-02-17 05:11:51 +08:00
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
Implement support for using modeling implicit-zero-extension on x86-64
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.
This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.
Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.
Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.
Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.
Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.
llvm-svn: 68576
2009-04-08 08:15:30 +08:00
|
|
|
/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
|
|
|
|
|
/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
|
|
|
|
|
/// cast, but it could be generalized for targets with other types of
|
|
|
|
|
/// implicit widening casts.
|
|
|
|
|
bool
|
|
|
|
|
TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
|
|
|
|
|
unsigned BitWidth,
|
|
|
|
|
const APInt &Demanded,
|
|
|
|
|
DebugLoc dl) {
|
|
|
|
|
assert(Op.getNumOperands() == 2 &&
|
|
|
|
|
"ShrinkDemandedOp only supports binary operators!");
|
|
|
|
|
assert(Op.getNode()->getNumValues() == 1 &&
|
|
|
|
|
"ShrinkDemandedOp only supports nodes with one result!");
|
|
|
|
|
|
|
|
|
|
// Don't do this if the node has another user, which may require the
|
|
|
|
|
// full value.
|
|
|
|
|
if (!Op.getNode()->hasOneUse())
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
// Search for the smallest integer type with free casts to and from
|
|
|
|
|
// Op's type. For expedience, just check power-of-2 integer types.
|
|
|
|
|
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
|
|
|
|
|
unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
|
|
|
|
|
if (!isPowerOf2_32(SmallVTBits))
|
|
|
|
|
SmallVTBits = NextPowerOf2(SmallVTBits);
|
|
|
|
|
for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
|
2009-08-12 08:36:31 +08:00
|
|
|
EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
|
Implement support for using modeling implicit-zero-extension on x86-64
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.
This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.
Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.
Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.
Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.
Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.
llvm-svn: 68576
2009-04-08 08:15:30 +08:00
|
|
|
if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
|
|
|
|
|
TLI.isZExtFree(SmallVT, Op.getValueType())) {
|
|
|
|
|
// We found a type with free casts.
|
|
|
|
|
SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
|
|
|
|
|
DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
|
|
|
|
|
Op.getNode()->getOperand(0)),
|
|
|
|
|
DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
|
|
|
|
|
Op.getNode()->getOperand(1)));
|
|
|
|
|
SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
|
|
|
|
|
return CombineTo(Op, Z);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
2006-02-17 05:11:51 +08:00
|
|
|
/// SimplifyDemandedBits - Look at Op. At this point, we know that only the
|
|
|
|
|
/// DemandedMask bits of the result of Op are ever used downstream. If we can
|
|
|
|
|
/// use this information to simplify Op, create a new simplified DAG node and
|
|
|
|
|
/// return true, returning the original and new nodes in Old and New. Otherwise,
|
|
|
|
|
/// analyze the expression and return a mask of KnownOne and KnownZero bits for
|
|
|
|
|
/// the expression (used to simplify the caller). The KnownZero/One bits may
|
|
|
|
|
/// only be accurate for those bits in the DemandedMask.
|
2008-07-28 05:46:04 +08:00
|
|
|
bool TargetLowering::SimplifyDemandedBits(SDValue Op,
|
2008-02-27 08:25:32 +08:00
|
|
|
const APInt &DemandedMask,
|
|
|
|
|
APInt &KnownZero,
|
|
|
|
|
APInt &KnownOne,
|
2006-02-17 05:11:51 +08:00
|
|
|
TargetLoweringOpt &TLO,
|
|
|
|
|
unsigned Depth) const {
|
2008-02-27 08:25:32 +08:00
|
|
|
unsigned BitWidth = DemandedMask.getBitWidth();
|
2009-12-12 05:31:27 +08:00
|
|
|
assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
|
2008-02-27 08:25:32 +08:00
|
|
|
"Mask size mismatches value type size!");
|
|
|
|
|
APInt NewMask = DemandedMask;
|
2009-02-08 03:59:05 +08:00
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
2008-02-27 08:25:32 +08:00
|
|
|
|
|
|
|
|
// Don't know anything.
|
|
|
|
|
KnownZero = KnownOne = APInt(BitWidth, 0);
|
2007-05-18 02:19:23 +08:00
|
|
|
|
2006-02-17 05:11:51 +08:00
|
|
|
// Other users may use these bits.
|
2008-08-29 05:40:38 +08:00
|
|
|
if (!Op.getNode()->hasOneUse()) {
|
2006-02-17 05:11:51 +08:00
|
|
|
if (Depth != 0) {
|
|
|
|
|
// If not at the root, Just compute the KnownZero/KnownOne bits to
|
|
|
|
|
// simplify things downstream.
|
2007-06-22 22:59:07 +08:00
|
|
|
TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
|
2006-02-17 05:11:51 +08:00
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
// If this is the root being simplified, allow it to have multiple uses,
|
2008-02-27 08:25:32 +08:00
|
|
|
// just set the NewMask to all bits.
|
|
|
|
|
NewMask = APInt::getAllOnesValue(BitWidth);
|
2006-02-17 05:11:51 +08:00
|
|
|
} else if (DemandedMask == 0) {
|
|
|
|
|
// Not demanding any bits from Op.
|
|
|
|
|
if (Op.getOpcode() != ISD::UNDEF)
|
2009-02-07 07:05:02 +08:00
|
|
|
return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
|
2006-02-04 06:24:05 +08:00
|
|
|
return false;
|
2006-02-17 05:11:51 +08:00
|
|
|
} else if (Depth == 6) { // Limit search depth.
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
2008-02-27 08:25:32 +08:00
|
|
|
APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
|
2006-02-04 06:24:05 +08:00
|
|
|
switch (Op.getOpcode()) {
|
2006-02-17 05:11:51 +08:00
|
|
|
case ISD::Constant:
|
|
|
|
|
// We know all of the bits for a constant!
|
2008-02-27 08:25:32 +08:00
|
|
|
KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
|
|
|
|
|
KnownZero = ~KnownOne & NewMask;
|
2006-02-27 07:36:02 +08:00
|
|
|
return false; // Don't fall through, will infinitely loop.
|
2006-02-04 06:24:05 +08:00
|
|
|
case ISD::AND:
|
2006-02-27 08:36:27 +08:00
|
|
|
// If the RHS is a constant, check to see if the LHS would be zero without
|
|
|
|
|
// using the bits from the RHS. Below, we use knowledge about the RHS to
|
|
|
|
|
// simplify the LHS, here we're using information from the LHS to simplify
|
|
|
|
|
// the RHS.
|
|
|
|
|
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
|
2008-02-27 08:25:32 +08:00
|
|
|
APInt LHSZero, LHSOne;
|
|
|
|
|
TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
|
2007-06-22 22:59:07 +08:00
|
|
|
LHSZero, LHSOne, Depth+1);
|
2006-02-27 08:36:27 +08:00
|
|
|
// If the LHS already has zeros where RHSC does, this and is dead.
|
2008-02-27 08:25:32 +08:00
|
|
|
if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
|
2006-02-27 08:36:27 +08:00
|
|
|
return TLO.CombineTo(Op, Op.getOperand(0));
|
|
|
|
|
// If any of the set bits in the RHS are known zero on the LHS, shrink
|
|
|
|
|
// the constant.
|
2008-02-27 08:25:32 +08:00
|
|
|
if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
|
2006-02-27 08:36:27 +08:00
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
2008-02-27 08:25:32 +08:00
|
|
|
if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
|
2006-02-17 05:11:51 +08:00
|
|
|
KnownOne, TLO, Depth+1))
|
|
|
|
|
return true;
|
|
|
|
|
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
2008-02-27 08:25:32 +08:00
|
|
|
if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
|
2006-02-17 05:11:51 +08:00
|
|
|
KnownZero2, KnownOne2, TLO, Depth+1))
|
|
|
|
|
return true;
|
|
|
|
|
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
|
|
|
|
|
|
|
|
|
|
// If all of the demanded bits are known one on one side, return the other.
|
|
|
|
|
// These bits cannot contribute to the result of the 'and'.
|
2008-02-27 08:25:32 +08:00
|
|
|
if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
|
2006-02-17 05:11:51 +08:00
|
|
|
return TLO.CombineTo(Op, Op.getOperand(0));
|
2008-02-27 08:25:32 +08:00
|
|
|
if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
|
2006-02-17 05:11:51 +08:00
|
|
|
return TLO.CombineTo(Op, Op.getOperand(1));
|
|
|
|
|
// If all of the demanded bits in the inputs are known zeros, return zero.
|
2008-02-27 08:25:32 +08:00
|
|
|
if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
|
2006-02-17 05:11:51 +08:00
|
|
|
return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
|
|
|
|
|
// If the RHS is a constant, see if we can simplify it.
|
2008-02-27 08:25:32 +08:00
|
|
|
if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
|
2006-02-17 05:11:51 +08:00
|
|
|
return true;
|
Implement support for using modeling implicit-zero-extension on x86-64
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.
This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.
Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.
Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.
Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.
Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.
llvm-svn: 68576
2009-04-08 08:15:30 +08:00
|
|
|
// If the operation can be done in a smaller type, do so.
|
2010-01-07 03:38:29 +08:00
|
|
|
if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
|
Implement support for using modeling implicit-zero-extension on x86-64
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.
This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.
Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.
Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.
Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.
Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.
llvm-svn: 68576
2009-04-08 08:15:30 +08:00
|
|
|
return true;
|
|
|
|
|
|
2006-02-17 05:11:51 +08:00
|
|
|
// Output known-1 bits are only known if set in both the LHS & RHS.
|
|
|
|
|
KnownOne &= KnownOne2;
|
|
|
|
|
// Output known-0 are known to be clear if zero in either the LHS | RHS.
|
|
|
|
|
KnownZero |= KnownZero2;
|
|
|
|
|
break;
|
|
|
|
|
case ISD::OR:
|
2008-02-27 08:25:32 +08:00
|
|
|
if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
|
2006-02-17 05:11:51 +08:00
|
|
|
KnownOne, TLO, Depth+1))
|
|
|
|
|
return true;
|
|
|
|
|
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
2008-02-27 08:25:32 +08:00
|
|
|
if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
|
2006-02-17 05:11:51 +08:00
|
|
|
KnownZero2, KnownOne2, TLO, Depth+1))
|
|
|
|
|
return true;
|
|
|
|
|
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
|
|
|
|
|
|
|
|
|
|
// If all of the demanded bits are known zero on one side, return the other.
|
|
|
|
|
// These bits cannot contribute to the result of the 'or'.
|
2008-02-27 08:25:32 +08:00
|
|
|
if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
|
2006-02-17 05:11:51 +08:00
|
|
|
return TLO.CombineTo(Op, Op.getOperand(0));
|
2008-02-27 08:25:32 +08:00
|
|
|
if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
|
2006-02-17 05:11:51 +08:00
|
|
|
return TLO.CombineTo(Op, Op.getOperand(1));
|
|
|
|
|
// If all of the potentially set bits on one side are known to be set on
|
|
|
|
|
// the other side, just use the 'other' side.
|
2008-02-27 08:25:32 +08:00
|
|
|
if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
|
2006-02-17 05:11:51 +08:00
|
|
|
return TLO.CombineTo(Op, Op.getOperand(0));
|
2008-02-27 08:25:32 +08:00
|
|
|
if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
|
2006-02-17 05:11:51 +08:00
|
|
|
return TLO.CombineTo(Op, Op.getOperand(1));
|
|
|
|
|
// If the RHS is a constant, see if we can simplify it.
|
2008-02-27 08:25:32 +08:00
|
|
|
if (TLO.ShrinkDemandedConstant(Op, NewMask))
|
2006-02-17 05:11:51 +08:00
|
|
|
return true;
|
Implement support for using modeling implicit-zero-extension on x86-64
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.
This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.
Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.
Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.
Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.
Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.
llvm-svn: 68576
2009-04-08 08:15:30 +08:00
|
|
|
// If the operation can be done in a smaller type, do so.
|
2010-01-07 03:38:29 +08:00
|
|
|
if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
|
Implement support for using modeling implicit-zero-extension on x86-64
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.
This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.
Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.
Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.
Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.
Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.
llvm-svn: 68576
2009-04-08 08:15:30 +08:00
|
|
|
return true;
|
|
|
|
|
|
2006-02-17 05:11:51 +08:00
|
|
|
// Output known-0 bits are only known if clear in both the LHS & RHS.
|
|
|
|
|
KnownZero &= KnownZero2;
|
|
|
|
|
// Output known-1 are known to be set if set in either the LHS | RHS.
|
|
|
|
|
KnownOne |= KnownOne2;
|
|
|
|
|
break;
|
|
|
|
|
case ISD::XOR:
|
2008-02-27 08:25:32 +08:00
|
|
|
if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
|
2006-02-17 05:11:51 +08:00
|
|
|
KnownOne, TLO, Depth+1))
|
|
|
|
|
return true;
|
|
|
|
|
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
2008-02-27 08:25:32 +08:00
|
|
|
if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
|
2006-02-17 05:11:51 +08:00
|
|
|
KnownOne2, TLO, Depth+1))
|
|
|
|
|
return true;
|
|
|
|
|
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
|
|
|
|
|
|
|
|
|
|
// If all of the demanded bits are known zero on one side, return the other.
|
|
|
|
|
// These bits cannot contribute to the result of the 'xor'.
|
2008-02-27 08:25:32 +08:00
|
|
|
if ((KnownZero & NewMask) == NewMask)
|
2006-02-17 05:11:51 +08:00
|
|
|
return TLO.CombineTo(Op, Op.getOperand(0));
|
2008-02-27 08:25:32 +08:00
|
|
|
if ((KnownZero2 & NewMask) == NewMask)
|
2006-02-17 05:11:51 +08:00
|
|
|
return TLO.CombineTo(Op, Op.getOperand(1));
|
Implement support for using modeling implicit-zero-extension on x86-64
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.
This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.
Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.
Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.
Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.
Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.
llvm-svn: 68576
2009-04-08 08:15:30 +08:00
|
|
|
// If the operation can be done in a smaller type, do so.
|
2010-01-07 03:38:29 +08:00
|
|
|
if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
|
Implement support for using modeling implicit-zero-extension on x86-64
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.
This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.
Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.
Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.
Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.
Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.
llvm-svn: 68576
2009-04-08 08:15:30 +08:00
|
|
|
return true;
|
|
|
|
|
|
2006-11-28 05:50:02 +08:00
|
|
|
// If all of the unknown bits are known to be zero on one side or the other
|
|
|
|
|
// (but not both) turn this into an *inclusive* or.
|
|
|
|
|
// e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
|
2008-02-27 08:25:32 +08:00
|
|
|
if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
|
2009-02-07 05:50:26 +08:00
|
|
|
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
|
2006-11-28 05:50:02 +08:00
|
|
|
Op.getOperand(0),
|
|
|
|
|
Op.getOperand(1)));
|
2006-02-17 05:11:51 +08:00
|
|
|
|
|
|
|
|
// Output known-0 bits are known if clear or set in both the LHS & RHS.
|
|
|
|
|
KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
|
|
|
|
|
// Output known-1 are known to be set if set in only one of the LHS, RHS.
|
|
|
|
|
KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
|
|
|
|
|
|
|
|
|
|
// If all of the demanded bits on one side are known, and all of the set
|
|
|
|
|
// bits on that side are also known to be set on the other side, turn this
|
|
|
|
|
// into an AND, as we know the bits will be cleared.
|
|
|
|
|
// e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
|
2008-02-27 08:25:32 +08:00
|
|
|
if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
|
2006-02-17 05:11:51 +08:00
|
|
|
if ((KnownOne & KnownOne2) == KnownOne) {
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT VT = Op.getValueType();
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
|
2009-02-03 08:47:48 +08:00
|
|
|
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
|
|
|
|
|
Op.getOperand(0), ANDC));
|
2006-02-17 05:11:51 +08:00
|
|
|
}
|
2006-02-04 06:24:05 +08:00
|
|
|
}
|
2006-02-17 05:11:51 +08:00
|
|
|
|
|
|
|
|
// If the RHS is a constant, see if we can simplify it.
|
2008-04-07 05:23:02 +08:00
|
|
|
// for XOR, we prefer to force bits to 1 if they will make a -1.
|
|
|
|
|
// if we can't force bits, try to shrink constant
|
|
|
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
|
|
|
|
|
APInt Expanded = C->getAPIntValue() | (~NewMask);
|
|
|
|
|
// if we can expand it to have all bits set, do it
|
|
|
|
|
if (Expanded.isAllOnesValue()) {
|
|
|
|
|
if (Expanded != C->getAPIntValue()) {
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT VT = Op.getValueType();
|
2009-02-03 08:47:48 +08:00
|
|
|
SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
|
2008-04-07 05:23:02 +08:00
|
|
|
TLO.DAG.getConstant(Expanded, VT));
|
|
|
|
|
return TLO.CombineTo(Op, New);
|
|
|
|
|
}
|
|
|
|
|
// if it already has all the bits set, nothing to change
|
|
|
|
|
// but don't shrink either!
|
|
|
|
|
} else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2006-02-17 05:11:51 +08:00
|
|
|
KnownZero = KnownZeroOut;
|
|
|
|
|
KnownOne = KnownOneOut;
|
|
|
|
|
break;
|
|
|
|
|
case ISD::SELECT:
|
2008-02-27 08:25:32 +08:00
|
|
|
if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
|
2006-02-17 05:11:51 +08:00
|
|
|
KnownOne, TLO, Depth+1))
|
|
|
|
|
return true;
|
2008-02-27 08:25:32 +08:00
|
|
|
if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
|
2006-02-17 05:11:51 +08:00
|
|
|
KnownOne2, TLO, Depth+1))
|
|
|
|
|
return true;
|
|
|
|
|
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
|
|
|
|
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
|
|
|
|
|
|
|
|
|
|
// If the operands are constants, see if we can simplify them.
|
2008-02-27 08:25:32 +08:00
|
|
|
if (TLO.ShrinkDemandedConstant(Op, NewMask))
|
2006-02-17 05:11:51 +08:00
|
|
|
return true;
|
|
|
|
|
|
2006-02-27 07:36:02 +08:00
|
|
|
// Only known if known in both the LHS and RHS.
|
|
|
|
|
KnownOne &= KnownOne2;
|
|
|
|
|
KnownZero &= KnownZero2;
|
|
|
|
|
break;
|
|
|
|
|
case ISD::SELECT_CC:
|
2008-02-27 08:25:32 +08:00
|
|
|
if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
|
2006-02-27 07:36:02 +08:00
|
|
|
KnownOne, TLO, Depth+1))
|
|
|
|
|
return true;
|
2008-02-27 08:25:32 +08:00
|
|
|
if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
|
2006-02-27 07:36:02 +08:00
|
|
|
KnownOne2, TLO, Depth+1))
|
|
|
|
|
return true;
|
|
|
|
|
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
|
|
|
|
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
|
|
|
|
|
|
|
|
|
|
// If the operands are constants, see if we can simplify them.
|
2008-02-27 08:25:32 +08:00
|
|
|
if (TLO.ShrinkDemandedConstant(Op, NewMask))
|
2006-02-27 07:36:02 +08:00
|
|
|
return true;
|
|
|
|
|
|
2006-02-17 05:11:51 +08:00
|
|
|
// Only known if known in both the LHS and RHS.
|
|
|
|
|
KnownOne &= KnownOne2;
|
|
|
|
|
KnownZero &= KnownZero2;
|
2006-02-04 06:24:05 +08:00
|
|
|
break;
|
|
|
|
|
case ISD::SHL:
|
2006-02-17 05:11:51 +08:00
|
|
|
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
|
2008-09-13 00:56:44 +08:00
|
|
|
unsigned ShAmt = SA->getZExtValue();
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue InOp = Op.getOperand(0);
|
Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used.
This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }
into:
_baz:
srwi r2, r3, 1
extsh r3, r2
blr
on PPC, instead of:
_baz:
slwi r2, r3, 8
srwi r2, r2, 9
extsh r3, r2
blr
GCC produces:
_baz:
srwi r10,r4,24
insrwi r10,r3,24,0
srawi r9,r3,24
srawi r3,r10,9
extsh r3,r3
blr
This implements CodeGen/PowerPC/shl_elim.ll
llvm-svn: 36221
2007-04-18 05:14:16 +08:00
|
|
|
|
2008-02-27 08:25:32 +08:00
|
|
|
// If the shift count is an invalid immediate, don't do anything.
|
|
|
|
|
if (ShAmt >= BitWidth)
|
|
|
|
|
break;
|
|
|
|
|
|
Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used.
This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }
into:
_baz:
srwi r2, r3, 1
extsh r3, r2
blr
on PPC, instead of:
_baz:
slwi r2, r3, 8
srwi r2, r2, 9
extsh r3, r2
blr
GCC produces:
_baz:
srwi r10,r4,24
insrwi r10,r3,24,0
srawi r9,r3,24
srawi r3,r10,9
extsh r3,r3
blr
This implements CodeGen/PowerPC/shl_elim.ll
llvm-svn: 36221
2007-04-18 05:14:16 +08:00
|
|
|
// If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
|
|
|
|
|
// single shift. We can do this if the bottom bits (which are shifted
|
|
|
|
|
// out) are never demanded.
|
|
|
|
|
if (InOp.getOpcode() == ISD::SRL &&
|
|
|
|
|
isa<ConstantSDNode>(InOp.getOperand(1))) {
|
2008-02-27 08:25:32 +08:00
|
|
|
if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
|
2008-09-13 00:56:44 +08:00
|
|
|
unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
|
Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used.
This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }
into:
_baz:
srwi r2, r3, 1
extsh r3, r2
blr
on PPC, instead of:
_baz:
slwi r2, r3, 8
srwi r2, r2, 9
extsh r3, r2
blr
GCC produces:
_baz:
srwi r10,r4,24
insrwi r10,r3,24,0
srawi r9,r3,24
srawi r3,r10,9
extsh r3,r3
blr
This implements CodeGen/PowerPC/shl_elim.ll
llvm-svn: 36221
2007-04-18 05:14:16 +08:00
|
|
|
unsigned Opc = ISD::SHL;
|
|
|
|
|
int Diff = ShAmt-C1;
|
|
|
|
|
if (Diff < 0) {
|
|
|
|
|
Diff = -Diff;
|
|
|
|
|
Opc = ISD::SRL;
|
|
|
|
|
}
|
|
|
|
|
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue NewSA =
|
2007-05-31 00:30:06 +08:00
|
|
|
TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT VT = Op.getValueType();
|
2009-02-03 08:47:48 +08:00
|
|
|
return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
|
Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used.
This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }
into:
_baz:
srwi r2, r3, 1
extsh r3, r2
blr
on PPC, instead of:
_baz:
slwi r2, r3, 8
srwi r2, r2, 9
extsh r3, r2
blr
GCC produces:
_baz:
srwi r10,r4,24
insrwi r10,r3,24,0
srawi r9,r3,24
srawi r3,r10,9
extsh r3,r3
blr
This implements CodeGen/PowerPC/shl_elim.ll
llvm-svn: 36221
2007-04-18 05:14:16 +08:00
|
|
|
InOp.getOperand(0), NewSA));
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2008-02-27 08:25:32 +08:00
|
|
|
if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt),
|
2006-02-17 05:11:51 +08:00
|
|
|
KnownZero, KnownOne, TLO, Depth+1))
|
|
|
|
|
return true;
|
2008-09-13 00:56:44 +08:00
|
|
|
KnownZero <<= SA->getZExtValue();
|
|
|
|
|
KnownOne <<= SA->getZExtValue();
|
2008-02-27 08:25:32 +08:00
|
|
|
// low bits known zero.
|
2008-09-13 00:56:44 +08:00
|
|
|
KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
|
2006-02-17 05:11:51 +08:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case ISD::SRL:
|
|
|
|
|
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT VT = Op.getValueType();
|
2008-09-13 00:56:44 +08:00
|
|
|
unsigned ShAmt = SA->getZExtValue();
|
2008-06-06 20:08:01 +08:00
|
|
|
unsigned VTSize = VT.getSizeInBits();
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue InOp = Op.getOperand(0);
|
Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used.
This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }
into:
_baz:
srwi r2, r3, 1
extsh r3, r2
blr
on PPC, instead of:
_baz:
slwi r2, r3, 8
srwi r2, r2, 9
extsh r3, r2
blr
GCC produces:
_baz:
srwi r10,r4,24
insrwi r10,r3,24,0
srawi r9,r3,24
srawi r3,r10,9
extsh r3,r3
blr
This implements CodeGen/PowerPC/shl_elim.ll
llvm-svn: 36221
2007-04-18 05:14:16 +08:00
|
|
|
|
2008-02-27 08:25:32 +08:00
|
|
|
// If the shift count is an invalid immediate, don't do anything.
|
|
|
|
|
if (ShAmt >= BitWidth)
|
|
|
|
|
break;
|
|
|
|
|
|
Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used.
This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }
into:
_baz:
srwi r2, r3, 1
extsh r3, r2
blr
on PPC, instead of:
_baz:
slwi r2, r3, 8
srwi r2, r2, 9
extsh r3, r2
blr
GCC produces:
_baz:
srwi r10,r4,24
insrwi r10,r3,24,0
srawi r9,r3,24
srawi r3,r10,9
extsh r3,r3
blr
This implements CodeGen/PowerPC/shl_elim.ll
llvm-svn: 36221
2007-04-18 05:14:16 +08:00
|
|
|
// If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
|
|
|
|
|
// single shift. We can do this if the top bits (which are shifted out)
|
|
|
|
|
// are never demanded.
|
|
|
|
|
if (InOp.getOpcode() == ISD::SHL &&
|
|
|
|
|
isa<ConstantSDNode>(InOp.getOperand(1))) {
|
2008-02-27 08:25:32 +08:00
|
|
|
if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
|
2008-09-13 00:56:44 +08:00
|
|
|
unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
|
Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used.
This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }
into:
_baz:
srwi r2, r3, 1
extsh r3, r2
blr
on PPC, instead of:
_baz:
slwi r2, r3, 8
srwi r2, r2, 9
extsh r3, r2
blr
GCC produces:
_baz:
srwi r10,r4,24
insrwi r10,r3,24,0
srawi r9,r3,24
srawi r3,r10,9
extsh r3,r3
blr
This implements CodeGen/PowerPC/shl_elim.ll
llvm-svn: 36221
2007-04-18 05:14:16 +08:00
|
|
|
unsigned Opc = ISD::SRL;
|
|
|
|
|
int Diff = ShAmt-C1;
|
|
|
|
|
if (Diff < 0) {
|
|
|
|
|
Diff = -Diff;
|
|
|
|
|
Opc = ISD::SHL;
|
|
|
|
|
}
|
|
|
|
|
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue NewSA =
|
2007-04-18 06:53:02 +08:00
|
|
|
TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
|
2009-02-03 08:47:48 +08:00
|
|
|
return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
|
Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used.
This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }
into:
_baz:
srwi r2, r3, 1
extsh r3, r2
blr
on PPC, instead of:
_baz:
slwi r2, r3, 8
srwi r2, r2, 9
extsh r3, r2
blr
GCC produces:
_baz:
srwi r10,r4,24
insrwi r10,r3,24,0
srawi r9,r3,24
srawi r3,r10,9
extsh r3,r3
blr
This implements CodeGen/PowerPC/shl_elim.ll
llvm-svn: 36221
2007-04-18 05:14:16 +08:00
|
|
|
InOp.getOperand(0), NewSA));
|
|
|
|
|
}
|
|
|
|
|
}
|
2006-02-17 05:11:51 +08:00
|
|
|
|
|
|
|
|
// Compute the new bits that are at the top now.
|
2008-02-27 08:25:32 +08:00
|
|
|
if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
|
2006-02-17 05:11:51 +08:00
|
|
|
KnownZero, KnownOne, TLO, Depth+1))
|
|
|
|
|
return true;
|
|
|
|
|
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
2008-02-27 08:25:32 +08:00
|
|
|
KnownZero = KnownZero.lshr(ShAmt);
|
|
|
|
|
KnownOne = KnownOne.lshr(ShAmt);
|
2006-06-14 00:52:37 +08:00
|
|
|
|
2008-02-27 08:25:32 +08:00
|
|
|
APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
|
2006-06-14 00:52:37 +08:00
|
|
|
KnownZero |= HighBits; // High bits known zero.
|
2006-02-17 05:11:51 +08:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case ISD::SRA:
|
2009-01-29 09:59:02 +08:00
|
|
|
// If this is an arithmetic shift right and only the low-bit is set, we can
|
|
|
|
|
// always convert this into a logical shr, even if the shift amount is
|
|
|
|
|
// variable. The low bit of the shift cannot be an input sign bit unless
|
|
|
|
|
// the shift amount is >= the size of the datatype, which is undefined.
|
|
|
|
|
if (DemandedMask == 1)
|
2009-02-03 08:47:48 +08:00
|
|
|
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
|
2009-01-29 09:59:02 +08:00
|
|
|
Op.getOperand(0), Op.getOperand(1)));
|
|
|
|
|
|
2006-02-17 05:11:51 +08:00
|
|
|
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT VT = Op.getValueType();
|
2008-09-13 00:56:44 +08:00
|
|
|
unsigned ShAmt = SA->getZExtValue();
|
2006-02-17 05:11:51 +08:00
|
|
|
|
2008-02-27 08:25:32 +08:00
|
|
|
// If the shift count is an invalid immediate, don't do anything.
|
|
|
|
|
if (ShAmt >= BitWidth)
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
APInt InDemandedMask = (NewMask << ShAmt);
|
2006-05-09 01:22:53 +08:00
|
|
|
|
|
|
|
|
// If any of the demanded bits are produced by the sign extension, we also
|
|
|
|
|
// demand the input sign bit.
|
2008-02-27 08:25:32 +08:00
|
|
|
APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
|
|
|
|
|
if (HighBits.intersects(NewMask))
|
2009-12-12 05:31:27 +08:00
|
|
|
InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
|
2006-05-09 01:22:53 +08:00
|
|
|
|
|
|
|
|
if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
|
2006-02-17 05:11:51 +08:00
|
|
|
KnownZero, KnownOne, TLO, Depth+1))
|
|
|
|
|
return true;
|
|
|
|
|
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
2008-02-27 08:25:32 +08:00
|
|
|
KnownZero = KnownZero.lshr(ShAmt);
|
|
|
|
|
KnownOne = KnownOne.lshr(ShAmt);
|
2006-02-17 05:11:51 +08:00
|
|
|
|
2008-02-27 08:25:32 +08:00
|
|
|
// Handle the sign bit, adjusted to where it is now in the mask.
|
|
|
|
|
APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
|
2006-02-17 05:11:51 +08:00
|
|
|
|
|
|
|
|
// If the input sign bit is known to be zero, or if none of the top bits
|
|
|
|
|
// are demanded, turn this into an unsigned shift right.
|
2008-02-27 08:25:32 +08:00
|
|
|
if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
|
2009-02-03 08:47:48 +08:00
|
|
|
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
|
|
|
|
|
Op.getOperand(0),
|
2006-02-17 05:11:51 +08:00
|
|
|
Op.getOperand(1)));
|
2008-02-27 08:25:32 +08:00
|
|
|
} else if (KnownOne.intersects(SignBit)) { // New bits are known one.
|
2006-02-17 05:11:51 +08:00
|
|
|
KnownOne |= HighBits;
|
|
|
|
|
}
|
2006-02-04 06:24:05 +08:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case ISD::SIGN_EXTEND_INREG: {
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
|
2006-02-17 05:11:51 +08:00
|
|
|
|
2006-02-27 07:36:02 +08:00
|
|
|
// Sign extension. Compute the demanded bits in the result that are not
|
2006-02-17 05:11:51 +08:00
|
|
|
// present in the input.
|
2010-01-09 10:13:55 +08:00
|
|
|
APInt NewBits =
|
|
|
|
|
APInt::getHighBitsSet(BitWidth,
|
|
|
|
|
BitWidth - EVT.getScalarType().getSizeInBits()) &
|
|
|
|
|
NewMask;
|
2006-02-17 05:11:51 +08:00
|
|
|
|
2006-02-27 07:36:02 +08:00
|
|
|
// If none of the extended bits are demanded, eliminate the sextinreg.
|
|
|
|
|
if (NewBits == 0)
|
|
|
|
|
return TLO.CombineTo(Op, Op.getOperand(0));
|
|
|
|
|
|
2010-01-09 10:13:55 +08:00
|
|
|
APInt InSignBit = APInt::getSignBit(EVT.getScalarType().getSizeInBits());
|
2008-02-27 08:25:32 +08:00
|
|
|
InSignBit.zext(BitWidth);
|
2010-01-09 10:13:55 +08:00
|
|
|
APInt InputDemandedBits =
|
|
|
|
|
APInt::getLowBitsSet(BitWidth,
|
|
|
|
|
EVT.getScalarType().getSizeInBits()) &
|
|
|
|
|
NewMask;
|
2006-02-17 05:11:51 +08:00
|
|
|
|
2006-02-27 07:36:02 +08:00
|
|
|
// Since the sign extended bits are demanded, we know that the sign
|
2006-02-17 05:11:51 +08:00
|
|
|
// bit is demanded.
|
2006-02-27 07:36:02 +08:00
|
|
|
InputDemandedBits |= InSignBit;
|
2006-02-17 05:11:51 +08:00
|
|
|
|
|
|
|
|
if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
|
|
|
|
|
KnownZero, KnownOne, TLO, Depth+1))
|
2006-02-04 06:24:05 +08:00
|
|
|
return true;
|
2006-02-17 05:11:51 +08:00
|
|
|
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
|
|
|
|
|
|
|
|
|
// If the sign bit of the input is known set or clear, then we know the
|
|
|
|
|
// top bits of the result.
|
|
|
|
|
|
2006-02-27 07:36:02 +08:00
|
|
|
// If the input sign bit is known zero, convert this into a zero extension.
|
2008-02-27 08:25:32 +08:00
|
|
|
if (KnownZero.intersects(InSignBit))
|
2006-02-27 07:36:02 +08:00
|
|
|
return TLO.CombineTo(Op,
|
2009-02-03 08:47:48 +08:00
|
|
|
TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT));
|
2006-02-27 07:36:02 +08:00
|
|
|
|
2008-02-27 08:25:32 +08:00
|
|
|
if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
|
2006-02-17 05:11:51 +08:00
|
|
|
KnownOne |= NewBits;
|
|
|
|
|
KnownZero &= ~NewBits;
|
2006-02-27 07:36:02 +08:00
|
|
|
} else { // Input sign bit unknown
|
2006-02-17 05:11:51 +08:00
|
|
|
KnownZero &= ~NewBits;
|
|
|
|
|
KnownOne &= ~NewBits;
|
2006-02-04 06:24:05 +08:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
2006-02-27 07:36:02 +08:00
|
|
|
case ISD::ZERO_EXTEND: {
|
2010-01-09 10:13:55 +08:00
|
|
|
unsigned OperandBitWidth =
|
|
|
|
|
Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
|
2008-02-27 08:25:32 +08:00
|
|
|
APInt InMask = NewMask;
|
|
|
|
|
InMask.trunc(OperandBitWidth);
|
2006-02-27 07:36:02 +08:00
|
|
|
|
|
|
|
|
// If none of the top bits are demanded, convert this into an any_extend.
|
2008-02-27 08:25:32 +08:00
|
|
|
APInt NewBits =
|
|
|
|
|
APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
|
|
|
|
|
if (!NewBits.intersects(NewMask))
|
2009-02-03 08:47:48 +08:00
|
|
|
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
|
2006-02-27 07:36:02 +08:00
|
|
|
Op.getValueType(),
|
|
|
|
|
Op.getOperand(0)));
|
|
|
|
|
|
2008-02-27 08:25:32 +08:00
|
|
|
if (SimplifyDemandedBits(Op.getOperand(0), InMask,
|
2006-02-27 07:36:02 +08:00
|
|
|
KnownZero, KnownOne, TLO, Depth+1))
|
|
|
|
|
return true;
|
|
|
|
|
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
2008-02-27 08:25:32 +08:00
|
|
|
KnownZero.zext(BitWidth);
|
|
|
|
|
KnownOne.zext(BitWidth);
|
2006-02-27 07:36:02 +08:00
|
|
|
KnownZero |= NewBits;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case ISD::SIGN_EXTEND: {
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT InVT = Op.getOperand(0).getValueType();
|
2010-01-09 10:13:55 +08:00
|
|
|
unsigned InBits = InVT.getScalarType().getSizeInBits();
|
2008-02-27 08:25:32 +08:00
|
|
|
APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
|
2008-03-12 05:29:43 +08:00
|
|
|
APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
|
2008-02-27 08:25:32 +08:00
|
|
|
APInt NewBits = ~InMask & NewMask;
|
2006-02-27 07:36:02 +08:00
|
|
|
|
|
|
|
|
// If none of the top bits are demanded, convert this into an any_extend.
|
|
|
|
|
if (NewBits == 0)
|
2009-02-03 08:47:48 +08:00
|
|
|
return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
|
|
|
|
|
Op.getValueType(),
|
|
|
|
|
Op.getOperand(0)));
|
2006-02-27 07:36:02 +08:00
|
|
|
|
|
|
|
|
// Since some of the sign extended bits are demanded, we know that the sign
|
|
|
|
|
// bit is demanded.
|
2008-02-27 08:25:32 +08:00
|
|
|
APInt InDemandedBits = InMask & NewMask;
|
2006-02-27 07:36:02 +08:00
|
|
|
InDemandedBits |= InSignBit;
|
2008-02-27 08:25:32 +08:00
|
|
|
InDemandedBits.trunc(InBits);
|
2006-02-27 07:36:02 +08:00
|
|
|
|
|
|
|
|
if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
|
|
|
|
|
KnownOne, TLO, Depth+1))
|
|
|
|
|
return true;
|
2008-02-27 08:25:32 +08:00
|
|
|
KnownZero.zext(BitWidth);
|
|
|
|
|
KnownOne.zext(BitWidth);
|
2006-02-27 07:36:02 +08:00
|
|
|
|
|
|
|
|
// If the sign bit is known zero, convert this to a zero extend.
|
2008-02-27 08:25:32 +08:00
|
|
|
if (KnownZero.intersects(InSignBit))
|
2009-02-03 08:47:48 +08:00
|
|
|
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
|
2006-02-27 07:36:02 +08:00
|
|
|
Op.getValueType(),
|
|
|
|
|
Op.getOperand(0)));
|
|
|
|
|
|
|
|
|
|
// If the sign bit is known one, the top bits match.
|
2008-02-27 08:25:32 +08:00
|
|
|
if (KnownOne.intersects(InSignBit)) {
|
2006-02-27 07:36:02 +08:00
|
|
|
KnownOne |= NewBits;
|
|
|
|
|
KnownZero &= ~NewBits;
|
|
|
|
|
} else { // Otherwise, top bits aren't known.
|
|
|
|
|
KnownOne &= ~NewBits;
|
|
|
|
|
KnownZero &= ~NewBits;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case ISD::ANY_EXTEND: {
|
2010-01-09 10:13:55 +08:00
|
|
|
unsigned OperandBitWidth =
|
|
|
|
|
Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
|
2008-02-27 08:25:32 +08:00
|
|
|
APInt InMask = NewMask;
|
|
|
|
|
InMask.trunc(OperandBitWidth);
|
|
|
|
|
if (SimplifyDemandedBits(Op.getOperand(0), InMask,
|
2006-02-27 07:36:02 +08:00
|
|
|
KnownZero, KnownOne, TLO, Depth+1))
|
|
|
|
|
return true;
|
|
|
|
|
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
2008-02-27 08:25:32 +08:00
|
|
|
KnownZero.zext(BitWidth);
|
|
|
|
|
KnownOne.zext(BitWidth);
|
2006-02-27 07:36:02 +08:00
|
|
|
break;
|
|
|
|
|
}
|
2006-05-06 06:32:12 +08:00
|
|
|
case ISD::TRUNCATE: {
|
2006-05-06 08:11:52 +08:00
|
|
|
// Simplify the input, using demanded bit information, and compute the known
|
|
|
|
|
// zero/one bits live out.
|
2008-02-27 08:25:32 +08:00
|
|
|
APInt TruncMask = NewMask;
|
|
|
|
|
TruncMask.zext(Op.getOperand(0).getValueSizeInBits());
|
|
|
|
|
if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
|
2006-05-06 06:32:12 +08:00
|
|
|
KnownZero, KnownOne, TLO, Depth+1))
|
|
|
|
|
return true;
|
2008-02-27 08:25:32 +08:00
|
|
|
KnownZero.trunc(BitWidth);
|
|
|
|
|
KnownOne.trunc(BitWidth);
|
2006-05-06 08:11:52 +08:00
|
|
|
|
|
|
|
|
// If the input is only used by this truncate, see if we can shrink it based
|
|
|
|
|
// on the known demanded bits.
|
2008-08-29 05:40:38 +08:00
|
|
|
if (Op.getOperand(0).getNode()->hasOneUse()) {
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue In = Op.getOperand(0);
|
2008-02-27 08:25:32 +08:00
|
|
|
unsigned InBitWidth = In.getValueSizeInBits();
|
2006-05-06 08:11:52 +08:00
|
|
|
switch (In.getOpcode()) {
|
|
|
|
|
default: break;
|
|
|
|
|
case ISD::SRL:
|
|
|
|
|
// Shrink SRL by a constant if none of the high bits shifted in are
|
|
|
|
|
// demanded.
|
|
|
|
|
if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){
|
2008-02-27 08:25:32 +08:00
|
|
|
APInt HighBits = APInt::getHighBitsSet(InBitWidth,
|
|
|
|
|
InBitWidth - BitWidth);
|
2008-09-13 00:56:44 +08:00
|
|
|
HighBits = HighBits.lshr(ShAmt->getZExtValue());
|
2008-02-27 08:25:32 +08:00
|
|
|
HighBits.trunc(BitWidth);
|
2006-05-06 08:11:52 +08:00
|
|
|
|
2008-09-13 00:56:44 +08:00
|
|
|
if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
|
2006-05-06 08:11:52 +08:00
|
|
|
// None of the shifted in bits are needed. Add a truncate of the
|
|
|
|
|
// shift input, then shift it.
|
2009-02-03 08:47:48 +08:00
|
|
|
SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
|
2006-05-06 08:11:52 +08:00
|
|
|
Op.getValueType(),
|
|
|
|
|
In.getOperand(0));
|
2009-02-03 08:47:48 +08:00
|
|
|
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
|
|
|
|
|
Op.getValueType(),
|
|
|
|
|
NewTrunc,
|
|
|
|
|
In.getOperand(1)));
|
2006-05-06 08:11:52 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2006-05-06 06:32:12 +08:00
|
|
|
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
|
|
|
|
break;
|
|
|
|
|
}
|
2006-02-27 07:36:02 +08:00
|
|
|
case ISD::AssertZext: {
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
|
2008-02-27 08:25:32 +08:00
|
|
|
APInt InMask = APInt::getLowBitsSet(BitWidth,
|
2008-06-06 20:08:01 +08:00
|
|
|
VT.getSizeInBits());
|
2008-02-27 08:25:32 +08:00
|
|
|
if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask,
|
2006-02-27 07:36:02 +08:00
|
|
|
KnownZero, KnownOne, TLO, Depth+1))
|
|
|
|
|
return true;
|
|
|
|
|
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
2008-02-27 08:25:32 +08:00
|
|
|
KnownZero |= ~InMask & NewMask;
|
2006-02-27 07:36:02 +08:00
|
|
|
break;
|
|
|
|
|
}
|
2007-12-23 05:35:38 +08:00
|
|
|
case ISD::BIT_CONVERT:
|
|
|
|
|
#if 0
|
|
|
|
|
// If this is an FP->Int bitcast and if the sign bit is the only thing that
|
|
|
|
|
// is demanded, turn this into a FGETSIGN.
|
2009-08-11 06:56:29 +08:00
|
|
|
if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) &&
|
2009-08-12 04:47:22 +08:00
|
|
|
MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
|
|
|
|
|
!MVT::isVector(Op.getOperand(0).getValueType())) {
|
2007-12-23 05:35:38 +08:00
|
|
|
// Only do this xform if FGETSIGN is valid or if before legalize.
|
|
|
|
|
if (!TLO.AfterLegalize ||
|
|
|
|
|
isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
|
|
|
|
|
// Make a FGETSIGN + SHL to move the sign bit into the appropriate
|
|
|
|
|
// place. We expect the SHL to be eliminated by other optimizations.
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
|
2007-12-23 05:35:38 +08:00
|
|
|
Op.getOperand(0));
|
2008-06-06 20:08:01 +08:00
|
|
|
unsigned ShVal = Op.getValueType().getSizeInBits()-1;
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
|
2007-12-23 05:35:38 +08:00
|
|
|
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
|
|
|
|
|
Sign, ShAmt));
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
break;
|
Implement support for using modeling implicit-zero-extension on x86-64
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.
This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.
Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.
Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.
Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.
Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.
llvm-svn: 68576
2009-04-08 08:15:30 +08:00
|
|
|
case ISD::ADD:
|
|
|
|
|
case ISD::MUL:
|
|
|
|
|
case ISD::SUB: {
|
|
|
|
|
// Add, Sub, and Mul don't demand any bits in positions beyond that
|
|
|
|
|
// of the highest bit demanded of them.
|
|
|
|
|
APInt LoMask = APInt::getLowBitsSet(BitWidth,
|
|
|
|
|
BitWidth - NewMask.countLeadingZeros());
|
|
|
|
|
if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
|
|
|
|
|
KnownOne2, TLO, Depth+1))
|
|
|
|
|
return true;
|
|
|
|
|
if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
|
|
|
|
|
KnownOne2, TLO, Depth+1))
|
|
|
|
|
return true;
|
|
|
|
|
// See if the operation should be performed at a smaller bit width.
|
2010-01-07 03:38:29 +08:00
|
|
|
if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
|
Implement support for using modeling implicit-zero-extension on x86-64
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.
This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.
Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.
Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.
Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.
Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.
llvm-svn: 68576
2009-04-08 08:15:30 +08:00
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
// FALL THROUGH
|
2008-05-06 08:53:29 +08:00
|
|
|
default:
|
2006-04-02 14:15:09 +08:00
|
|
|
// Just use ComputeMaskedBits to compute output bits.
|
2008-02-27 08:25:32 +08:00
|
|
|
TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
|
2006-02-27 09:00:42 +08:00
|
|
|
break;
|
2006-02-04 06:24:05 +08:00
|
|
|
}
|
2006-02-27 07:36:02 +08:00
|
|
|
|
|
|
|
|
// If we know the value of all of the demanded bits, return this as a
|
|
|
|
|
// constant.
|
2008-02-27 08:25:32 +08:00
|
|
|
if ((NewMask & (KnownZero|KnownOne)) == NewMask)
|
2006-02-27 07:36:02 +08:00
|
|
|
return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
|
|
|
|
|
|
2006-02-04 06:24:05 +08:00
|
|
|
return false;
|
|
|
|
|
}
|
2006-01-30 12:09:27 +08:00
|
|
|
|
2006-02-17 05:11:51 +08:00
|
|
|
/// computeMaskedBitsForTargetNode - Determine which of the bits specified
|
|
|
|
|
/// in Mask are known to be either zero or one and return them in the
|
|
|
|
|
/// KnownZero/KnownOne bitsets.
|
2008-07-28 05:46:04 +08:00
|
|
|
void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
|
2008-02-14 06:28:48 +08:00
|
|
|
const APInt &Mask,
|
2008-02-13 08:35:47 +08:00
|
|
|
APInt &KnownZero,
|
|
|
|
|
APInt &KnownOne,
|
2007-06-22 22:59:07 +08:00
|
|
|
const SelectionDAG &DAG,
|
2006-02-17 05:11:51 +08:00
|
|
|
unsigned Depth) const {
|
2006-04-02 14:19:46 +08:00
|
|
|
assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
|
|
|
|
|
Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
|
|
|
|
|
Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
|
|
|
|
|
Op.getOpcode() == ISD::INTRINSIC_VOID) &&
|
2006-01-30 12:09:27 +08:00
|
|
|
"Should use MaskedValueIsZero if you don't know whether Op"
|
|
|
|
|
" is a target node!");
|
2008-02-14 06:28:48 +08:00
|
|
|
KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
|
2005-12-22 07:05:39 +08:00
|
|
|
}
|
2006-01-27 04:37:03 +08:00
|
|
|
|
2006-05-06 17:27:13 +08:00
|
|
|
/// ComputeNumSignBitsForTargetNode - This method can be implemented by
|
|
|
|
|
/// targets that want to expose additional information about sign bits to the
|
|
|
|
|
/// DAG Combiner.
|
2008-07-28 05:46:04 +08:00
|
|
|
unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
|
2006-05-06 17:27:13 +08:00
|
|
|
unsigned Depth) const {
|
|
|
|
|
assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
|
|
|
|
|
Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
|
|
|
|
|
Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
|
|
|
|
|
Op.getOpcode() == ISD::INTRINSIC_VOID) &&
|
|
|
|
|
"Should use ComputeNumSignBits if you don't know whether Op"
|
|
|
|
|
" is a target node!");
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
|
2009-02-16 07:59:32 +08:00
|
|
|
/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
|
|
|
|
|
/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
|
|
|
|
|
/// determine which bit is set.
|
|
|
|
|
///
|
2009-02-12 03:19:41 +08:00
|
|
|
static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
|
2009-02-16 07:59:32 +08:00
|
|
|
// A left-shift of a constant one will have exactly one bit set, because
|
|
|
|
|
// shifting the bit off the end is undefined.
|
|
|
|
|
if (Val.getOpcode() == ISD::SHL)
|
|
|
|
|
if (ConstantSDNode *C =
|
|
|
|
|
dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
|
|
|
|
|
if (C->getAPIntValue() == 1)
|
|
|
|
|
return true;
|
|
|
|
|
|
|
|
|
|
// Similarly, a right-shift of a constant sign-bit will have exactly
|
|
|
|
|
// one bit set.
|
|
|
|
|
if (Val.getOpcode() == ISD::SRL)
|
|
|
|
|
if (ConstantSDNode *C =
|
|
|
|
|
dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
|
|
|
|
|
if (C->getAPIntValue().isSignBit())
|
|
|
|
|
return true;
|
|
|
|
|
|
|
|
|
|
// More could be done here, though the above checks are enough
|
|
|
|
|
// to handle some common cases.
|
2009-01-29 09:59:02 +08:00
|
|
|
|
2009-02-16 07:59:32 +08:00
|
|
|
// Fall back to ComputeMaskedBits to catch other known cases.
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT OpVT = Val.getValueType();
|
2009-01-29 09:59:02 +08:00
|
|
|
unsigned BitWidth = OpVT.getSizeInBits();
|
|
|
|
|
APInt Mask = APInt::getAllOnesValue(BitWidth);
|
|
|
|
|
APInt KnownZero, KnownOne;
|
|
|
|
|
DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
|
2009-02-12 03:19:41 +08:00
|
|
|
return (KnownZero.countPopulation() == BitWidth - 1) &&
|
|
|
|
|
(KnownOne.countPopulation() == 1);
|
2009-01-29 09:59:02 +08:00
|
|
|
}
|
2006-05-06 17:27:13 +08:00
|
|
|
|
2007-02-09 06:13:59 +08:00
|
|
|
/// SimplifySetCC - Try to simplify a setcc built with the specified operands
|
2008-07-28 05:46:04 +08:00
|
|
|
/// and cc. If it is unable to simplify it, return a null SDValue.
|
|
|
|
|
SDValue
|
2009-08-11 06:56:29 +08:00
|
|
|
TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
|
2007-02-09 06:13:59 +08:00
|
|
|
ISD::CondCode Cond, bool foldBooleans,
|
2009-02-03 08:47:48 +08:00
|
|
|
DAGCombinerInfo &DCI, DebugLoc dl) const {
|
2007-02-09 06:13:59 +08:00
|
|
|
SelectionDAG &DAG = DCI.DAG;
|
2009-08-12 08:36:31 +08:00
|
|
|
LLVMContext &Context = *DAG.getContext();
|
2007-02-09 06:13:59 +08:00
|
|
|
|
|
|
|
|
// These setcc operations always fold.
|
|
|
|
|
switch (Cond) {
|
|
|
|
|
default: break;
|
|
|
|
|
case ISD::SETFALSE:
|
|
|
|
|
case ISD::SETFALSE2: return DAG.getConstant(0, VT);
|
|
|
|
|
case ISD::SETTRUE:
|
|
|
|
|
case ISD::SETTRUE2: return DAG.getConstant(1, VT);
|
|
|
|
|
}
|
|
|
|
|
|
2009-07-27 07:47:17 +08:00
|
|
|
if (isa<ConstantSDNode>(N0.getNode())) {
|
|
|
|
|
// Ensure that the constant occurs on the RHS, and fold constant
|
|
|
|
|
// comparisons.
|
|
|
|
|
return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
|
|
|
|
|
}
|
|
|
|
|
|
2008-08-29 05:40:38 +08:00
|
|
|
if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
|
2008-03-04 06:22:56 +08:00
|
|
|
const APInt &C1 = N1C->getAPIntValue();
|
2009-07-27 07:47:17 +08:00
|
|
|
|
|
|
|
|
// If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
|
|
|
|
|
// equality comparison, then we're just comparing whether X itself is
|
|
|
|
|
// zero.
|
|
|
|
|
if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
|
|
|
|
|
N0.getOperand(0).getOpcode() == ISD::CTLZ &&
|
|
|
|
|
N0.getOperand(1).getOpcode() == ISD::Constant) {
|
2010-01-08 04:58:44 +08:00
|
|
|
const APInt &ShAmt
|
|
|
|
|
= cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
|
2009-07-27 07:47:17 +08:00
|
|
|
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
|
|
|
|
|
ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
|
|
|
|
|
if ((C1 == 0) == (Cond == ISD::SETEQ)) {
|
|
|
|
|
// (srl (ctlz x), 5) == 0 -> X != 0
|
|
|
|
|
// (srl (ctlz x), 5) != 1 -> X != 0
|
|
|
|
|
Cond = ISD::SETNE;
|
|
|
|
|
} else {
|
|
|
|
|
// (srl (ctlz x), 5) != 0 -> X == 0
|
|
|
|
|
// (srl (ctlz x), 5) == 1 -> X == 0
|
|
|
|
|
Cond = ISD::SETEQ;
|
2007-02-09 06:13:59 +08:00
|
|
|
}
|
2009-07-27 07:47:17 +08:00
|
|
|
SDValue Zero = DAG.getConstant(0, N0.getValueType());
|
|
|
|
|
return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
|
|
|
|
|
Zero, Cond);
|
2007-02-09 06:13:59 +08:00
|
|
|
}
|
2009-07-27 07:47:17 +08:00
|
|
|
}
|
2008-11-07 09:28:02 +08:00
|
|
|
|
2009-07-27 07:47:17 +08:00
|
|
|
// If the LHS is '(and load, const)', the RHS is 0,
|
|
|
|
|
// the test is for equality or unsigned, and all 1 bits of the const are
|
|
|
|
|
// in the same partial word, see if we can shorten the load.
|
|
|
|
|
if (DCI.isBeforeLegalize() &&
|
|
|
|
|
N0.getOpcode() == ISD::AND && C1 == 0 &&
|
|
|
|
|
N0.getNode()->hasOneUse() &&
|
|
|
|
|
isa<LoadSDNode>(N0.getOperand(0)) &&
|
|
|
|
|
N0.getOperand(0).getNode()->hasOneUse() &&
|
|
|
|
|
isa<ConstantSDNode>(N0.getOperand(1))) {
|
|
|
|
|
LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
|
2010-01-08 04:58:44 +08:00
|
|
|
APInt bestMask;
|
2009-07-27 07:47:17 +08:00
|
|
|
unsigned bestWidth = 0, bestOffset = 0;
|
2010-01-08 04:58:44 +08:00
|
|
|
if (!Lod->isVolatile() && Lod->isUnindexed()) {
|
2009-07-27 07:47:17 +08:00
|
|
|
unsigned origWidth = N0.getValueType().getSizeInBits();
|
2010-01-08 04:58:44 +08:00
|
|
|
unsigned maskWidth = origWidth;
|
2009-07-27 07:47:17 +08:00
|
|
|
// We can narrow (e.g.) 16-bit extending loads on 32-bit target to
|
|
|
|
|
// 8 bits, but have to be careful...
|
|
|
|
|
if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
|
|
|
|
|
origWidth = Lod->getMemoryVT().getSizeInBits();
|
2010-01-08 04:58:44 +08:00
|
|
|
const APInt &Mask =
|
|
|
|
|
cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
|
2009-07-27 07:47:17 +08:00
|
|
|
for (unsigned width = origWidth / 2; width>=8; width /= 2) {
|
2010-01-08 04:58:44 +08:00
|
|
|
APInt newMask = APInt::getLowBitsSet(maskWidth, width);
|
2009-07-27 07:47:17 +08:00
|
|
|
for (unsigned offset=0; offset<origWidth/width; offset++) {
|
|
|
|
|
if ((newMask & Mask) == Mask) {
|
|
|
|
|
if (!TD->isLittleEndian())
|
|
|
|
|
bestOffset = (origWidth/width - offset - 1) * (width/8);
|
|
|
|
|
else
|
|
|
|
|
bestOffset = (uint64_t)offset * (width/8);
|
2010-01-08 04:58:44 +08:00
|
|
|
bestMask = Mask.lshr(offset * (width/8) * 8);
|
2009-07-27 07:47:17 +08:00
|
|
|
bestWidth = width;
|
|
|
|
|
break;
|
2008-11-07 09:28:02 +08:00
|
|
|
}
|
2009-07-27 07:47:17 +08:00
|
|
|
newMask = newMask << width;
|
2008-11-07 09:28:02 +08:00
|
|
|
}
|
|
|
|
|
}
|
2009-07-27 07:47:17 +08:00
|
|
|
}
|
|
|
|
|
if (bestWidth) {
|
2009-08-12 08:36:31 +08:00
|
|
|
EVT newVT = EVT::getIntegerVT(Context, bestWidth);
|
2009-07-27 07:47:17 +08:00
|
|
|
if (newVT.isRound()) {
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT PtrType = Lod->getOperand(1).getValueType();
|
2009-07-27 07:47:17 +08:00
|
|
|
SDValue Ptr = Lod->getBasePtr();
|
|
|
|
|
if (bestOffset != 0)
|
|
|
|
|
Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
|
|
|
|
|
DAG.getConstant(bestOffset, PtrType));
|
|
|
|
|
unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
|
|
|
|
|
SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
|
|
|
|
|
Lod->getSrcValue(),
|
|
|
|
|
Lod->getSrcValueOffset() + bestOffset,
|
2010-02-16 01:00:31 +08:00
|
|
|
false, false, NewAlign);
|
2009-07-27 07:47:17 +08:00
|
|
|
return DAG.getSetCC(dl, VT,
|
|
|
|
|
DAG.getNode(ISD::AND, dl, newVT, NewLoad,
|
2010-01-08 04:58:44 +08:00
|
|
|
DAG.getConstant(bestMask.trunc(bestWidth),
|
|
|
|
|
newVT)),
|
2009-07-27 07:47:17 +08:00
|
|
|
DAG.getConstant(0LL, newVT), Cond);
|
2008-11-07 09:28:02 +08:00
|
|
|
}
|
|
|
|
|
}
|
2009-07-27 07:47:17 +08:00
|
|
|
}
|
2008-11-11 05:22:06 +08:00
|
|
|
|
2009-07-27 07:47:17 +08:00
|
|
|
// If the LHS is a ZERO_EXTEND, perform the comparison on the input.
|
|
|
|
|
if (N0.getOpcode() == ISD::ZERO_EXTEND) {
|
|
|
|
|
unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
|
2007-02-09 06:13:59 +08:00
|
|
|
|
2009-07-27 07:47:17 +08:00
|
|
|
// If the comparison constant has bits in the upper part, the
|
|
|
|
|
// zero-extended value could never match.
|
|
|
|
|
if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
|
|
|
|
|
C1.getBitWidth() - InSize))) {
|
2007-02-09 06:13:59 +08:00
|
|
|
switch (Cond) {
|
|
|
|
|
case ISD::SETUGT:
|
|
|
|
|
case ISD::SETUGE:
|
2009-07-27 07:47:17 +08:00
|
|
|
case ISD::SETEQ: return DAG.getConstant(0, VT);
|
2007-02-09 06:13:59 +08:00
|
|
|
case ISD::SETULT:
|
2009-07-27 07:47:17 +08:00
|
|
|
case ISD::SETULE:
|
|
|
|
|
case ISD::SETNE: return DAG.getConstant(1, VT);
|
|
|
|
|
case ISD::SETGT:
|
|
|
|
|
case ISD::SETGE:
|
|
|
|
|
// True if the sign bit of C1 is set.
|
|
|
|
|
return DAG.getConstant(C1.isNegative(), VT);
|
|
|
|
|
case ISD::SETLT:
|
|
|
|
|
case ISD::SETLE:
|
|
|
|
|
// True if the sign bit of C1 isn't set.
|
|
|
|
|
return DAG.getConstant(C1.isNonNegative(), VT);
|
2007-02-09 06:13:59 +08:00
|
|
|
default:
|
2009-07-27 07:47:17 +08:00
|
|
|
break;
|
2007-02-09 06:13:59 +08:00
|
|
|
}
|
|
|
|
|
}
|
2009-07-27 07:47:17 +08:00
|
|
|
|
|
|
|
|
// Otherwise, we can perform the comparison with the low bits.
|
|
|
|
|
switch (Cond) {
|
|
|
|
|
case ISD::SETEQ:
|
|
|
|
|
case ISD::SETNE:
|
|
|
|
|
case ISD::SETUGT:
|
|
|
|
|
case ISD::SETUGE:
|
|
|
|
|
case ISD::SETULT:
|
|
|
|
|
case ISD::SETULE: {
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT newVT = N0.getOperand(0).getValueType();
|
2009-07-27 07:47:17 +08:00
|
|
|
if (DCI.isBeforeLegalizeOps() ||
|
|
|
|
|
(isOperationLegal(ISD::SETCC, newVT) &&
|
|
|
|
|
getCondCodeAction(Cond, newVT)==Legal))
|
|
|
|
|
return DAG.getSetCC(dl, VT, N0.getOperand(0),
|
|
|
|
|
DAG.getConstant(APInt(C1).trunc(InSize), newVT),
|
|
|
|
|
Cond);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
default:
|
|
|
|
|
break; // todo, be more careful with signed comparisons
|
|
|
|
|
}
|
|
|
|
|
} else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
|
Revert commits 96556 and 96640, because commit 96556 breaks the
dragonegg self-host build. I reverted 96640 in order to revert
96556 (96640 goes on top of 96556), but it also looks like with
both of them applied the breakage happens even earlier. The
symptom of the 96556 miscompile is the following crash:
llvm[3]: Compiling AlphaISelLowering.cpp for Release build
cc1plus: /home/duncan/tmp/tmp/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:4982: void llvm::SelectionDAG::ReplaceAllUsesWith(llvm::SDNode*, llvm::SDNode*, llvm::SelectionDAG::DAGUpdateListener*): Assertion `(!From->hasAnyUseOfValue(i) || From->getValueType(i) == To->getValueType(i)) && "Cannot use this version of ReplaceAllUsesWith!"' failed.
Stack dump:
0. Running pass 'X86 DAG->DAG Instruction Selection' on function '@_ZN4llvm19AlphaTargetLowering14LowerOperationENS_7SDValueERNS_12SelectionDAGE'
g++: Internal error: Aborted (program cc1plus)
This occurs when building LLVM using LLVM built by LLVM (via
dragonegg). Probably LLVM has miscompiled itself, though it
may have miscompiled GCC and/or dragonegg itself: at this point
of the self-host build, all of GCC, LLVM and dragonegg were built
using LLVM. Unfortunately this kind of thing is extremely hard
to debug, and while I did rummage around a bit I didn't find any
smoking guns, aka obviously miscompiled code.
Found by bisection.
r96556 | evancheng | 2010-02-18 03:13:50 +0100 (Thu, 18 Feb 2010) | 5 lines
Some dag combiner goodness:
Transform br (xor (x, y)) -> br (x != y)
Transform br (xor (xor (x,y), 1)) -> br (x == y)
Also normalize (and (X, 1) == / != 1 -> (and (X, 1)) != / == 0 to match to "test on x86" and "tst on arm"
r96640 | evancheng | 2010-02-19 01:34:39 +0100 (Fri, 19 Feb 2010) | 16 lines
Transform (xor (setcc), (setcc)) == / != 1 to
(xor (setcc), (setcc)) != / == 1.
e.g. On x86_64
%0 = icmp eq i32 %x, 0
%1 = icmp eq i32 %y, 0
%2 = xor i1 %1, %0
br i1 %2, label %bb, label %return
=>
testl %edi, %edi
sete %al
testl %esi, %esi
sete %cl
cmpb %al, %cl
je LBB1_2
llvm-svn: 96672
2010-02-19 19:30:41 +08:00
|
|
|
(Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
|
2009-07-27 07:47:17 +08:00
|
|
|
unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT ExtDstTy = N0.getValueType();
|
2009-07-27 07:47:17 +08:00
|
|
|
unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
|
|
|
|
|
|
|
|
|
|
// If the extended part has any inconsistent bits, it cannot ever
|
|
|
|
|
// compare equal. In other words, they have to be all ones or all
|
|
|
|
|
// zeros.
|
|
|
|
|
APInt ExtBits =
|
|
|
|
|
APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits);
|
|
|
|
|
if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
|
|
|
|
|
return DAG.getConstant(Cond == ISD::SETNE, VT);
|
2007-02-09 06:13:59 +08:00
|
|
|
|
2009-07-27 07:47:17 +08:00
|
|
|
SDValue ZextOp;
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT Op0Ty = N0.getOperand(0).getValueType();
|
2009-07-27 07:47:17 +08:00
|
|
|
if (Op0Ty == ExtSrcTy) {
|
|
|
|
|
ZextOp = N0.getOperand(0);
|
2007-02-09 06:13:59 +08:00
|
|
|
} else {
|
2009-07-27 07:47:17 +08:00
|
|
|
APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
|
|
|
|
|
ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
|
|
|
|
|
DAG.getConstant(Imm, Op0Ty));
|
2007-02-09 06:13:59 +08:00
|
|
|
}
|
2009-07-27 07:47:17 +08:00
|
|
|
if (!DCI.isCalledByLegalizer())
|
|
|
|
|
DCI.AddToWorklist(ZextOp.getNode());
|
|
|
|
|
// Otherwise, make this a use of a zext.
|
|
|
|
|
return DAG.getSetCC(dl, VT, ZextOp,
|
|
|
|
|
DAG.getConstant(C1 & APInt::getLowBitsSet(
|
|
|
|
|
ExtDstTyBits,
|
|
|
|
|
ExtSrcTyBits),
|
|
|
|
|
ExtDstTy),
|
|
|
|
|
Cond);
|
|
|
|
|
} else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
|
|
|
|
|
(Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
|
Revert commits 96556 and 96640, because commit 96556 breaks the
dragonegg self-host build. I reverted 96640 in order to revert
96556 (96640 goes on top of 96556), but it also looks like with
both of them applied the breakage happens even earlier. The
symptom of the 96556 miscompile is the following crash:
llvm[3]: Compiling AlphaISelLowering.cpp for Release build
cc1plus: /home/duncan/tmp/tmp/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:4982: void llvm::SelectionDAG::ReplaceAllUsesWith(llvm::SDNode*, llvm::SDNode*, llvm::SelectionDAG::DAGUpdateListener*): Assertion `(!From->hasAnyUseOfValue(i) || From->getValueType(i) == To->getValueType(i)) && "Cannot use this version of ReplaceAllUsesWith!"' failed.
Stack dump:
0. Running pass 'X86 DAG->DAG Instruction Selection' on function '@_ZN4llvm19AlphaTargetLowering14LowerOperationENS_7SDValueERNS_12SelectionDAGE'
g++: Internal error: Aborted (program cc1plus)
This occurs when building LLVM using LLVM built by LLVM (via
dragonegg). Probably LLVM has miscompiled itself, though it
may have miscompiled GCC and/or dragonegg itself: at this point
of the self-host build, all of GCC, LLVM and dragonegg were built
using LLVM. Unfortunately this kind of thing is extremely hard
to debug, and while I did rummage around a bit I didn't find any
smoking guns, aka obviously miscompiled code.
Found by bisection.
r96556 | evancheng | 2010-02-18 03:13:50 +0100 (Thu, 18 Feb 2010) | 5 lines
Some dag combiner goodness:
Transform br (xor (x, y)) -> br (x != y)
Transform br (xor (xor (x,y), 1)) -> br (x == y)
Also normalize (and (X, 1) == / != 1 -> (and (X, 1)) != / == 0 to match to "test on x86" and "tst on arm"
r96640 | evancheng | 2010-02-19 01:34:39 +0100 (Fri, 19 Feb 2010) | 16 lines
Transform (xor (setcc), (setcc)) == / != 1 to
(xor (setcc), (setcc)) != / == 1.
e.g. On x86_64
%0 = icmp eq i32 %x, 0
%1 = icmp eq i32 %y, 0
%2 = xor i1 %1, %0
br i1 %2, label %bb, label %return
=>
testl %edi, %edi
sete %al
testl %esi, %esi
sete %cl
cmpb %al, %cl
je LBB1_2
llvm-svn: 96672
2010-02-19 19:30:41 +08:00
|
|
|
|
2009-07-27 07:47:17 +08:00
|
|
|
// SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
|
|
|
|
|
if (N0.getOpcode() == ISD::SETCC) {
|
2010-01-08 04:58:44 +08:00
|
|
|
bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
|
2009-07-27 07:47:17 +08:00
|
|
|
if (TrueWhenTrue)
|
|
|
|
|
return N0;
|
|
|
|
|
|
|
|
|
|
// Invert the condition.
|
|
|
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
|
|
|
|
|
CC = ISD::getSetCCInverse(CC,
|
|
|
|
|
N0.getOperand(0).getValueType().isInteger());
|
|
|
|
|
return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
|
2007-02-09 06:13:59 +08:00
|
|
|
}
|
Revert commits 96556 and 96640, because commit 96556 breaks the
dragonegg self-host build. I reverted 96640 in order to revert
96556 (96640 goes on top of 96556), but it also looks like with
both of them applied the breakage happens even earlier. The
symptom of the 96556 miscompile is the following crash:
llvm[3]: Compiling AlphaISelLowering.cpp for Release build
cc1plus: /home/duncan/tmp/tmp/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:4982: void llvm::SelectionDAG::ReplaceAllUsesWith(llvm::SDNode*, llvm::SDNode*, llvm::SelectionDAG::DAGUpdateListener*): Assertion `(!From->hasAnyUseOfValue(i) || From->getValueType(i) == To->getValueType(i)) && "Cannot use this version of ReplaceAllUsesWith!"' failed.
Stack dump:
0. Running pass 'X86 DAG->DAG Instruction Selection' on function '@_ZN4llvm19AlphaTargetLowering14LowerOperationENS_7SDValueERNS_12SelectionDAGE'
g++: Internal error: Aborted (program cc1plus)
This occurs when building LLVM using LLVM built by LLVM (via
dragonegg). Probably LLVM has miscompiled itself, though it
may have miscompiled GCC and/or dragonegg itself: at this point
of the self-host build, all of GCC, LLVM and dragonegg were built
using LLVM. Unfortunately this kind of thing is extremely hard
to debug, and while I did rummage around a bit I didn't find any
smoking guns, aka obviously miscompiled code.
Found by bisection.
r96556 | evancheng | 2010-02-18 03:13:50 +0100 (Thu, 18 Feb 2010) | 5 lines
Some dag combiner goodness:
Transform br (xor (x, y)) -> br (x != y)
Transform br (xor (xor (x,y), 1)) -> br (x == y)
Also normalize (and (X, 1) == / != 1 -> (and (X, 1)) != / == 0 to match to "test on x86" and "tst on arm"
r96640 | evancheng | 2010-02-19 01:34:39 +0100 (Fri, 19 Feb 2010) | 16 lines
Transform (xor (setcc), (setcc)) == / != 1 to
(xor (setcc), (setcc)) != / == 1.
e.g. On x86_64
%0 = icmp eq i32 %x, 0
%1 = icmp eq i32 %y, 0
%2 = xor i1 %1, %0
br i1 %2, label %bb, label %return
=>
testl %edi, %edi
sete %al
testl %esi, %esi
sete %cl
cmpb %al, %cl
je LBB1_2
llvm-svn: 96672
2010-02-19 19:30:41 +08:00
|
|
|
|
2009-07-27 07:47:17 +08:00
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if ((N0.getOpcode() == ISD::XOR ||
|
Revert commits 96556 and 96640, because commit 96556 breaks the
dragonegg self-host build. I reverted 96640 in order to revert
96556 (96640 goes on top of 96556), but it also looks like with
both of them applied the breakage happens even earlier. The
symptom of the 96556 miscompile is the following crash:
llvm[3]: Compiling AlphaISelLowering.cpp for Release build
cc1plus: /home/duncan/tmp/tmp/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:4982: void llvm::SelectionDAG::ReplaceAllUsesWith(llvm::SDNode*, llvm::SDNode*, llvm::SelectionDAG::DAGUpdateListener*): Assertion `(!From->hasAnyUseOfValue(i) || From->getValueType(i) == To->getValueType(i)) && "Cannot use this version of ReplaceAllUsesWith!"' failed.
Stack dump:
0. Running pass 'X86 DAG->DAG Instruction Selection' on function '@_ZN4llvm19AlphaTargetLowering14LowerOperationENS_7SDValueERNS_12SelectionDAGE'
g++: Internal error: Aborted (program cc1plus)
This occurs when building LLVM using LLVM built by LLVM (via
dragonegg). Probably LLVM has miscompiled itself, though it
may have miscompiled GCC and/or dragonegg itself: at this point
of the self-host build, all of GCC, LLVM and dragonegg were built
using LLVM. Unfortunately this kind of thing is extremely hard
to debug, and while I did rummage around a bit I didn't find any
smoking guns, aka obviously miscompiled code.
Found by bisection.
r96556 | evancheng | 2010-02-18 03:13:50 +0100 (Thu, 18 Feb 2010) | 5 lines
Some dag combiner goodness:
Transform br (xor (x, y)) -> br (x != y)
Transform br (xor (xor (x,y), 1)) -> br (x == y)
Also normalize (and (X, 1) == / != 1 -> (and (X, 1)) != / == 0 to match to "test on x86" and "tst on arm"
r96640 | evancheng | 2010-02-19 01:34:39 +0100 (Fri, 19 Feb 2010) | 16 lines
Transform (xor (setcc), (setcc)) == / != 1 to
(xor (setcc), (setcc)) != / == 1.
e.g. On x86_64
%0 = icmp eq i32 %x, 0
%1 = icmp eq i32 %y, 0
%2 = xor i1 %1, %0
br i1 %2, label %bb, label %return
=>
testl %edi, %edi
sete %al
testl %esi, %esi
sete %cl
cmpb %al, %cl
je LBB1_2
llvm-svn: 96672
2010-02-19 19:30:41 +08:00
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(N0.getOpcode() == ISD::AND &&
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2009-07-27 07:47:17 +08:00
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N0.getOperand(0).getOpcode() == ISD::XOR &&
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N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
|
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isa<ConstantSDNode>(N0.getOperand(1)) &&
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cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
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// If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
|
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// can only do this if the top bits are known zero.
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unsigned BitWidth = N0.getValueSizeInBits();
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if (DAG.MaskedValueIsZero(N0,
|
|
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APInt::getHighBitsSet(BitWidth,
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|
BitWidth-1))) {
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// Okay, get the un-inverted input value.
|
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SDValue Val;
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if (N0.getOpcode() == ISD::XOR)
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Val = N0.getOperand(0);
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else {
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assert(N0.getOpcode() == ISD::AND &&
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N0.getOperand(0).getOpcode() == ISD::XOR);
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// ((X^1)&1)^1 -> X & 1
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Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
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N0.getOperand(0).getOperand(0),
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N0.getOperand(1));
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}
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return DAG.getSetCC(dl, VT, Val, N1,
|
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Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
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}
|
2007-02-09 06:13:59 +08:00
|
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|
}
|
2009-07-27 07:47:17 +08:00
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}
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APInt MinVal, MaxVal;
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unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
|
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|
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if (ISD::isSignedIntSetCC(Cond)) {
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MinVal = APInt::getSignedMinValue(OperandBitSize);
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MaxVal = APInt::getSignedMaxValue(OperandBitSize);
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} else {
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MinVal = APInt::getMinValue(OperandBitSize);
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MaxVal = APInt::getMaxValue(OperandBitSize);
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|
}
|
2007-02-09 06:13:59 +08:00
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2009-07-27 07:47:17 +08:00
|
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|
// Canonicalize GE/LE comparisons to use GT/LT comparisons.
|
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|
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|
if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
|
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|
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if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
|
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|
|
// X >= C0 --> X > (C0-1)
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|
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return DAG.getSetCC(dl, VT, N0,
|
|
|
|
|
DAG.getConstant(C1-1, N1.getValueType()),
|
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|
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(Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
|
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|
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|
}
|
2007-02-09 06:13:59 +08:00
|
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|
2009-07-27 07:47:17 +08:00
|
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if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
|
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|
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if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
|
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|
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|
// X <= C0 --> X < (C0+1)
|
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|
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|
return DAG.getSetCC(dl, VT, N0,
|
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|
|
|
DAG.getConstant(C1+1, N1.getValueType()),
|
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|
|
|
(Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
|
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|
|
|
}
|
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if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
|
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|
return DAG.getConstant(0, VT); // X < MIN --> false
|
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if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
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return DAG.getConstant(1, VT); // X >= MIN --> true
|
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|
|
if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
|
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|
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|
return DAG.getConstant(0, VT); // X > MAX --> false
|
|
|
|
|
if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
|
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|
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|
return DAG.getConstant(1, VT); // X <= MAX --> true
|
|
|
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|
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|
// Canonicalize setgt X, Min --> setne X, Min
|
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|
|
|
if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
|
|
|
|
|
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
|
|
|
|
|
// Canonicalize setlt X, Max --> setne X, Max
|
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|
|
|
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
|
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|
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|
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
|
|
|
|
|
|
|
|
|
|
// If we have setult X, 1, turn it into seteq X, 0
|
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|
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|
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
|
|
|
|
|
return DAG.getSetCC(dl, VT, N0,
|
|
|
|
|
DAG.getConstant(MinVal, N0.getValueType()),
|
|
|
|
|
ISD::SETEQ);
|
|
|
|
|
// If we have setugt X, Max-1, turn it into seteq X, Max
|
|
|
|
|
else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
|
|
|
|
|
return DAG.getSetCC(dl, VT, N0,
|
|
|
|
|
DAG.getConstant(MaxVal, N0.getValueType()),
|
|
|
|
|
ISD::SETEQ);
|
|
|
|
|
|
|
|
|
|
// If we have "setcc X, C0", check to see if we can shrink the immediate
|
|
|
|
|
// by changing cc.
|
|
|
|
|
|
|
|
|
|
// SETUGT X, SINTMAX -> SETLT X, 0
|
|
|
|
|
if (Cond == ISD::SETUGT &&
|
|
|
|
|
C1 == APInt::getSignedMaxValue(OperandBitSize))
|
|
|
|
|
return DAG.getSetCC(dl, VT, N0,
|
|
|
|
|
DAG.getConstant(0, N1.getValueType()),
|
|
|
|
|
ISD::SETLT);
|
|
|
|
|
|
|
|
|
|
// SETULT X, SINTMIN -> SETGT X, -1
|
|
|
|
|
if (Cond == ISD::SETULT &&
|
|
|
|
|
C1 == APInt::getSignedMinValue(OperandBitSize)) {
|
|
|
|
|
SDValue ConstMinusOne =
|
|
|
|
|
DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
|
|
|
|
|
N1.getValueType());
|
|
|
|
|
return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Fold bit comparisons when we can.
|
|
|
|
|
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
|
2010-01-07 03:38:29 +08:00
|
|
|
(VT == N0.getValueType() ||
|
|
|
|
|
(isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
|
|
|
|
|
N0.getOpcode() == ISD::AND)
|
2009-07-27 07:47:17 +08:00
|
|
|
if (ConstantSDNode *AndRHS =
|
|
|
|
|
dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT ShiftTy = DCI.isBeforeLegalize() ?
|
2009-07-27 07:47:17 +08:00
|
|
|
getPointerTy() : getShiftAmountTy();
|
|
|
|
|
if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
|
|
|
|
|
// Perform the xform if the AND RHS is a single bit.
|
2010-01-08 04:58:44 +08:00
|
|
|
if (AndRHS->getAPIntValue().isPowerOf2()) {
|
2010-01-07 03:38:29 +08:00
|
|
|
return DAG.getNode(ISD::TRUNCATE, dl, VT,
|
|
|
|
|
DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
|
2010-01-08 04:58:44 +08:00
|
|
|
DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
|
2009-07-27 07:47:17 +08:00
|
|
|
}
|
2010-01-08 04:58:44 +08:00
|
|
|
} else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
|
2009-07-27 07:47:17 +08:00
|
|
|
// (X & 8) == 8 --> (X & 8) >> 3
|
|
|
|
|
// Perform the xform if C1 is a single bit.
|
|
|
|
|
if (C1.isPowerOf2()) {
|
2010-01-07 03:38:29 +08:00
|
|
|
return DAG.getNode(ISD::TRUNCATE, dl, VT,
|
|
|
|
|
DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
|
|
|
|
|
DAG.getConstant(C1.logBase2(), ShiftTy)));
|
2007-02-09 06:13:59 +08:00
|
|
|
}
|
|
|
|
|
}
|
2009-07-27 07:47:17 +08:00
|
|
|
}
|
2007-02-09 06:13:59 +08:00
|
|
|
}
|
|
|
|
|
|
2008-08-29 05:40:38 +08:00
|
|
|
if (isa<ConstantFPSDNode>(N0.getNode())) {
|
2007-02-09 06:13:59 +08:00
|
|
|
// Constant fold or commute setcc.
|
2009-02-03 08:47:48 +08:00
|
|
|
SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
|
2008-08-29 05:40:38 +08:00
|
|
|
if (O.getNode()) return O;
|
|
|
|
|
} else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
|
Fold comparisons against a constant nan, and optimize ORD/UNORD
comparisons with a constant. This allows us to compile isnan to:
_foo:
fcmpu cr7, f1, f1
mfcr r2
rlwinm r3, r2, 0, 31, 31
blr
instead of:
LCPI1_0: ; float
.space 4
_foo:
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr7, f1, f0
mfcr r2
rlwinm r3, r2, 0, 31, 31
blr
llvm-svn: 45405
2007-12-29 16:37:08 +08:00
|
|
|
// If the RHS of an FP comparison is a constant, simplify it away in
|
|
|
|
|
// some cases.
|
|
|
|
|
if (CFP->getValueAPF().isNaN()) {
|
|
|
|
|
// If an operand is known to be a nan, we can fold it.
|
|
|
|
|
switch (ISD::getUnorderedFlavor(Cond)) {
|
2009-07-15 00:55:14 +08:00
|
|
|
default: llvm_unreachable("Unknown flavor!");
|
Fold comparisons against a constant nan, and optimize ORD/UNORD
comparisons with a constant. This allows us to compile isnan to:
_foo:
fcmpu cr7, f1, f1
mfcr r2
rlwinm r3, r2, 0, 31, 31
blr
instead of:
LCPI1_0: ; float
.space 4
_foo:
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr7, f1, f0
mfcr r2
rlwinm r3, r2, 0, 31, 31
blr
llvm-svn: 45405
2007-12-29 16:37:08 +08:00
|
|
|
case 0: // Known false.
|
|
|
|
|
return DAG.getConstant(0, VT);
|
|
|
|
|
case 1: // Known true.
|
|
|
|
|
return DAG.getConstant(1, VT);
|
2007-12-31 05:21:10 +08:00
|
|
|
case 2: // Undefined.
|
2009-02-07 07:05:02 +08:00
|
|
|
return DAG.getUNDEF(VT);
|
Fold comparisons against a constant nan, and optimize ORD/UNORD
comparisons with a constant. This allows us to compile isnan to:
_foo:
fcmpu cr7, f1, f1
mfcr r2
rlwinm r3, r2, 0, 31, 31
blr
instead of:
LCPI1_0: ; float
.space 4
_foo:
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr7, f1, f0
mfcr r2
rlwinm r3, r2, 0, 31, 31
blr
llvm-svn: 45405
2007-12-29 16:37:08 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
|
|
|
|
|
// constant if knowing that the operand is non-nan is enough. We prefer to
|
|
|
|
|
// have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
|
|
|
|
|
// materialize 0.0.
|
|
|
|
|
if (Cond == ISD::SETO || Cond == ISD::SETUO)
|
2009-02-03 08:47:48 +08:00
|
|
|
return DAG.getSetCC(dl, VT, N0, N0, Cond);
|
2009-09-26 23:24:17 +08:00
|
|
|
|
|
|
|
|
// If the condition is not legal, see if we can find an equivalent one
|
|
|
|
|
// which is legal.
|
|
|
|
|
if (!isCondCodeLegal(Cond, N0.getValueType())) {
|
|
|
|
|
// If the comparison was an awkward floating-point == or != and one of
|
|
|
|
|
// the comparison operands is infinity or negative infinity, convert the
|
|
|
|
|
// condition to a less-awkward <= or >=.
|
|
|
|
|
if (CFP->getValueAPF().isInfinity()) {
|
|
|
|
|
if (CFP->getValueAPF().isNegative()) {
|
|
|
|
|
if (Cond == ISD::SETOEQ &&
|
|
|
|
|
isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
|
|
|
|
|
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
|
|
|
|
|
if (Cond == ISD::SETUEQ &&
|
|
|
|
|
isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
|
|
|
|
|
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
|
|
|
|
|
if (Cond == ISD::SETUNE &&
|
|
|
|
|
isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
|
|
|
|
|
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
|
|
|
|
|
if (Cond == ISD::SETONE &&
|
|
|
|
|
isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
|
|
|
|
|
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
|
|
|
|
|
} else {
|
|
|
|
|
if (Cond == ISD::SETOEQ &&
|
|
|
|
|
isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
|
|
|
|
|
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
|
|
|
|
|
if (Cond == ISD::SETUEQ &&
|
|
|
|
|
isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
|
|
|
|
|
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
|
|
|
|
|
if (Cond == ISD::SETUNE &&
|
|
|
|
|
isCondCodeLegal(ISD::SETULT, N0.getValueType()))
|
|
|
|
|
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
|
|
|
|
|
if (Cond == ISD::SETONE &&
|
|
|
|
|
isCondCodeLegal(ISD::SETULT, N0.getValueType()))
|
|
|
|
|
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
2007-02-09 06:13:59 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (N0 == N1) {
|
|
|
|
|
// We can always fold X == X for integer setcc's.
|
2008-06-06 20:08:01 +08:00
|
|
|
if (N0.getValueType().isInteger())
|
2007-02-09 06:13:59 +08:00
|
|
|
return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
|
|
|
|
|
unsigned UOF = ISD::getUnorderedFlavor(Cond);
|
|
|
|
|
if (UOF == 2) // FP operators that are undefined on NaNs.
|
|
|
|
|
return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
|
|
|
|
|
if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
|
|
|
|
|
return DAG.getConstant(UOF, VT);
|
|
|
|
|
// Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
|
|
|
|
|
// if it is not already.
|
|
|
|
|
ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
|
|
|
|
|
if (NewCond != Cond)
|
2009-02-03 08:47:48 +08:00
|
|
|
return DAG.getSetCC(dl, VT, N0, N1, NewCond);
|
2007-02-09 06:13:59 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
|
2008-06-06 20:08:01 +08:00
|
|
|
N0.getValueType().isInteger()) {
|
2007-02-09 06:13:59 +08:00
|
|
|
if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
|
|
|
|
|
N0.getOpcode() == ISD::XOR) {
|
|
|
|
|
// Simplify (X+Y) == (X+Z) --> Y == Z
|
|
|
|
|
if (N0.getOpcode() == N1.getOpcode()) {
|
|
|
|
|
if (N0.getOperand(0) == N1.getOperand(0))
|
2009-02-03 08:47:48 +08:00
|
|
|
return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
|
2007-02-09 06:13:59 +08:00
|
|
|
if (N0.getOperand(1) == N1.getOperand(1))
|
2009-02-03 08:47:48 +08:00
|
|
|
return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
|
2007-02-09 06:13:59 +08:00
|
|
|
if (DAG.isCommutativeBinOp(N0.getOpcode())) {
|
|
|
|
|
// If X op Y == Y op X, try other combinations.
|
|
|
|
|
if (N0.getOperand(0) == N1.getOperand(1))
|
2009-02-03 08:47:48 +08:00
|
|
|
return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
|
|
|
|
|
Cond);
|
2007-02-09 06:13:59 +08:00
|
|
|
if (N0.getOperand(1) == N1.getOperand(0))
|
2009-02-03 08:47:48 +08:00
|
|
|
return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
|
|
|
|
|
Cond);
|
2007-02-09 06:13:59 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
|
|
|
|
|
if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
|
|
|
|
|
// Turn (X+C1) == C2 --> X == C2-C1
|
2008-08-29 05:40:38 +08:00
|
|
|
if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
|
2009-02-03 08:47:48 +08:00
|
|
|
return DAG.getSetCC(dl, VT, N0.getOperand(0),
|
2008-09-13 00:56:44 +08:00
|
|
|
DAG.getConstant(RHSC->getAPIntValue()-
|
|
|
|
|
LHSR->getAPIntValue(),
|
2007-02-09 06:13:59 +08:00
|
|
|
N0.getValueType()), Cond);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
|
|
|
|
|
if (N0.getOpcode() == ISD::XOR)
|
|
|
|
|
// If we know that all of the inverted bits are zero, don't bother
|
|
|
|
|
// performing the inversion.
|
2008-02-26 05:11:39 +08:00
|
|
|
if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
|
|
|
|
|
return
|
2009-02-03 08:47:48 +08:00
|
|
|
DAG.getSetCC(dl, VT, N0.getOperand(0),
|
2008-02-26 05:11:39 +08:00
|
|
|
DAG.getConstant(LHSR->getAPIntValue() ^
|
|
|
|
|
RHSC->getAPIntValue(),
|
|
|
|
|
N0.getValueType()),
|
|
|
|
|
Cond);
|
2007-02-09 06:13:59 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Turn (C1-X) == C2 --> X == C1-C2
|
|
|
|
|
if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
|
2008-08-29 05:40:38 +08:00
|
|
|
if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
|
2008-02-26 05:11:39 +08:00
|
|
|
return
|
2009-02-03 08:47:48 +08:00
|
|
|
DAG.getSetCC(dl, VT, N0.getOperand(1),
|
2008-02-26 05:11:39 +08:00
|
|
|
DAG.getConstant(SUBC->getAPIntValue() -
|
|
|
|
|
RHSC->getAPIntValue(),
|
|
|
|
|
N0.getValueType()),
|
|
|
|
|
Cond);
|
2007-02-09 06:13:59 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Simplify (X+Z) == X --> Z == 0
|
|
|
|
|
if (N0.getOperand(0) == N1)
|
2009-02-03 08:47:48 +08:00
|
|
|
return DAG.getSetCC(dl, VT, N0.getOperand(1),
|
2007-02-09 06:13:59 +08:00
|
|
|
DAG.getConstant(0, N0.getValueType()), Cond);
|
|
|
|
|
if (N0.getOperand(1) == N1) {
|
|
|
|
|
if (DAG.isCommutativeBinOp(N0.getOpcode()))
|
2009-02-03 08:47:48 +08:00
|
|
|
return DAG.getSetCC(dl, VT, N0.getOperand(0),
|
2007-02-09 06:13:59 +08:00
|
|
|
DAG.getConstant(0, N0.getValueType()), Cond);
|
2008-08-29 05:40:38 +08:00
|
|
|
else if (N0.getNode()->hasOneUse()) {
|
2007-02-09 06:13:59 +08:00
|
|
|
assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
|
|
|
|
|
// (Z-X) == X --> Z == X<<1
|
2009-02-03 08:47:48 +08:00
|
|
|
SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
|
2007-02-09 06:13:59 +08:00
|
|
|
N1,
|
|
|
|
|
DAG.getConstant(1, getShiftAmountTy()));
|
|
|
|
|
if (!DCI.isCalledByLegalizer())
|
2008-08-29 05:40:38 +08:00
|
|
|
DCI.AddToWorklist(SH.getNode());
|
2009-02-03 08:47:48 +08:00
|
|
|
return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
|
2007-02-09 06:13:59 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
|
|
|
|
|
N1.getOpcode() == ISD::XOR) {
|
|
|
|
|
// Simplify X == (X+Z) --> Z == 0
|
|
|
|
|
if (N1.getOperand(0) == N0) {
|
2009-02-03 08:47:48 +08:00
|
|
|
return DAG.getSetCC(dl, VT, N1.getOperand(1),
|
2007-02-09 06:13:59 +08:00
|
|
|
DAG.getConstant(0, N1.getValueType()), Cond);
|
|
|
|
|
} else if (N1.getOperand(1) == N0) {
|
|
|
|
|
if (DAG.isCommutativeBinOp(N1.getOpcode())) {
|
2009-02-03 08:47:48 +08:00
|
|
|
return DAG.getSetCC(dl, VT, N1.getOperand(0),
|
2007-02-09 06:13:59 +08:00
|
|
|
DAG.getConstant(0, N1.getValueType()), Cond);
|
2008-08-29 05:40:38 +08:00
|
|
|
} else if (N1.getNode()->hasOneUse()) {
|
2007-02-09 06:13:59 +08:00
|
|
|
assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
|
|
|
|
|
// X == (Z-X) --> X<<1 == Z
|
2009-02-03 08:47:48 +08:00
|
|
|
SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
|
2007-02-09 06:13:59 +08:00
|
|
|
DAG.getConstant(1, getShiftAmountTy()));
|
|
|
|
|
if (!DCI.isCalledByLegalizer())
|
2008-08-29 05:40:38 +08:00
|
|
|
DCI.AddToWorklist(SH.getNode());
|
2009-02-03 08:47:48 +08:00
|
|
|
return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
|
2007-02-09 06:13:59 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
2009-01-29 09:59:02 +08:00
|
|
|
|
2009-01-30 00:18:12 +08:00
|
|
|
// Simplify x&y == y to x&y != 0 if y has exactly one bit set.
|
2009-02-12 03:19:41 +08:00
|
|
|
// Note that where y is variable and is known to have at most
|
|
|
|
|
// one bit set (for example, if it is z&1) we cannot do this;
|
|
|
|
|
// the expressions are not equivalent when y==0.
|
2009-01-29 09:59:02 +08:00
|
|
|
if (N0.getOpcode() == ISD::AND)
|
|
|
|
|
if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
|
2009-02-12 03:19:41 +08:00
|
|
|
if (ValueHasExactlyOneBitSet(N1, DAG)) {
|
2009-01-29 09:59:02 +08:00
|
|
|
Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
|
|
|
|
|
SDValue Zero = DAG.getConstant(0, N1.getValueType());
|
2009-02-03 08:47:48 +08:00
|
|
|
return DAG.getSetCC(dl, VT, N0, Zero, Cond);
|
2009-01-29 09:59:02 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (N1.getOpcode() == ISD::AND)
|
|
|
|
|
if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
|
2009-02-12 03:19:41 +08:00
|
|
|
if (ValueHasExactlyOneBitSet(N0, DAG)) {
|
2009-01-29 09:59:02 +08:00
|
|
|
Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
|
|
|
|
|
SDValue Zero = DAG.getConstant(0, N0.getValueType());
|
2009-02-03 08:47:48 +08:00
|
|
|
return DAG.getSetCC(dl, VT, N1, Zero, Cond);
|
2009-01-29 09:59:02 +08:00
|
|
|
}
|
|
|
|
|
}
|
2007-02-09 06:13:59 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Fold away ALL boolean setcc's.
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue Temp;
|
2009-08-12 04:47:22 +08:00
|
|
|
if (N0.getValueType() == MVT::i1 && foldBooleans) {
|
2007-02-09 06:13:59 +08:00
|
|
|
switch (Cond) {
|
2009-07-15 00:55:14 +08:00
|
|
|
default: llvm_unreachable("Unknown integer setcc!");
|
2009-01-23 01:39:32 +08:00
|
|
|
case ISD::SETEQ: // X == Y -> ~(X^Y)
|
2009-08-12 04:47:22 +08:00
|
|
|
Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
|
|
|
|
|
N0 = DAG.getNOT(dl, Temp, MVT::i1);
|
2007-02-09 06:13:59 +08:00
|
|
|
if (!DCI.isCalledByLegalizer())
|
2008-08-29 05:40:38 +08:00
|
|
|
DCI.AddToWorklist(Temp.getNode());
|
2007-02-09 06:13:59 +08:00
|
|
|
break;
|
|
|
|
|
case ISD::SETNE: // X != Y --> (X^Y)
|
2009-08-12 04:47:22 +08:00
|
|
|
N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
|
2007-02-09 06:13:59 +08:00
|
|
|
break;
|
2009-01-23 01:39:32 +08:00
|
|
|
case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
|
|
|
|
|
case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
|
2009-08-12 04:47:22 +08:00
|
|
|
Temp = DAG.getNOT(dl, N0, MVT::i1);
|
|
|
|
|
N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
|
2007-02-09 06:13:59 +08:00
|
|
|
if (!DCI.isCalledByLegalizer())
|
2008-08-29 05:40:38 +08:00
|
|
|
DCI.AddToWorklist(Temp.getNode());
|
2007-02-09 06:13:59 +08:00
|
|
|
break;
|
2009-01-23 01:39:32 +08:00
|
|
|
case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
|
|
|
|
|
case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
|
2009-08-12 04:47:22 +08:00
|
|
|
Temp = DAG.getNOT(dl, N1, MVT::i1);
|
|
|
|
|
N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
|
2007-02-09 06:13:59 +08:00
|
|
|
if (!DCI.isCalledByLegalizer())
|
2008-08-29 05:40:38 +08:00
|
|
|
DCI.AddToWorklist(Temp.getNode());
|
2007-02-09 06:13:59 +08:00
|
|
|
break;
|
2009-01-23 01:39:32 +08:00
|
|
|
case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
|
|
|
|
|
case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
|
2009-08-12 04:47:22 +08:00
|
|
|
Temp = DAG.getNOT(dl, N0, MVT::i1);
|
|
|
|
|
N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
|
2007-02-09 06:13:59 +08:00
|
|
|
if (!DCI.isCalledByLegalizer())
|
2008-08-29 05:40:38 +08:00
|
|
|
DCI.AddToWorklist(Temp.getNode());
|
2007-02-09 06:13:59 +08:00
|
|
|
break;
|
2009-01-23 01:39:32 +08:00
|
|
|
case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
|
|
|
|
|
case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
|
2009-08-12 04:47:22 +08:00
|
|
|
Temp = DAG.getNOT(dl, N1, MVT::i1);
|
|
|
|
|
N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
|
2007-02-09 06:13:59 +08:00
|
|
|
break;
|
|
|
|
|
}
|
2009-08-12 04:47:22 +08:00
|
|
|
if (VT != MVT::i1) {
|
2007-02-09 06:13:59 +08:00
|
|
|
if (!DCI.isCalledByLegalizer())
|
2008-08-29 05:40:38 +08:00
|
|
|
DCI.AddToWorklist(N0.getNode());
|
2007-02-09 06:13:59 +08:00
|
|
|
// FIXME: If running after legalize, we probably can't do this.
|
2009-02-03 08:47:48 +08:00
|
|
|
N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
|
2007-02-09 06:13:59 +08:00
|
|
|
}
|
|
|
|
|
return N0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Could not fold it.
|
2008-07-28 05:46:04 +08:00
|
|
|
return SDValue();
|
2007-02-09 06:13:59 +08:00
|
|
|
}
|
|
|
|
|
|
2008-05-13 03:56:52 +08:00
|
|
|
/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
|
|
|
|
|
/// node is a GlobalAddress + offset.
|
|
|
|
|
bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA,
|
|
|
|
|
int64_t &Offset) const {
|
|
|
|
|
if (isa<GlobalAddressSDNode>(N)) {
|
2008-06-10 06:05:52 +08:00
|
|
|
GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
|
|
|
|
|
GA = GASD->getGlobal();
|
|
|
|
|
Offset += GASD->getOffset();
|
2008-05-13 03:56:52 +08:00
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (N->getOpcode() == ISD::ADD) {
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue N1 = N->getOperand(0);
|
|
|
|
|
SDValue N2 = N->getOperand(1);
|
2008-08-29 05:40:38 +08:00
|
|
|
if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
|
2008-05-13 03:56:52 +08:00
|
|
|
ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
|
|
|
|
|
if (V) {
|
2008-09-27 05:54:37 +08:00
|
|
|
Offset += V->getSExtValue();
|
2008-05-13 03:56:52 +08:00
|
|
|
return true;
|
|
|
|
|
}
|
2008-08-29 05:40:38 +08:00
|
|
|
} else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
|
2008-05-13 03:56:52 +08:00
|
|
|
ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
|
|
|
|
|
if (V) {
|
2008-09-27 05:54:37 +08:00
|
|
|
Offset += V->getSExtValue();
|
2008-05-13 03:56:52 +08:00
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue TargetLowering::
|
2006-03-01 12:52:55 +08:00
|
|
|
PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
|
|
|
|
|
// Default implementation: no optimization.
|
2008-07-28 05:46:04 +08:00
|
|
|
return SDValue();
|
2006-03-01 12:52:55 +08:00
|
|
|
}
|
|
|
|
|
|
2006-02-04 10:13:02 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// Inline Assembler Implementation Methods
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
2008-04-27 08:09:47 +08:00
|
|
|
|
2006-02-04 10:13:02 +08:00
|
|
|
TargetLowering::ConstraintType
|
2007-03-25 10:14:49 +08:00
|
|
|
TargetLowering::getConstraintType(const std::string &Constraint) const {
|
2006-02-04 10:13:02 +08:00
|
|
|
// FIXME: lots more standard ones to handle.
|
2007-03-25 10:14:49 +08:00
|
|
|
if (Constraint.size() == 1) {
|
|
|
|
|
switch (Constraint[0]) {
|
|
|
|
|
default: break;
|
|
|
|
|
case 'r': return C_RegisterClass;
|
|
|
|
|
case 'm': // memory
|
|
|
|
|
case 'o': // offsetable
|
|
|
|
|
case 'V': // not offsetable
|
|
|
|
|
return C_Memory;
|
|
|
|
|
case 'i': // Simple Integer or Relocatable Constant
|
|
|
|
|
case 'n': // Simple Integer
|
|
|
|
|
case 's': // Relocatable Constant
|
2007-03-25 12:35:41 +08:00
|
|
|
case 'X': // Allow ANY value.
|
2007-03-25 10:14:49 +08:00
|
|
|
case 'I': // Target registers.
|
|
|
|
|
case 'J':
|
|
|
|
|
case 'K':
|
|
|
|
|
case 'L':
|
|
|
|
|
case 'M':
|
|
|
|
|
case 'N':
|
|
|
|
|
case 'O':
|
|
|
|
|
case 'P':
|
|
|
|
|
return C_Other;
|
|
|
|
|
}
|
2006-02-04 10:13:02 +08:00
|
|
|
}
|
2007-03-25 10:18:14 +08:00
|
|
|
|
|
|
|
|
if (Constraint.size() > 1 && Constraint[0] == '{' &&
|
|
|
|
|
Constraint[Constraint.size()-1] == '}')
|
|
|
|
|
return C_Register;
|
2007-03-25 10:14:49 +08:00
|
|
|
return C_Unknown;
|
2006-02-04 10:13:02 +08:00
|
|
|
}
|
|
|
|
|
|
2008-01-29 10:21:21 +08:00
|
|
|
/// LowerXConstraint - try to replace an X constraint, which matches anything,
|
|
|
|
|
/// with another that has more specific requirements based on the type of the
|
|
|
|
|
/// corresponding operand.
|
2009-08-11 06:56:29 +08:00
|
|
|
const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
|
2008-06-06 20:08:01 +08:00
|
|
|
if (ConstraintVT.isInteger())
|
2008-04-27 07:02:14 +08:00
|
|
|
return "r";
|
2008-06-06 20:08:01 +08:00
|
|
|
if (ConstraintVT.isFloatingPoint())
|
2008-04-27 07:02:14 +08:00
|
|
|
return "f"; // works for many targets
|
|
|
|
|
return 0;
|
2008-01-29 10:21:21 +08:00
|
|
|
}
|
|
|
|
|
|
2007-08-25 08:47:38 +08:00
|
|
|
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
|
|
|
|
|
/// vector. If it is invalid, don't add anything to Ops.
|
2008-07-28 05:46:04 +08:00
|
|
|
void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
|
2007-08-25 08:47:38 +08:00
|
|
|
char ConstraintLetter,
|
2008-09-24 08:05:32 +08:00
|
|
|
bool hasMemory,
|
2008-07-28 05:46:04 +08:00
|
|
|
std::vector<SDValue> &Ops,
|
2008-04-27 07:02:14 +08:00
|
|
|
SelectionDAG &DAG) const {
|
2006-02-04 10:13:02 +08:00
|
|
|
switch (ConstraintLetter) {
|
2007-02-17 14:00:35 +08:00
|
|
|
default: break;
|
2007-11-06 05:20:28 +08:00
|
|
|
case 'X': // Allows any operand; labels (basic block) use this.
|
|
|
|
|
if (Op.getOpcode() == ISD::BasicBlock) {
|
|
|
|
|
Ops.push_back(Op);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
// fall through
|
2006-02-04 10:13:02 +08:00
|
|
|
case 'i': // Simple Integer or Relocatable Constant
|
|
|
|
|
case 'n': // Simple Integer
|
2007-11-06 05:20:28 +08:00
|
|
|
case 's': { // Relocatable Constant
|
2007-05-04 00:54:34 +08:00
|
|
|
// These operands are interested in values of the form (GV+C), where C may
|
|
|
|
|
// be folded in as an offset of GV, or it may be explicitly added. Also, it
|
|
|
|
|
// is possible and fine if either GV or C are missing.
|
|
|
|
|
ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
|
|
|
|
|
GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
|
|
|
|
|
|
|
|
|
|
// If we have "(add GV, C)", pull out GV/C
|
|
|
|
|
if (Op.getOpcode() == ISD::ADD) {
|
|
|
|
|
C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
|
|
|
|
|
GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
|
|
|
|
|
if (C == 0 || GA == 0) {
|
|
|
|
|
C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
|
|
|
|
|
GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
|
|
|
|
|
}
|
|
|
|
|
if (C == 0 || GA == 0)
|
|
|
|
|
C = 0, GA = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// If we find a valid operand, map to the TargetXXX version so that the
|
|
|
|
|
// value itself doesn't get selected.
|
|
|
|
|
if (GA) { // Either &GV or &GV+C
|
|
|
|
|
if (ConstraintLetter != 'n') {
|
|
|
|
|
int64_t Offs = GA->getOffset();
|
2008-09-13 00:56:44 +08:00
|
|
|
if (C) Offs += C->getZExtValue();
|
2007-08-25 08:47:38 +08:00
|
|
|
Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
|
|
|
|
|
Op.getValueType(), Offs));
|
|
|
|
|
return;
|
2007-05-04 00:54:34 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (C) { // just C, no GV.
|
2007-02-17 14:00:35 +08:00
|
|
|
// Simple constants are not allowed for 's'.
|
2007-08-25 08:47:38 +08:00
|
|
|
if (ConstraintLetter != 's') {
|
2009-02-13 04:58:09 +08:00
|
|
|
// gcc prints these as sign extended. Sign extend value to 64 bits
|
|
|
|
|
// now; without this it would get ZExt'd later in
|
|
|
|
|
// ScheduleDAGSDNodes::EmitNode, which is very generic.
|
|
|
|
|
Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
|
2009-08-12 04:47:22 +08:00
|
|
|
MVT::i64));
|
2007-08-25 08:47:38 +08:00
|
|
|
return;
|
|
|
|
|
}
|
2007-02-17 14:00:35 +08:00
|
|
|
}
|
|
|
|
|
break;
|
2006-02-04 10:13:02 +08:00
|
|
|
}
|
2007-05-04 00:54:34 +08:00
|
|
|
}
|
2006-02-04 10:13:02 +08:00
|
|
|
}
|
|
|
|
|
|
2006-01-27 04:37:03 +08:00
|
|
|
std::vector<unsigned> TargetLowering::
|
2006-02-22 08:56:39 +08:00
|
|
|
getRegClassForInlineAsmConstraint(const std::string &Constraint,
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT VT) const {
|
2006-02-22 08:56:39 +08:00
|
|
|
return std::vector<unsigned>();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
|
2006-02-22 07:11:00 +08:00
|
|
|
getRegForInlineAsmConstraint(const std::string &Constraint,
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT VT) const {
|
2006-02-22 08:56:39 +08:00
|
|
|
if (Constraint[0] != '{')
|
|
|
|
|
return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
|
2006-02-01 09:29:47 +08:00
|
|
|
assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
|
|
|
|
|
|
|
|
|
|
// Remove the braces from around the name.
|
2009-11-13 04:36:59 +08:00
|
|
|
StringRef RegName(Constraint.data()+1, Constraint.size()-2);
|
2006-02-22 08:56:39 +08:00
|
|
|
|
|
|
|
|
// Figure out which register class contains this reg.
|
2008-02-11 02:45:23 +08:00
|
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
|
|
|
|
for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
|
2006-02-22 08:56:39 +08:00
|
|
|
E = RI->regclass_end(); RCI != E; ++RCI) {
|
|
|
|
|
const TargetRegisterClass *RC = *RCI;
|
2006-02-23 07:00:51 +08:00
|
|
|
|
2010-02-11 00:03:48 +08:00
|
|
|
// If none of the value types for this register class are valid, we
|
2006-02-23 07:00:51 +08:00
|
|
|
// can't use it. For example, 64-bit reg classes on 32-bit targets.
|
|
|
|
|
bool isLegal = false;
|
|
|
|
|
for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
|
|
|
|
|
I != E; ++I) {
|
|
|
|
|
if (isTypeLegal(*I)) {
|
|
|
|
|
isLegal = true;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (!isLegal) continue;
|
|
|
|
|
|
2006-02-22 08:56:39 +08:00
|
|
|
for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
|
|
|
|
|
I != E; ++I) {
|
2009-11-13 04:36:59 +08:00
|
|
|
if (RegName.equals_lower(RI->getName(*I)))
|
2006-02-22 08:56:39 +08:00
|
|
|
return std::make_pair(*I, RC);
|
|
|
|
|
}
|
2006-01-27 04:37:03 +08:00
|
|
|
}
|
2006-02-01 09:29:47 +08:00
|
|
|
|
2006-02-22 08:56:39 +08:00
|
|
|
return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
|
2006-01-27 04:37:03 +08:00
|
|
|
}
|
2006-03-14 07:18:16 +08:00
|
|
|
|
2008-04-27 08:09:47 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// Constraint Selection.
|
|
|
|
|
|
2008-10-18 00:47:46 +08:00
|
|
|
/// isMatchingInputConstraint - Return true of this is an input operand that is
|
|
|
|
|
/// a matching constraint like "4".
|
|
|
|
|
bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
|
2008-10-18 00:21:11 +08:00
|
|
|
assert(!ConstraintCode.empty() && "No known constraint!");
|
|
|
|
|
return isdigit(ConstraintCode[0]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/// getMatchedOperand - If this is an input matching constraint, this method
|
|
|
|
|
/// returns the output operand it matches.
|
|
|
|
|
unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
|
|
|
|
|
assert(!ConstraintCode.empty() && "No known constraint!");
|
|
|
|
|
return atoi(ConstraintCode.c_str());
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2008-04-27 08:09:47 +08:00
|
|
|
/// getConstraintGenerality - Return an integer indicating how general CT
|
|
|
|
|
/// is.
|
|
|
|
|
static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
|
|
|
|
|
switch (CT) {
|
2009-07-15 00:55:14 +08:00
|
|
|
default: llvm_unreachable("Unknown constraint type!");
|
2008-04-27 08:09:47 +08:00
|
|
|
case TargetLowering::C_Other:
|
|
|
|
|
case TargetLowering::C_Unknown:
|
|
|
|
|
return 0;
|
|
|
|
|
case TargetLowering::C_Register:
|
|
|
|
|
return 1;
|
|
|
|
|
case TargetLowering::C_RegisterClass:
|
|
|
|
|
return 2;
|
|
|
|
|
case TargetLowering::C_Memory:
|
|
|
|
|
return 3;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/// ChooseConstraint - If there are multiple different constraints that we
|
|
|
|
|
/// could pick for this operand (e.g. "imr") try to pick the 'best' one.
|
2008-04-27 09:49:46 +08:00
|
|
|
/// This is somewhat tricky: constraints fall into four classes:
|
2008-04-27 08:09:47 +08:00
|
|
|
/// Other -> immediates and magic values
|
|
|
|
|
/// Register -> one specific register
|
|
|
|
|
/// RegisterClass -> a group of regs
|
|
|
|
|
/// Memory -> memory
|
|
|
|
|
/// Ideally, we would pick the most specific constraint possible: if we have
|
|
|
|
|
/// something that fits into a register, we would pick it. The problem here
|
|
|
|
|
/// is that if we have something that could either be in a register or in
|
|
|
|
|
/// memory that use of the register could cause selection of *other*
|
|
|
|
|
/// operands to fail: they might only succeed if we pick memory. Because of
|
|
|
|
|
/// this the heuristic we use is:
|
|
|
|
|
///
|
|
|
|
|
/// 1) If there is an 'other' constraint, and if the operand is valid for
|
|
|
|
|
/// that constraint, use it. This makes us take advantage of 'i'
|
|
|
|
|
/// constraints when available.
|
|
|
|
|
/// 2) Otherwise, pick the most general constraint present. This prefers
|
|
|
|
|
/// 'm' over 'r', for example.
|
|
|
|
|
///
|
|
|
|
|
static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
|
2008-09-24 08:05:32 +08:00
|
|
|
bool hasMemory, const TargetLowering &TLI,
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue Op, SelectionDAG *DAG) {
|
2008-04-27 08:09:47 +08:00
|
|
|
assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
|
|
|
|
|
unsigned BestIdx = 0;
|
|
|
|
|
TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
|
|
|
|
|
int BestGenerality = -1;
|
|
|
|
|
|
|
|
|
|
// Loop over the options, keeping track of the most general one.
|
|
|
|
|
for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
|
|
|
|
|
TargetLowering::ConstraintType CType =
|
|
|
|
|
TLI.getConstraintType(OpInfo.Codes[i]);
|
|
|
|
|
|
2008-04-27 08:37:18 +08:00
|
|
|
// If this is an 'other' constraint, see if the operand is valid for it.
|
|
|
|
|
// For example, on X86 we might have an 'rI' constraint. If the operand
|
|
|
|
|
// is an integer in the range [0..31] we want to use I (saving a load
|
|
|
|
|
// of a register), otherwise we must use 'r'.
|
2008-08-29 05:40:38 +08:00
|
|
|
if (CType == TargetLowering::C_Other && Op.getNode()) {
|
2008-04-27 08:37:18 +08:00
|
|
|
assert(OpInfo.Codes[i].size() == 1 &&
|
|
|
|
|
"Unhandled multi-letter 'other' constraint");
|
2008-07-28 05:46:04 +08:00
|
|
|
std::vector<SDValue> ResultOps;
|
2008-09-24 08:05:32 +08:00
|
|
|
TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory,
|
2008-04-27 08:37:18 +08:00
|
|
|
ResultOps, *DAG);
|
|
|
|
|
if (!ResultOps.empty()) {
|
|
|
|
|
BestType = CType;
|
|
|
|
|
BestIdx = i;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2008-04-27 08:09:47 +08:00
|
|
|
// This constraint letter is more general than the previous one, use it.
|
|
|
|
|
int Generality = getConstraintGenerality(CType);
|
|
|
|
|
if (Generality > BestGenerality) {
|
|
|
|
|
BestType = CType;
|
|
|
|
|
BestIdx = i;
|
|
|
|
|
BestGenerality = Generality;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
|
|
|
|
|
OpInfo.ConstraintType = BestType;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/// ComputeConstraintToUse - Determines the constraint code and constraint
|
|
|
|
|
/// type to use for the specific AsmOperandInfo, setting
|
|
|
|
|
/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
|
2008-04-27 08:37:18 +08:00
|
|
|
void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue Op,
|
2008-09-24 08:05:32 +08:00
|
|
|
bool hasMemory,
|
2008-04-27 08:37:18 +08:00
|
|
|
SelectionDAG *DAG) const {
|
2008-04-27 08:09:47 +08:00
|
|
|
assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
|
|
|
|
|
|
|
|
|
|
// Single-letter constraints ('r') are very common.
|
|
|
|
|
if (OpInfo.Codes.size() == 1) {
|
|
|
|
|
OpInfo.ConstraintCode = OpInfo.Codes[0];
|
|
|
|
|
OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
|
|
|
|
|
} else {
|
2008-09-24 08:05:32 +08:00
|
|
|
ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG);
|
2008-04-27 08:09:47 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// 'X' matches anything.
|
|
|
|
|
if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
|
|
|
|
|
// Labels and constants are handled elsewhere ('X' is the only thing
|
2009-07-08 07:26:33 +08:00
|
|
|
// that matches labels). For Functions, the type here is the type of
|
2009-07-21 07:27:39 +08:00
|
|
|
// the result, which is not what we want to look at; leave them alone.
|
|
|
|
|
Value *v = OpInfo.CallOperandVal;
|
2009-07-08 07:26:33 +08:00
|
|
|
if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
|
|
|
|
|
OpInfo.CallOperandVal = v;
|
2008-04-27 08:09:47 +08:00
|
|
|
return;
|
2009-07-08 07:26:33 +08:00
|
|
|
}
|
2008-04-27 08:09:47 +08:00
|
|
|
|
|
|
|
|
// Otherwise, try to resolve it to something we know about by looking at
|
|
|
|
|
// the actual operand type.
|
|
|
|
|
if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
|
|
|
|
|
OpInfo.ConstraintCode = Repl;
|
|
|
|
|
OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2006-03-14 07:18:16 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// Loop Strength Reduction hooks
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
2007-03-31 07:14:50 +08:00
|
|
|
/// isLegalAddressingMode - Return true if the addressing mode represented
|
|
|
|
|
/// by AM is legal for this target, for a load/store of the specified type.
|
|
|
|
|
bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
|
|
|
|
|
const Type *Ty) const {
|
|
|
|
|
// The default implementation of this implements a conservative RISCy, r+r and
|
|
|
|
|
// r+i addr mode.
|
|
|
|
|
|
|
|
|
|
// Allows a sign-extended 16-bit immediate field.
|
|
|
|
|
if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
// No global is ever allowed as a base.
|
|
|
|
|
if (AM.BaseGV)
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
// Only support r+r,
|
|
|
|
|
switch (AM.Scale) {
|
|
|
|
|
case 0: // "r+i" or just "i", depending on HasBaseReg.
|
|
|
|
|
break;
|
|
|
|
|
case 1:
|
|
|
|
|
if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
|
|
|
|
|
return false;
|
|
|
|
|
// Otherwise we have r+r or r+i.
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
|
|
|
|
|
return false;
|
|
|
|
|
// Allow 2*r as r+r.
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
2006-05-17 01:42:15 +08:00
|
|
|
/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
|
|
|
|
|
/// return a DAG expression to select that will generate the same value by
|
|
|
|
|
/// multiplying by a magic number. See:
|
|
|
|
|
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
|
|
|
|
|
std::vector<SDNode*>* Created) const {
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT VT = N->getValueType(0);
|
2009-02-03 08:47:48 +08:00
|
|
|
DebugLoc dl= N->getDebugLoc();
|
2006-05-17 01:42:15 +08:00
|
|
|
|
|
|
|
|
// Check to see if we can do this.
|
2008-11-30 14:35:39 +08:00
|
|
|
// FIXME: We should be more aggressive here.
|
|
|
|
|
if (!isTypeLegal(VT))
|
|
|
|
|
return SDValue();
|
2006-05-17 01:42:15 +08:00
|
|
|
|
2008-11-30 14:35:39 +08:00
|
|
|
APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
|
2009-04-30 18:15:35 +08:00
|
|
|
APInt::ms magics = d.magic();
|
2006-05-17 01:42:15 +08:00
|
|
|
|
|
|
|
|
// Multiply the numerator (operand 0) by the magic value
|
2008-11-30 14:35:39 +08:00
|
|
|
// FIXME: We should support doing a MUL in a wider type
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue Q;
|
2009-01-29 01:46:25 +08:00
|
|
|
if (isOperationLegalOrCustom(ISD::MULHS, VT))
|
2009-02-03 08:47:48 +08:00
|
|
|
Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
|
2007-10-09 02:33:35 +08:00
|
|
|
DAG.getConstant(magics.m, VT));
|
2009-01-29 01:46:25 +08:00
|
|
|
else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
|
2009-02-03 08:47:48 +08:00
|
|
|
Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
|
2007-10-09 02:33:35 +08:00
|
|
|
N->getOperand(0),
|
2008-08-29 05:40:38 +08:00
|
|
|
DAG.getConstant(magics.m, VT)).getNode(), 1);
|
2007-10-09 02:33:35 +08:00
|
|
|
else
|
2008-07-28 05:46:04 +08:00
|
|
|
return SDValue(); // No mulhs or equvialent
|
2006-05-17 01:42:15 +08:00
|
|
|
// If d > 0 and m < 0, add the numerator
|
2008-11-30 14:35:39 +08:00
|
|
|
if (d.isStrictlyPositive() && magics.m.isNegative()) {
|
2009-02-03 08:47:48 +08:00
|
|
|
Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
|
2006-05-17 01:42:15 +08:00
|
|
|
if (Created)
|
2008-08-29 05:40:38 +08:00
|
|
|
Created->push_back(Q.getNode());
|
2006-05-17 01:42:15 +08:00
|
|
|
}
|
|
|
|
|
// If d < 0 and m > 0, subtract the numerator.
|
2008-11-30 14:35:39 +08:00
|
|
|
if (d.isNegative() && magics.m.isStrictlyPositive()) {
|
2009-02-03 08:47:48 +08:00
|
|
|
Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
|
2006-05-17 01:42:15 +08:00
|
|
|
if (Created)
|
2008-08-29 05:40:38 +08:00
|
|
|
Created->push_back(Q.getNode());
|
2006-05-17 01:42:15 +08:00
|
|
|
}
|
|
|
|
|
// Shift right algebraic if shift value is nonzero
|
|
|
|
|
if (magics.s > 0) {
|
2009-02-03 08:47:48 +08:00
|
|
|
Q = DAG.getNode(ISD::SRA, dl, VT, Q,
|
2006-05-17 01:42:15 +08:00
|
|
|
DAG.getConstant(magics.s, getShiftAmountTy()));
|
|
|
|
|
if (Created)
|
2008-08-29 05:40:38 +08:00
|
|
|
Created->push_back(Q.getNode());
|
2006-05-17 01:42:15 +08:00
|
|
|
}
|
|
|
|
|
// Extract the sign bit and add it to the quotient
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue T =
|
2009-02-03 08:47:48 +08:00
|
|
|
DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
|
2006-05-17 01:42:15 +08:00
|
|
|
getShiftAmountTy()));
|
|
|
|
|
if (Created)
|
2008-08-29 05:40:38 +08:00
|
|
|
Created->push_back(T.getNode());
|
2009-02-03 08:47:48 +08:00
|
|
|
return DAG.getNode(ISD::ADD, dl, VT, Q, T);
|
2006-05-17 01:42:15 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
|
|
|
|
|
/// return a DAG expression to select that will generate the same value by
|
|
|
|
|
/// multiplying by a magic number. See:
|
|
|
|
|
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
|
|
|
|
|
std::vector<SDNode*>* Created) const {
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT VT = N->getValueType(0);
|
2009-02-03 08:47:48 +08:00
|
|
|
DebugLoc dl = N->getDebugLoc();
|
2008-11-30 14:02:26 +08:00
|
|
|
|
2006-05-17 01:42:15 +08:00
|
|
|
// Check to see if we can do this.
|
2008-11-30 14:02:26 +08:00
|
|
|
// FIXME: We should be more aggressive here.
|
|
|
|
|
if (!isTypeLegal(VT))
|
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
|
|
// FIXME: We should use a narrower constant when the upper
|
|
|
|
|
// bits are known to be zero.
|
|
|
|
|
ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1));
|
2009-04-30 18:15:35 +08:00
|
|
|
APInt::mu magics = N1C->getAPIntValue().magicu();
|
2008-11-30 14:02:26 +08:00
|
|
|
|
2006-05-17 01:42:15 +08:00
|
|
|
// Multiply the numerator (operand 0) by the magic value
|
2008-11-30 14:02:26 +08:00
|
|
|
// FIXME: We should support doing a MUL in a wider type
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue Q;
|
2009-01-29 01:46:25 +08:00
|
|
|
if (isOperationLegalOrCustom(ISD::MULHU, VT))
|
2009-02-03 08:47:48 +08:00
|
|
|
Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0),
|
2007-10-09 02:33:35 +08:00
|
|
|
DAG.getConstant(magics.m, VT));
|
2009-01-29 01:46:25 +08:00
|
|
|
else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
|
2009-02-03 08:47:48 +08:00
|
|
|
Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT),
|
2007-10-09 02:33:35 +08:00
|
|
|
N->getOperand(0),
|
2008-08-29 05:40:38 +08:00
|
|
|
DAG.getConstant(magics.m, VT)).getNode(), 1);
|
2007-10-09 02:33:35 +08:00
|
|
|
else
|
2008-07-28 05:46:04 +08:00
|
|
|
return SDValue(); // No mulhu or equvialent
|
2006-05-17 01:42:15 +08:00
|
|
|
if (Created)
|
2008-08-29 05:40:38 +08:00
|
|
|
Created->push_back(Q.getNode());
|
2006-05-17 01:42:15 +08:00
|
|
|
|
|
|
|
|
if (magics.a == 0) {
|
2008-11-30 14:02:26 +08:00
|
|
|
assert(magics.s < N1C->getAPIntValue().getBitWidth() &&
|
|
|
|
|
"We shouldn't generate an undefined shift!");
|
2009-02-03 08:47:48 +08:00
|
|
|
return DAG.getNode(ISD::SRL, dl, VT, Q,
|
2006-05-17 01:42:15 +08:00
|
|
|
DAG.getConstant(magics.s, getShiftAmountTy()));
|
|
|
|
|
} else {
|
2009-02-03 08:47:48 +08:00
|
|
|
SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
|
2006-05-17 01:42:15 +08:00
|
|
|
if (Created)
|
2008-08-29 05:40:38 +08:00
|
|
|
Created->push_back(NPQ.getNode());
|
2009-02-03 08:47:48 +08:00
|
|
|
NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
|
2006-05-17 01:42:15 +08:00
|
|
|
DAG.getConstant(1, getShiftAmountTy()));
|
|
|
|
|
if (Created)
|
2008-08-29 05:40:38 +08:00
|
|
|
Created->push_back(NPQ.getNode());
|
2009-02-03 08:47:48 +08:00
|
|
|
NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
|
2006-05-17 01:42:15 +08:00
|
|
|
if (Created)
|
2008-08-29 05:40:38 +08:00
|
|
|
Created->push_back(NPQ.getNode());
|
2009-02-03 08:47:48 +08:00
|
|
|
return DAG.getNode(ISD::SRL, dl, VT, NPQ,
|
2006-05-17 01:42:15 +08:00
|
|
|
DAG.getConstant(magics.s-1, getShiftAmountTy()));
|
|
|
|
|
}
|
|
|
|
|
}
|