2014-04-04 07:47:24 +08:00
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; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
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Explicitly request physreg coalesing for a bunch of Thumb2 unit tests.
These tests all follow the same pattern:
mov r2, r0
movs r0, #0
$CMP r2, r1
it eq
moveq r0, #1
bx lr
The first 'mov' can be eliminated by rematerializing 'movs r0, #0' below the
test instruction:
$CMP r0, r1
mov.w r0, #0
it eq
moveq r0, #1
bx lr
So far, only physreg coalescing can do that. The register allocators won't yet
split live ranges just to eliminate copies. They can learn, but this particular
problem is not likely to show up in real code. It only appears because r0 is
used for both the function argument and return value.
llvm-svn: 130858
2011-05-05 03:02:07 +08:00
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2012-05-18 07:44:19 +08:00
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; These tests would be improved by 'movs r0, #0' being rematerialized below the
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; tst as 'mov.w r0, #0'.
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2009-06-30 06:49:42 +08:00
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2018-02-16 17:23:59 +08:00
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define i32 @f2(i32 %a, i32 %b) {
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2009-11-17 04:04:15 +08:00
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; CHECK: f2
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2019-01-10 16:36:33 +08:00
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; CHECK: eors {{.*}}, r1
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2009-06-30 06:49:42 +08:00
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%tmp = xor i32 %a, %b
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%tmp1 = icmp eq i32 %tmp, 0
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2018-02-16 17:23:59 +08:00
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%ret = select i1 %tmp1, i32 42, i32 24
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ret i32 %ret
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2009-06-30 06:49:42 +08:00
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}
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2018-02-16 17:23:59 +08:00
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define i32 @f4(i32 %a, i32 %b) {
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2009-11-17 04:04:15 +08:00
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; CHECK: f4
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2019-01-10 16:36:33 +08:00
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; CHECK: eors {{.*}}, r1
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2009-06-30 06:49:42 +08:00
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%tmp = xor i32 %a, %b
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%tmp1 = icmp eq i32 0, %tmp
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2018-02-16 17:23:59 +08:00
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%ret = select i1 %tmp1, i32 42, i32 24
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ret i32 %ret
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2009-06-30 06:49:42 +08:00
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}
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2009-06-30 09:02:20 +08:00
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2018-02-16 17:23:59 +08:00
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define i32 @f6(i32 %a, i32 %b) {
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2009-11-17 04:04:15 +08:00
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; CHECK: f6
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2012-05-18 07:44:19 +08:00
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; CHECK: teq.w {{.*}}, r1, lsl #5
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2009-06-30 09:02:20 +08:00
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%tmp = shl i32 %b, 5
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%tmp1 = xor i32 %a, %tmp
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%tmp2 = icmp eq i32 %tmp1, 0
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2018-02-16 17:23:59 +08:00
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%ret = select i1 %tmp2, i32 42, i32 24
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ret i32 %ret
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2009-06-30 09:02:20 +08:00
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}
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2018-02-16 17:23:59 +08:00
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define i32 @f7(i32 %a, i32 %b) {
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2009-11-17 04:04:15 +08:00
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; CHECK: f7
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2012-05-18 07:44:19 +08:00
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; CHECK: teq.w {{.*}}, r1, lsr #6
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2009-06-30 09:02:20 +08:00
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%tmp = lshr i32 %b, 6
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%tmp1 = xor i32 %a, %tmp
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%tmp2 = icmp eq i32 %tmp1, 0
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2018-02-16 17:23:59 +08:00
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%ret = select i1 %tmp2, i32 42, i32 24
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ret i32 %ret
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2009-06-30 09:02:20 +08:00
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}
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2018-02-16 17:23:59 +08:00
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define i32 @f8(i32 %a, i32 %b) {
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2009-11-17 04:04:15 +08:00
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; CHECK: f8
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2012-05-18 07:44:19 +08:00
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; CHECK: teq.w {{.*}}, r1, asr #7
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2009-06-30 09:02:20 +08:00
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%tmp = ashr i32 %b, 7
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%tmp1 = xor i32 %a, %tmp
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%tmp2 = icmp eq i32 %tmp1, 0
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2018-02-16 17:23:59 +08:00
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%ret = select i1 %tmp2, i32 42, i32 24
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ret i32 %ret
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2009-06-30 09:02:20 +08:00
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}
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2018-02-16 17:23:59 +08:00
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define i32 @f9(i32 %a, i32 %b) {
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2009-11-17 04:04:15 +08:00
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; CHECK: f9
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2012-05-18 07:44:19 +08:00
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; CHECK: teq.w {{.*}}, {{.*}}, ror #8
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2009-06-30 09:02:20 +08:00
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%l8 = shl i32 %a, 24
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%r8 = lshr i32 %a, 8
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%tmp = or i32 %l8, %r8
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%tmp1 = xor i32 %a, %tmp
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%tmp2 = icmp eq i32 %tmp1, 0
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2018-02-16 17:23:59 +08:00
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%ret = select i1 %tmp2, i32 42, i32 24
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ret i32 %ret
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2009-06-30 09:02:20 +08:00
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}
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