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llvm-project/llvm/test/CodeGen/ARM/fp16-bitcast.ll

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[ARM] FP16 bitcast test. NFC
2020-02-24 19:15:09 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend Summary: Half-precision floating point arguments and returns are currently promoted to either float or int32 in clang's CodeGen and there's no existing support for the lowering of `half` arguments and returns from IR in AArch32's backend. Such frontend coercions, implemented as coercion through memory in clang, can cause a series of issues in argument lowering, as causing arguments to be stored on the wrong bits on big-endian architectures and incurring in missing overflow detections in the return of certain functions. This patch introduces the handling of half-precision arguments and returns in the backend using the actual "half" type on the IR. Using the "half" type the backend is able to properly enforce the AAPCS' directions for those arguments, making sure they are stored on the proper bits of the registers and performing the necessary floating point convertions. Reviewers: rjmccall, olista01, asl, efriedma, ostannard, SjoerdMeijer Reviewed By: ostannard Subscribers: stuij, hiraditya, dmgreen, llvm-commits, chill, dnsampaio, danielkiss, kristof.beyls, cfe-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D75169
2020-06-09 16:45:47 +08:00
; RUN: llc -mtriple thumbv8m.main-arm-unknown-eabi --float-abi=soft -mattr=+vfp4d16sp < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-VFPV4-SOFT
; RUN: llc -mtriple thumbv8.1m.main-arm-unknown-eabi --float-abi=soft -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP16-SOFT
; RUN: llc -mtriple thumbv8m.main-arm-unknown-eabi --float-abi=hard -mattr=+vfp4d16sp < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-VFPV4-HARD
; RUN: llc -mtriple thumbv8.1m.main-arm-unknown-eabi --float-abi=hard -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP16-HARD
[ARM] FP16 bitcast test. NFC
2020-02-24 19:15:09 +08:00
target triple = "thumbv8.1m.main-arm-unknown-eabi"
define float @add(float %a, float %b) {
[ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend Summary: Half-precision floating point arguments and returns are currently promoted to either float or int32 in clang's CodeGen and there's no existing support for the lowering of `half` arguments and returns from IR in AArch32's backend. Such frontend coercions, implemented as coercion through memory in clang, can cause a series of issues in argument lowering, as causing arguments to be stored on the wrong bits on big-endian architectures and incurring in missing overflow detections in the return of certain functions. This patch introduces the handling of half-precision arguments and returns in the backend using the actual "half" type on the IR. Using the "half" type the backend is able to properly enforce the AAPCS' directions for those arguments, making sure they are stored on the proper bits of the registers and performing the necessary floating point convertions. Reviewers: rjmccall, olista01, asl, efriedma, ostannard, SjoerdMeijer Reviewed By: ostannard Subscribers: stuij, hiraditya, dmgreen, llvm-commits, chill, dnsampaio, danielkiss, kristof.beyls, cfe-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D75169
2020-06-09 16:45:47 +08:00
; CHECK-VFPV4-SOFT-LABEL: add:
; CHECK-VFPV4-SOFT: @ %bb.0: @ %entry
; CHECK-VFPV4-SOFT-NEXT: vmov s0, r1
; CHECK-VFPV4-SOFT-NEXT: vmov s2, r0
; CHECK-VFPV4-SOFT-NEXT: vadd.f32 s0, s2, s0
; CHECK-VFPV4-SOFT-NEXT: vmov r0, s0
; CHECK-VFPV4-SOFT-NEXT: bx lr
;
; CHECK-FP16-SOFT-LABEL: add:
; CHECK-FP16-SOFT: @ %bb.0: @ %entry
; CHECK-FP16-SOFT-NEXT: vmov s0, r1
; CHECK-FP16-SOFT-NEXT: vmov s2, r0
; CHECK-FP16-SOFT-NEXT: vadd.f32 s0, s2, s0
; CHECK-FP16-SOFT-NEXT: vmov r0, s0
; CHECK-FP16-SOFT-NEXT: bx lr
;
; CHECK-VFPV4-HARD-LABEL: add:
; CHECK-VFPV4-HARD: @ %bb.0: @ %entry
; CHECK-VFPV4-HARD-NEXT: vadd.f32 s0, s0, s1
; CHECK-VFPV4-HARD-NEXT: bx lr
;
; CHECK-FP16-HARD-LABEL: add:
; CHECK-FP16-HARD: @ %bb.0: @ %entry
; CHECK-FP16-HARD-NEXT: vadd.f32 s0, s0, s1
; CHECK-FP16-HARD-NEXT: bx lr
[ARM] FP16 bitcast test. NFC
2020-02-24 19:15:09 +08:00
entry:
%add = fadd float %a, %b
ret float %add
}
[ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend Summary: Half-precision floating point arguments and returns are currently promoted to either float or int32 in clang's CodeGen and there's no existing support for the lowering of `half` arguments and returns from IR in AArch32's backend. Such frontend coercions, implemented as coercion through memory in clang, can cause a series of issues in argument lowering, as causing arguments to be stored on the wrong bits on big-endian architectures and incurring in missing overflow detections in the return of certain functions. This patch introduces the handling of half-precision arguments and returns in the backend using the actual "half" type on the IR. Using the "half" type the backend is able to properly enforce the AAPCS' directions for those arguments, making sure they are stored on the proper bits of the registers and performing the necessary floating point convertions. Reviewers: rjmccall, olista01, asl, efriedma, ostannard, SjoerdMeijer Reviewed By: ostannard Subscribers: stuij, hiraditya, dmgreen, llvm-commits, chill, dnsampaio, danielkiss, kristof.beyls, cfe-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D75169
2020-06-09 16:45:47 +08:00
define half @addf16(half %a, half %b) {
; CHECK-VFPV4-SOFT-LABEL: addf16:
; CHECK-VFPV4-SOFT: @ %bb.0: @ %entry
; CHECK-VFPV4-SOFT-NEXT: vmov s0, r0
[ARM] Remove hasSideEffects from FP converts Whether an instruction is deemed to have side effects in determined by whether it has a tblgen pattern that emits a single instruction. Because of the way a lot of the the vcvt instructions are specified either in dagtodag code or with patterns that emit multiple instructions, they don't get marked as not having side effects. This just marks them as not having side effects manually. It can help especially with instruction scheduling, to not create artificial barriers, but one of these tests also managed to produce fewer instructions. Differential Revision: https://reviews.llvm.org/D81639
2020-07-05 21:54:12 +08:00
; CHECK-VFPV4-SOFT-NEXT: vmov s2, r1
[ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend Summary: Half-precision floating point arguments and returns are currently promoted to either float or int32 in clang's CodeGen and there's no existing support for the lowering of `half` arguments and returns from IR in AArch32's backend. Such frontend coercions, implemented as coercion through memory in clang, can cause a series of issues in argument lowering, as causing arguments to be stored on the wrong bits on big-endian architectures and incurring in missing overflow detections in the return of certain functions. This patch introduces the handling of half-precision arguments and returns in the backend using the actual "half" type on the IR. Using the "half" type the backend is able to properly enforce the AAPCS' directions for those arguments, making sure they are stored on the proper bits of the registers and performing the necessary floating point convertions. Reviewers: rjmccall, olista01, asl, efriedma, ostannard, SjoerdMeijer Reviewed By: ostannard Subscribers: stuij, hiraditya, dmgreen, llvm-commits, chill, dnsampaio, danielkiss, kristof.beyls, cfe-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D75169
2020-06-09 16:45:47 +08:00
; CHECK-VFPV4-SOFT-NEXT: vcvtb.f32.f16 s0, s0
[ARM] Remove hasSideEffects from FP converts Whether an instruction is deemed to have side effects in determined by whether it has a tblgen pattern that emits a single instruction. Because of the way a lot of the the vcvt instructions are specified either in dagtodag code or with patterns that emit multiple instructions, they don't get marked as not having side effects. This just marks them as not having side effects manually. It can help especially with instruction scheduling, to not create artificial barriers, but one of these tests also managed to produce fewer instructions. Differential Revision: https://reviews.llvm.org/D81639
2020-07-05 21:54:12 +08:00
; CHECK-VFPV4-SOFT-NEXT: vcvtb.f32.f16 s2, s2
[ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend Summary: Half-precision floating point arguments and returns are currently promoted to either float or int32 in clang's CodeGen and there's no existing support for the lowering of `half` arguments and returns from IR in AArch32's backend. Such frontend coercions, implemented as coercion through memory in clang, can cause a series of issues in argument lowering, as causing arguments to be stored on the wrong bits on big-endian architectures and incurring in missing overflow detections in the return of certain functions. This patch introduces the handling of half-precision arguments and returns in the backend using the actual "half" type on the IR. Using the "half" type the backend is able to properly enforce the AAPCS' directions for those arguments, making sure they are stored on the proper bits of the registers and performing the necessary floating point convertions. Reviewers: rjmccall, olista01, asl, efriedma, ostannard, SjoerdMeijer Reviewed By: ostannard Subscribers: stuij, hiraditya, dmgreen, llvm-commits, chill, dnsampaio, danielkiss, kristof.beyls, cfe-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D75169
2020-06-09 16:45:47 +08:00
; CHECK-VFPV4-SOFT-NEXT: vadd.f32 s0, s0, s2
; CHECK-VFPV4-SOFT-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-VFPV4-SOFT-NEXT: vmov r0, s0
; CHECK-VFPV4-SOFT-NEXT: bx lr
[ARM] FP16 bitcast test. NFC
2020-02-24 19:15:09 +08:00
;
[ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend Summary: Half-precision floating point arguments and returns are currently promoted to either float or int32 in clang's CodeGen and there's no existing support for the lowering of `half` arguments and returns from IR in AArch32's backend. Such frontend coercions, implemented as coercion through memory in clang, can cause a series of issues in argument lowering, as causing arguments to be stored on the wrong bits on big-endian architectures and incurring in missing overflow detections in the return of certain functions. This patch introduces the handling of half-precision arguments and returns in the backend using the actual "half" type on the IR. Using the "half" type the backend is able to properly enforce the AAPCS' directions for those arguments, making sure they are stored on the proper bits of the registers and performing the necessary floating point convertions. Reviewers: rjmccall, olista01, asl, efriedma, ostannard, SjoerdMeijer Reviewed By: ostannard Subscribers: stuij, hiraditya, dmgreen, llvm-commits, chill, dnsampaio, danielkiss, kristof.beyls, cfe-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D75169
2020-06-09 16:45:47 +08:00
; CHECK-FP16-SOFT-LABEL: addf16:
; CHECK-FP16-SOFT: @ %bb.0: @ %entry
; CHECK-FP16-SOFT-NEXT: vmov.f16 s0, r1
; CHECK-FP16-SOFT-NEXT: vmov.f16 s2, r0
; CHECK-FP16-SOFT-NEXT: vadd.f16 s0, s2, s0
; CHECK-FP16-SOFT-NEXT: vmov r0, s0
; CHECK-FP16-SOFT-NEXT: bx lr
;
; CHECK-VFPV4-HARD-LABEL: addf16:
; CHECK-VFPV4-HARD: @ %bb.0: @ %entry
; CHECK-VFPV4-HARD-NEXT: vcvtb.f32.f16 s2, s1
; CHECK-VFPV4-HARD-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-VFPV4-HARD-NEXT: vadd.f32 s0, s0, s2
; CHECK-VFPV4-HARD-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-VFPV4-HARD-NEXT: bx lr
;
; CHECK-FP16-HARD-LABEL: addf16:
; CHECK-FP16-HARD: @ %bb.0: @ %entry
; CHECK-FP16-HARD-NEXT: vadd.f16 s0, s0, s1
; CHECK-FP16-HARD-NEXT: bx lr
[ARM] FP16 bitcast test. NFC
2020-02-24 19:15:09 +08:00
entry:
[ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend Summary: Half-precision floating point arguments and returns are currently promoted to either float or int32 in clang's CodeGen and there's no existing support for the lowering of `half` arguments and returns from IR in AArch32's backend. Such frontend coercions, implemented as coercion through memory in clang, can cause a series of issues in argument lowering, as causing arguments to be stored on the wrong bits on big-endian architectures and incurring in missing overflow detections in the return of certain functions. This patch introduces the handling of half-precision arguments and returns in the backend using the actual "half" type on the IR. Using the "half" type the backend is able to properly enforce the AAPCS' directions for those arguments, making sure they are stored on the proper bits of the registers and performing the necessary floating point convertions. Reviewers: rjmccall, olista01, asl, efriedma, ostannard, SjoerdMeijer Reviewed By: ostannard Subscribers: stuij, hiraditya, dmgreen, llvm-commits, chill, dnsampaio, danielkiss, kristof.beyls, cfe-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D75169
2020-06-09 16:45:47 +08:00
%add = fadd half %a, %b
ret half %add
[ARM] FP16 bitcast test. NFC
2020-02-24 19:15:09 +08:00
}
[ARM] Various tests for MVE and FP16 codegen. NFC
2020-04-24 04:58:00 +08:00
define half @load_i16(i16 *%hp) {
[ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend Summary: Half-precision floating point arguments and returns are currently promoted to either float or int32 in clang's CodeGen and there's no existing support for the lowering of `half` arguments and returns from IR in AArch32's backend. Such frontend coercions, implemented as coercion through memory in clang, can cause a series of issues in argument lowering, as causing arguments to be stored on the wrong bits on big-endian architectures and incurring in missing overflow detections in the return of certain functions. This patch introduces the handling of half-precision arguments and returns in the backend using the actual "half" type on the IR. Using the "half" type the backend is able to properly enforce the AAPCS' directions for those arguments, making sure they are stored on the proper bits of the registers and performing the necessary floating point convertions. Reviewers: rjmccall, olista01, asl, efriedma, ostannard, SjoerdMeijer Reviewed By: ostannard Subscribers: stuij, hiraditya, dmgreen, llvm-commits, chill, dnsampaio, danielkiss, kristof.beyls, cfe-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D75169
2020-06-09 16:45:47 +08:00
; CHECK-VFPV4-SOFT-LABEL: load_i16:
; CHECK-VFPV4-SOFT: @ %bb.0: @ %entry
; CHECK-VFPV4-SOFT-NEXT: vmov.f32 s0, #1.000000e+00
; CHECK-VFPV4-SOFT-NEXT: ldrh r0, [r0]
; CHECK-VFPV4-SOFT-NEXT: vmov s2, r0
; CHECK-VFPV4-SOFT-NEXT: vcvtb.f32.f16 s2, s2
; CHECK-VFPV4-SOFT-NEXT: vadd.f32 s0, s2, s0
; CHECK-VFPV4-SOFT-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-VFPV4-SOFT-NEXT: vmov r0, s0
; CHECK-VFPV4-SOFT-NEXT: bx lr
;
; CHECK-FP16-SOFT-LABEL: load_i16:
; CHECK-FP16-SOFT: @ %bb.0: @ %entry
; CHECK-FP16-SOFT-NEXT: vldr.16 s2, [r0]
; CHECK-FP16-SOFT-NEXT: vmov.f16 s0, #1.000000e+00
; CHECK-FP16-SOFT-NEXT: vadd.f16 s0, s2, s0
; CHECK-FP16-SOFT-NEXT: vmov r0, s0
; CHECK-FP16-SOFT-NEXT: bx lr
;
; CHECK-VFPV4-HARD-LABEL: load_i16:
; CHECK-VFPV4-HARD: @ %bb.0: @ %entry
; CHECK-VFPV4-HARD-NEXT: vmov.f32 s0, #1.000000e+00
; CHECK-VFPV4-HARD-NEXT: ldrh r0, [r0]
; CHECK-VFPV4-HARD-NEXT: vmov s2, r0
; CHECK-VFPV4-HARD-NEXT: vcvtb.f32.f16 s2, s2
; CHECK-VFPV4-HARD-NEXT: vadd.f32 s0, s2, s0
; CHECK-VFPV4-HARD-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-VFPV4-HARD-NEXT: bx lr
[ARM] Various tests for MVE and FP16 codegen. NFC
2020-04-24 04:58:00 +08:00
;
[ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend Summary: Half-precision floating point arguments and returns are currently promoted to either float or int32 in clang's CodeGen and there's no existing support for the lowering of `half` arguments and returns from IR in AArch32's backend. Such frontend coercions, implemented as coercion through memory in clang, can cause a series of issues in argument lowering, as causing arguments to be stored on the wrong bits on big-endian architectures and incurring in missing overflow detections in the return of certain functions. This patch introduces the handling of half-precision arguments and returns in the backend using the actual "half" type on the IR. Using the "half" type the backend is able to properly enforce the AAPCS' directions for those arguments, making sure they are stored on the proper bits of the registers and performing the necessary floating point convertions. Reviewers: rjmccall, olista01, asl, efriedma, ostannard, SjoerdMeijer Reviewed By: ostannard Subscribers: stuij, hiraditya, dmgreen, llvm-commits, chill, dnsampaio, danielkiss, kristof.beyls, cfe-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D75169
2020-06-09 16:45:47 +08:00
; CHECK-FP16-HARD-LABEL: load_i16:
; CHECK-FP16-HARD: @ %bb.0: @ %entry
; CHECK-FP16-HARD-NEXT: vldr.16 s2, [r0]
; CHECK-FP16-HARD-NEXT: vmov.f16 s0, #1.000000e+00
; CHECK-FP16-HARD-NEXT: vadd.f16 s0, s2, s0
; CHECK-FP16-HARD-NEXT: bx lr
[ARM] Various tests for MVE and FP16 codegen. NFC
2020-04-24 04:58:00 +08:00
entry:
%h = load i16, i16 *%hp, align 2
%hc = bitcast i16 %h to half
%add = fadd half %hc, 1.0
ret half %add
}
define i16 @load_f16(half *%hp) {
; CHECK-LABEL: load_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrh r0, [r0]
; CHECK-NEXT: adds r0, #1
; CHECK-NEXT: bx lr
entry:
%h = load half, half *%hp, align 2
%hc = bitcast half %h to i16
%add = add i16 %hc, 1
ret i16 %add
}
[ARM] Extra fp16 bitcast tests. NFC
2020-09-17 19:10:23 +08:00
define half @constcall() {
; CHECK-VFPV4-SOFT-LABEL: constcall:
; CHECK-VFPV4-SOFT: @ %bb.0: @ %entry
; CHECK-VFPV4-SOFT-NEXT: mov.w r0, #18688
; CHECK-VFPV4-SOFT-NEXT: b ccc
;
; CHECK-FP16-SOFT-LABEL: constcall:
; CHECK-FP16-SOFT: @ %bb.0: @ %entry
[ARM] Constant fold VMOVrh This adds simple constant folding for VMOVrh, to constant fold fp16 constants to integer values. It can help especially with soft calling conventions, but some of the results are not optimal as we end up loading using a vldr. This will be improved in a follow up patch. Differential Revision: https://reviews.llvm.org/D87789
2020-09-21 04:32:51 +08:00
; CHECK-FP16-SOFT-NEXT: mov.w r0, #18688
[ARM] Extra fp16 bitcast tests. NFC
2020-09-17 19:10:23 +08:00
; CHECK-FP16-SOFT-NEXT: b ccc
;
; CHECK-VFPV4-HARD-LABEL: constcall:
; CHECK-VFPV4-HARD: @ %bb.0: @ %entry
; CHECK-VFPV4-HARD-NEXT: vldr s0, .LCPI4_0
; CHECK-VFPV4-HARD-NEXT: b ccc
; CHECK-VFPV4-HARD-NEXT: .p2align 2
; CHECK-VFPV4-HARD-NEXT: @ %bb.1:
; CHECK-VFPV4-HARD-NEXT: .LCPI4_0:
; CHECK-VFPV4-HARD-NEXT: .long 0x00004900 @ float 2.61874657E-41
;
; CHECK-FP16-HARD-LABEL: constcall:
; CHECK-FP16-HARD: @ %bb.0: @ %entry
[ARM] Select f32 constants with vmov.f16 This adds lowering for f32 values using the vmov.f16, which zeroes the top bits whilst setting the lower bits to a pattern. This range of values does not often come up, except where a f16 constant value has been converted to a f32. Differential Revision: https://reviews.llvm.org/D87790
2020-09-21 18:10:47 +08:00
; CHECK-FP16-HARD-NEXT: vmov.f16 s0, #1.000000e+01
[ARM] Extra fp16 bitcast tests. NFC
2020-09-17 19:10:23 +08:00
; CHECK-FP16-HARD-NEXT: b ccc
entry:
%call = tail call fast half @ccc(half 0xH4900)
ret half %call
}
define half @constret() {
; CHECK-VFPV4-SOFT-LABEL: constret:
; CHECK-VFPV4-SOFT: @ %bb.0: @ %entry
; CHECK-VFPV4-SOFT-NEXT: mov.w r0, #18688
; CHECK-VFPV4-SOFT-NEXT: bx lr
;
; CHECK-FP16-SOFT-LABEL: constret:
; CHECK-FP16-SOFT: @ %bb.0: @ %entry
; CHECK-FP16-SOFT-NEXT: vmov.f16 s0, #1.000000e+01
; CHECK-FP16-SOFT-NEXT: vmov r0, s0
; CHECK-FP16-SOFT-NEXT: bx lr
;
; CHECK-VFPV4-HARD-LABEL: constret:
; CHECK-VFPV4-HARD: @ %bb.0: @ %entry
; CHECK-VFPV4-HARD-NEXT: vldr s0, .LCPI5_0
; CHECK-VFPV4-HARD-NEXT: bx lr
; CHECK-VFPV4-HARD-NEXT: .p2align 2
; CHECK-VFPV4-HARD-NEXT: @ %bb.1:
; CHECK-VFPV4-HARD-NEXT: .LCPI5_0:
; CHECK-VFPV4-HARD-NEXT: .long 0x00004900 @ float 2.61874657E-41
;
; CHECK-FP16-HARD-LABEL: constret:
; CHECK-FP16-HARD: @ %bb.0: @ %entry
; CHECK-FP16-HARD-NEXT: vmov.f16 s0, #1.000000e+01
; CHECK-FP16-HARD-NEXT: bx lr
entry:
ret half 0xH4900
}
declare half @ccc(half)