2019-06-06 19:53:26 +08:00
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; RUN: llc < %s -mtriple=aarch64-windows -mattr=+fullfp16 | FileCheck %s
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; CHECK-LABEL: testmhhs:
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; CHECK: fcvtas w0, h0
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; CHECK: ret
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define i16 @testmhhs(half %x) {
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entry:
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%0 = tail call i32 @llvm.lround.i32.f16(half %x)
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%conv = trunc i32 %0 to i16
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ret i16 %conv
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}
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; CHECK-LABEL: testmhws:
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; CHECK: fcvtas w0, h0
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; CHECK: ret
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define i32 @testmhws(half %x) {
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entry:
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%0 = tail call i32 @llvm.lround.i32.f16(half %x)
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ret i32 %0
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}
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; CHECK-LABEL: testmhxs:
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; CHECK: fcvtas w8, h0
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; CHECK-NEXT: sxtw x0, w8
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[AArch64] Generate and parse SEH assembly directives
This ensures that you get the same output regardless if generating
code directly to an object file or if generating assembly and
assembling that.
Add implementations of the EmitARM64WinCFI*() methods in
AArch64TargetAsmStreamer, and fill in one blank in MCAsmStreamer.
Add corresponding directive handlers in AArch64AsmParser and
COFFAsmParser.
Some SEH directive names have been picked to match the prior art
for SEH assembly directives for x86_64, e.g. the spelling of
".seh_startepilogue" matching the preexisting ".seh_endprologue".
For the directives for saving registers, the exact spelling
from the arm64 documentation is picked, e.g. ".seh_save_reg" (to follow
that naming for all the other ones, e.g. ".seh_save_fregp_x"), while
the corresponding one for x86_64 is plain ".seh_savereg" without the
second underscore.
Directives in the epilogues have the same names as in prologues,
e.g. .seh_savereg, even though the registers are restored, not
saved, at that point.
Differential Revision: https://reviews.llvm.org/D86529
2020-08-07 17:44:48 +08:00
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; CHECK-NEXT: .seh_startepilogue
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; CHECK-NEXT: .seh_endepilogue
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2019-06-06 19:53:26 +08:00
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; CHECK-NEXT: ret
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define i64 @testmhxs(half %x) {
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entry:
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%0 = tail call i32 @llvm.lround.i32.f16(half %x)
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%conv = sext i32 %0 to i64
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ret i64 %conv
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}
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declare i32 @llvm.lround.i32.f16(half) nounwind readnone
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