2016-05-18 22:28:54 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2018-06-03 01:33:26 +08:00
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; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefixes=CHECK,SSE
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; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX,AVX1
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2018-06-03 02:01:09 +08:00
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; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
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2016-05-18 22:28:54 +08:00
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; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/sse42-builtins.c
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define i64 @test_mm_crc64_u8(i64 %a0, i8 %a1) nounwind{
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2018-06-03 01:33:26 +08:00
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; CHECK-LABEL: test_mm_crc64_u8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: crc32b %sil, %edi
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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2016-05-18 22:28:54 +08:00
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%res = call i64 @llvm.x86.sse42.crc32.64.8(i64 %a0, i8 %a1)
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ret i64 %res
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}
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declare i64 @llvm.x86.sse42.crc32.64.8(i64, i8) nounwind readnone
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define i64 @test_mm_crc64_u64(i64 %a0, i64 %a1) nounwind{
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2018-06-03 01:33:26 +08:00
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; CHECK-LABEL: test_mm_crc64_u64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: crc32q %rsi, %rdi
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: retq
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2016-05-18 22:28:54 +08:00
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%res = call i64 @llvm.x86.sse42.crc32.64.64(i64 %a0, i64 %a1)
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ret i64 %res
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}
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declare i64 @llvm.x86.sse42.crc32.64.64(i64, i64) nounwind readnone
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