2016-02-13 07:45:29 +08:00
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; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VCCZ-BUG %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VCCZ-BUG %s
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2017-01-25 06:02:15 +08:00
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NOVCCZ-BUG %s
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2016-02-13 07:45:29 +08:00
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; GCN-FUNC: {{^}}vccz_workaround:
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; GCN: s_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0x0
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[AMDGPU] Fixed incorrect uniform branch condition
Summary:
I had a case where multiple nested uniform ifs resulted in code that did
v_cmp comparisons, combining the results with s_and_b64, s_or_b64 and
s_xor_b64 and using the resulting mask in s_cbranch_vccnz, without first
ensuring that bits for inactive lanes were clear.
There was already code for inserting an "s_and_b64 vcc, exec, vcc" to
clear bits for inactive lanes in the case that the branch is instruction
selected as s_cbranch_scc1 and is then changed to s_cbranch_vccnz in
SIFixSGPRCopies. I have added the same code into SILowerControlFlow for
the case that the branch is instruction selected as s_cbranch_vccnz.
This de-optimizes the code in some cases where the s_and is not needed,
because vcc is the result of a v_cmp, or multiple v_cmp instructions
combined by s_and/s_or. We should add a pass to re-optimize those cases.
Reviewers: arsenm, kzhuravl
Subscribers: wdng, yaxunl, t-tye, llvm-commits, dstuttard, timcorringham, nhaehnle
Differential Revision: https://reviews.llvm.org/D41292
llvm-svn: 322119
2018-01-10 05:34:43 +08:00
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; GCN: v_cmp_neq_f32_e64 {{[^,]*}}, s{{[0-9]+}}, 0{{$}}
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2017-06-02 22:19:25 +08:00
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; VCCZ-BUG: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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2016-02-13 07:45:29 +08:00
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; VCCZ-BUG: s_mov_b64 vcc, vcc
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; NOVCCZ-BUG-NOT: s_mov_b64 vcc, vcc
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; GCN: s_cbranch_vccnz [[EXIT:[0-9A-Za-z_]+]]
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; GCN: buffer_store_dword
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; GCN: [[EXIT]]:
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; GCN: s_endpgm
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2018-02-14 02:00:25 +08:00
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define amdgpu_kernel void @vccz_workaround(i32 addrspace(4)* %in, i32 addrspace(1)* %out, float %cond) {
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2016-02-13 07:45:29 +08:00
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entry:
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%cnd = fcmp oeq float 0.0, %cond
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2018-02-14 02:00:25 +08:00
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%sgpr = load volatile i32, i32 addrspace(4)* %in
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2016-02-13 07:45:29 +08:00
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br i1 %cnd, label %if, label %endif
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if:
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store i32 %sgpr, i32 addrspace(1)* %out
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br label %endif
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endif:
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ret void
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}
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; GCN-FUNC: {{^}}vccz_noworkaround:
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; GCN: v_cmp_neq_f32_e32 vcc, 0, v{{[0-9]+}}
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; GCN: s_cbranch_vccnz [[EXIT:[0-9A-Za-z_]+]]
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; GCN: buffer_store_dword
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; GCN: [[EXIT]]:
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; GCN: s_endpgm
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2017-03-22 05:39:51 +08:00
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define amdgpu_kernel void @vccz_noworkaround(float addrspace(1)* %in, float addrspace(1)* %out) {
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2016-02-13 07:45:29 +08:00
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entry:
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%vgpr = load volatile float, float addrspace(1)* %in
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%cnd = fcmp oeq float 0.0, %vgpr
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br i1 %cnd, label %if, label %endif
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if:
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store float %vgpr, float addrspace(1)* %out
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br label %endif
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endif:
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ret void
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}
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