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llvm-project/llvm/test/MC/AArch64/SVE/add-diagnostics.s

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[AArch64][SVE] Asm: More concise test format Change the test format for SVE assembler/disassembler tests to be less verbose and have both tests in the same file. The tests check the following: * All instructions are assembled correctly into the right encoding. * All instructions are disassembled correctly (into the preferred assembly format) * Without -mattr=+sve the instructions are not assembled. * Without -mattr=+sve the instructions are not disassembled. This patch also adds several negative tests for SVE add/sub. Patch by Sander De Smalen. Reviewed by: rengolin, fhahn Differential Revision: https://reviews.llvm.org/D39792 llvm-svn: 317894
2017-11-11 00:25:16 +08:00
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// Register z32 does not exist.
add z22.h, z10.h, z32.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: add z22.h, z10.h, z32.h
[AArch64][SVE] Asm: Report SVE parsing diagnostics only once Summary: Prevent an issue where a diagnostic is reported multiple times by bailing out with a ParseFail if an invalid SVE register element qualifier/suffix is specified, for example: <stdin>:10:18: error: invalid sve vector kind qualifier add z20.h, z2.h, z31.x ^ <stdin>:10:18: error: invalid sve vector kind qualifier add z20.h, z2.h, z31.x ... <stdin>:10:18: error: invalid sve vector kind qualifier add z20.h, z2.h, z31.x ^ Reviewers: fhahn, rengolin Reviewed By: rengolin Subscribers: aemerson, javed.absar, tschuett, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D39894 llvm-svn: 318297
2017-11-15 23:44:43 +08:00
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
[AArch64][SVE] Asm: More concise test format Change the test format for SVE assembler/disassembler tests to be less verbose and have both tests in the same file. The tests check the following: * All instructions are assembled correctly into the right encoding. * All instructions are disassembled correctly (into the preferred assembly format) * Without -mattr=+sve the instructions are not assembled. * Without -mattr=+sve the instructions are not disassembled. This patch also adds several negative tests for SVE add/sub. Patch by Sander De Smalen. Reviewed by: rengolin, fhahn Differential Revision: https://reviews.llvm.org/D39792 llvm-svn: 317894
2017-11-11 00:25:16 +08:00
// Invalid element kind.
add z20.h, z2.h, z31.x
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid sve vector kind qualifier
// CHECK-NEXT: add z20.h, z2.h, z31.x
[AArch64][SVE] Asm: Report SVE parsing diagnostics only once Summary: Prevent an issue where a diagnostic is reported multiple times by bailing out with a ParseFail if an invalid SVE register element qualifier/suffix is specified, for example: <stdin>:10:18: error: invalid sve vector kind qualifier add z20.h, z2.h, z31.x ^ <stdin>:10:18: error: invalid sve vector kind qualifier add z20.h, z2.h, z31.x ... <stdin>:10:18: error: invalid sve vector kind qualifier add z20.h, z2.h, z31.x ^ Reviewers: fhahn, rengolin Reviewed By: rengolin Subscribers: aemerson, javed.absar, tschuett, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D39894 llvm-svn: 318297
2017-11-15 23:44:43 +08:00
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
[AArch64][SVE] Asm: More concise test format Change the test format for SVE assembler/disassembler tests to be less verbose and have both tests in the same file. The tests check the following: * All instructions are assembled correctly into the right encoding. * All instructions are disassembled correctly (into the preferred assembly format) * Without -mattr=+sve the instructions are not assembled. * Without -mattr=+sve the instructions are not disassembled. This patch also adds several negative tests for SVE add/sub. Patch by Sander De Smalen. Reviewed by: rengolin, fhahn Differential Revision: https://reviews.llvm.org/D39792 llvm-svn: 317894
2017-11-11 00:25:16 +08:00
// Element size specifiers should match.
add z27.h, z11.h, z27.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: add z27.h, z11.h, z27.b
[AArch64][SVE] Asm: Report SVE parsing diagnostics only once Summary: Prevent an issue where a diagnostic is reported multiple times by bailing out with a ParseFail if an invalid SVE register element qualifier/suffix is specified, for example: <stdin>:10:18: error: invalid sve vector kind qualifier add z20.h, z2.h, z31.x ^ <stdin>:10:18: error: invalid sve vector kind qualifier add z20.h, z2.h, z31.x ... <stdin>:10:18: error: invalid sve vector kind qualifier add z20.h, z2.h, z31.x ^ Reviewers: fhahn, rengolin Reviewed By: rengolin Subscribers: aemerson, javed.absar, tschuett, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D39894 llvm-svn: 318297
2017-11-15 23:44:43 +08:00
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Recommit r322073: [AArch64][SVE] Asm: Add predicated ADD/SUB instructions Fixed issue that was found on sanitizer-x86_64-linux-fast. I changed the result type of 'Parser.getTok().getString().lower()' in AArch64AsmParser::tryParseSVEPredicateVector() from 'StringRef' to 'auto', since StringRef::lower() returns a std::string. llvm-svn: 322092
2018-01-10 01:01:27 +08:00
// Invalid predicate suffix '/a'
add z29.d, p7/a, z29.d, z8.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expecting 'm' or 'z' predication
// CHECK-NEXT: add z29.d, p7/a, z29.d, z8.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Missing predicate suffix
add z29.d, p7, z29.d, z8.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: add z29.d, p7, z29.d, z8.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7].
add z22.b, p8/m, z22.b, z11.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: add z22.b, p8/m, z22.b, z11.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
add z22.h, p8/m, z22.h, z6.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: add z22.h, p8/m, z22.h, z6.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
add z30.s, p8/m, z30.s, z13.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: add z30.s, p8/m, z30.s, z13.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
add z29.d, p8/m, z29.d, z8.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: add z29.d, p8/m, z29.d, z8.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: