forked from OSchip/llvm-project
55 lines
1.8 KiB
Plaintext
55 lines
1.8 KiB
Plaintext
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//===- README_ALTIVEC.txt - Notes for improving Altivec code gen ----------===//
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Implement TargetConstantVec, and set up PPC to custom lower ConstantVec into
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TargetConstantVec's if it's one of the many forms that are algorithmically
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computable using the spiffy altivec instructions.
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//===----------------------------------------------------------------------===//
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Implement PPCInstrInfo::isLoadFromStackSlot/isStoreToStackSlot for vector
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registers, to generate better spill code.
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//===----------------------------------------------------------------------===//
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Altivec support. The first should be a single lvx from the constant pool, the
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second should be a xor/stvx:
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void foo(void) {
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int x[8] __attribute__((aligned(128))) = { 1, 1, 1, 1, 1, 1, 1, 1 };
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bar (x);
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}
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#include <string.h>
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void foo(void) {
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int x[8] __attribute__((aligned(128)));
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memset (x, 0, sizeof (x));
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bar (x);
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}
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//===----------------------------------------------------------------------===//
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Altivec: Codegen'ing MUL with vector FMADD should add -0.0, not 0.0:
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=8763
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We need to codegen -0.0 vector efficiently (no constant pool load).
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When -ffast-math is on, we can use 0.0.
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//===----------------------------------------------------------------------===//
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Consider this:
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v4f32 Vector;
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v4f32 Vector2 = { Vector.X, Vector.X, Vector.X, Vector.X };
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Since we know that "Vector" is 16-byte aligned and we know the element offset
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of ".X", we should change the load into a lve*x instruction, instead of doing
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a load/store/lve*x sequence.
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//===----------------------------------------------------------------------===//
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There are a wide range of vector constants we can generate with combinations of
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altivec instructions. For example, GCC does: t=vsplti*, r = t+t.
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//===----------------------------------------------------------------------===//
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