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llvm-project/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir

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[ARM] GlobalISel: Select add i32, i32 Add the minimal support necessary to select a function that returns the sum of two i32 values. This includes some support for argument/return lowering of i32 values through registers, as well as the handling of copy and add instructions throughout the GlobalISel pipeline. Differential Revision: https://reviews.llvm.org/D26677 llvm-svn: 289940
2016-12-16 20:54:46 +08:00
# RUN: llc -O0 -mtriple arm-- -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
[ARM] GlobalISel: Support i1 add and ABI extensions Add support for: * i1 add * i1 function arguments, if passed through registers * i1 returns, with ABI signext/zeroext Differential Revision: https://reviews.llvm.org/D27706 llvm-svn: 293035
2017-01-25 16:47:40 +08:00
define void @test_zext_s1() { ret void }
define void @test_sext_s1() { ret void }
[ARM] GlobalISel: Support i8/i16 ABI extensions At the moment, this means supporting the signext/zeroext attribute on the return type of the function. For function arguments, signext/zeroext should be handled by the caller, so there's nothing for us to do until we start lowering calls. Note that this does not include support for other extensions (i8 to i16), those will be added later. Differential Revision: https://reviews.llvm.org/D27705 llvm-svn: 293034
2017-01-25 16:10:40 +08:00
define void @test_sext_s8() { ret void }
define void @test_zext_s16() { ret void }
[ARM][GlobalISel] Support for G_ANYEXT G_ANYEXT can be introduced by the legalizer when widening scalars. Add support for it in the register bank info (same mapping as everything else) and in the instruction selector. When selecting it, we treat it as a COPY, just like G_TRUNC. On this occasion we get rid of some assertions in selectCopy so we can reuse it. This shouldn't be a problem at the moment since we're not supporting any complicated cases (e.g. FPR, different register banks). We might want to separate the paths when we do. llvm-svn: 302778
2017-05-11 16:28:31 +08:00
define void @test_anyext_s8() { ret void }
define void @test_anyext_s16() { ret void }
[ARM] GlobalISel: Support i8/i16 ABI extensions At the moment, this means supporting the signext/zeroext attribute on the return type of the function. For function arguments, signext/zeroext should be handled by the caller, so there's nothing for us to do until we start lowering calls. Note that this does not include support for other extensions (i8 to i16), those will be added later. Differential Revision: https://reviews.llvm.org/D27705 llvm-svn: 293034
2017-01-25 16:10:40 +08:00
[ARM] GlobalISel: Add support for G_TRUNC Select them as copies. We only select if both the source and the destination are on the same register bank, so this shouldn't cause any trouble. llvm-svn: 300971
2017-04-21 21:16:50 +08:00
define void @test_trunc_s32_16() { ret void }
[ARM] GlobalISel: Select i8 and i16 copies Teach the instruction selector that it's ok to copy small values from physical registers. First part of https://reviews.llvm.org/D27704 llvm-svn: 290104
2016-12-19 22:07:50 +08:00
define void @test_add_s8() { ret void }
define void @test_add_s16() { ret void }
define void @test_add_s32() { ret void }
[ARM] GlobalISel: Add FPR reg bank Add a register bank for floating point values and select simple instructions using them (add, copies from GPR). This assumes that the hardware can cope with a single precision add (VADDS) instruction, so the legalizer will treat G_FADD as legal and the instruction selector will refuse to select if the hardware doesn't support it. In the future we'll want to be more careful about this, and legalize to libcalls if we have to use soft float. llvm-svn: 294442
2017-02-08 21:23:04 +08:00
define void @test_fadd_s32() #0 { ret void }
[ARM] GlobalISel: Select double G_FADD and copies Just use VADDD if available, bail out if not. llvm-svn: 295309
2017-02-16 20:19:52 +08:00
define void @test_fadd_s64() #0 { ret void }
[ARM] GlobalISel: Add FPR reg bank Add a register bank for floating point values and select simple instructions using them (add, copies from GPR). This assumes that the hardware can cope with a single precision add (VADDS) instruction, so the legalizer will treat G_FADD as legal and the instruction selector will refuse to select if the hardware doesn't support it. In the future we'll want to be more careful about this, and legalize to libcalls if we have to use soft float. llvm-svn: 294442
2017-02-08 21:23:04 +08:00
[ARM] GlobalISel: Add support for G_SUB Support G_SUB throughout the GlobalISel pipeline. It is exactly the same as G_ADD, nothing fancy. llvm-svn: 300546
2017-04-18 20:35:28 +08:00
define void @test_sub_s8() { ret void }
define void @test_sub_s16() { ret void }
define void @test_sub_s32() { ret void }
[ARM] GlobalISel: Add support for G_MUL Support G_MUL, very similar to G_ADD and G_SUB. The only difference is in the instruction selector, where we have to select either MUL or MULv5 depending on the target. llvm-svn: 300665
2017-04-19 15:29:46 +08:00
define void @test_mul_s8() #1 { ret void }
define void @test_mul_s16() #1 { ret void }
define void @test_mul_s32() #1 { ret void }
define void @test_mulv5_s32() { ret void }
[ARM] GlobalISel: Support G_(S|U)DIV for s32 Add support for both targets with hardware division and without. For hardware division we have to add support throughout the pipeline (legalizer, reg bank select, instruction select). For targets without hardware division, we only need to mark it as a libcall. llvm-svn: 301164
2017-04-24 16:20:05 +08:00
define void @test_sdiv_s32() #2 { ret void }
define void @test_udiv_s32() #2 { ret void }
[ARM] GlobalISel: Support G_AND This is identical to the support for the other binary operators: - widen to s32 - map into GPR - select ANDrr (via TableGen'erated code) llvm-svn: 304885
2017-06-07 17:17:41 +08:00
define void @test_and_s32() { ret void }
[ARM] GlobalISel: Support G_OR Same as the other binary operators: - legalize to 32 bits - map to GPRs - select ORRrr thanks to TableGen'erated code llvm-svn: 304890
2017-06-07 18:14:23 +08:00
define void @test_or_s32() { ret void }
[ARM] GlobalISel: Support G_XOR Same as the other binary operators: - legalize to 32 bits - map to GPRs - select to EORrr via TableGen'erated code llvm-svn: 304898
2017-06-07 19:57:30 +08:00
define void @test_xor_s32() { ret void }
[ARM] GlobalISel: Support G_AND This is identical to the support for the other binary operators: - widen to s32 - map into GPR - select ANDrr (via TableGen'erated code) llvm-svn: 304885
2017-06-07 17:17:41 +08:00
[ARM] GlobalISel: Support loading from the stack Add support for selecting simple G_LOAD and G_FRAME_INDEX instructions (32-bit scalars only). This will be useful for functions that need to pass arguments on the stack. First part of https://reviews.llvm.org/D27195. llvm-svn: 290096
2016-12-19 19:26:31 +08:00
define void @test_load_from_stack() { ret void }
[ARM] GlobalISel: Select floating point loads llvm-svn: 295321
2017-02-16 22:10:50 +08:00
define void @test_load_f32() #0 { ret void }
define void @test_load_f64() #0 { ret void }
[ARM] GlobalISel: Add FPR reg bank Add a register bank for floating point values and select simple instructions using them (add, copies from GPR). This assumes that the hardware can cope with a single precision add (VADDS) instruction, so the legalizer will treat G_FADD as legal and the instruction selector will refuse to select if the hardware doesn't support it. In the future we'll want to be more careful about this, and legalize to libcalls if we have to use soft float. llvm-svn: 294442
2017-02-08 21:23:04 +08:00
[ARM] GlobalISel: Select G_STORE Same as selecting G_LOAD. llvm-svn: 296122
2017-02-24 22:01:27 +08:00
define void @test_stores() #0 { ret void }
[ARM] GlobalISel: Select G_GEP At this point, G_GEP is just an add, so we treat it exactly like a G_ADD. llvm-svn: 296462
2017-02-28 18:14:38 +08:00
define void @test_gep() { ret void }
[ARM] GlobalISel: Select G_CONSTANT with CImm operands When selecting a G_CONSTANT to a MOVi, we need the value to be an Imm operand. We used to just leave the G_CONSTANT operand unchanged, which works in some cases (such as the GEP offsets that we create when referring to stack slots). However, in many other places the G_CONSTANTs are created with CImm operands. This patch makes sure to handle those as well, and to error out gracefully if in the end we don't end up with an Imm operand. Thanks to Oliver Stannard for reporting this issue. llvm-svn: 301162
2017-04-24 14:30:56 +08:00
define void @test_constant_imm() { ret void }
define void @test_constant_cimm() { ret void }
[ARM] GlobalISel: Select G_GEP At this point, G_GEP is just an add, so we treat it exactly like a G_ADD. llvm-svn: 296462
2017-02-28 18:14:38 +08:00
[ARM] GlobalISel: Select G_SEQUENCE and G_EXTRACT Since they're only used for passing around double precision floating point values into the general purpose registers, we'll lower them to VMOVDRR and VMOVRRD. llvm-svn: 295310
2017-02-16 20:19:57 +08:00
define void @test_soft_fp_double() #0 { ret void }
Fix test to work on swift/cyclone too I forgot to remove the neonfp target feature from the test, which means we'd have trouble selecting VADDS on targets that have neonfp enabled by default. llvm-svn: 294451
2017-02-08 22:23:30 +08:00
attributes #0 = { "target-features"="+vfp2,-neonfp" }
[ARM] GlobalISel: Add support for G_MUL Support G_MUL, very similar to G_ADD and G_SUB. The only difference is in the instruction selector, where we have to select either MUL or MULv5 depending on the target. llvm-svn: 300665
2017-04-19 15:29:46 +08:00
attributes #1 = { "target-features"="+v6" }
[ARM] GlobalISel: Support G_(S|U)DIV for s32 Add support for both targets with hardware division and without. For hardware division we have to add support throughout the pipeline (legalizer, reg bank select, instruction select). For targets without hardware division, we only need to mark it as a libcall. llvm-svn: 301164
2017-04-24 16:20:05 +08:00
attributes #2 = { "target-features"="+hwdiv-arm" }
[ARM] GlobalISel: Select add i32, i32 Add the minimal support necessary to select a function that returns the sum of two i32 values. This includes some support for argument/return lowering of i32 values through registers, as well as the handling of copy and add instructions throughout the GlobalISel pipeline. Differential Revision: https://reviews.llvm.org/D26677 llvm-svn: 289940
2016-12-16 20:54:46 +08:00
...
---
[ARM] GlobalISel: Support i1 add and ABI extensions Add support for: * i1 add * i1 function arguments, if passed through registers * i1 returns, with ABI signext/zeroext Differential Revision: https://reviews.llvm.org/D27706 llvm-svn: 293035
2017-01-25 16:47:40 +08:00
name: test_zext_s1
# CHECK-LABEL: name: test_zext_s1
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
body: |
bb.0:
liveins: %r0
%0(s1) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = G_ZEXT %0(s1)
; CHECK: [[VREGEXT:%[0-9]+]] = ANDri [[VREGX]], 1, 14, _, _
%r0 = COPY %1(s32)
; CHECK: %r0 = COPY [[VREGEXT]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_sext_s1
# CHECK-LABEL: name: test_sext_s1
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
body: |
bb.0:
liveins: %r0
%0(s1) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = G_SEXT %0(s1)
; CHECK: [[VREGAND:%[0-9]+]] = ANDri [[VREGX]], 1, 14, _, _
; CHECK: [[VREGEXT:%[0-9]+]] = RSBri [[VREGAND]], 0, 14, _, _
%r0 = COPY %1(s32)
; CHECK: %r0 = COPY [[VREGEXT]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
[ARM] GlobalISel: Support i8/i16 ABI extensions At the moment, this means supporting the signext/zeroext attribute on the return type of the function. For function arguments, signext/zeroext should be handled by the caller, so there's nothing for us to do until we start lowering calls. Note that this does not include support for other extensions (i8 to i16), those will be added later. Differential Revision: https://reviews.llvm.org/D27705 llvm-svn: 293034
2017-01-25 16:10:40 +08:00
---
name: test_sext_s8
# CHECK-LABEL: name: test_sext_s8
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
body: |
bb.0:
liveins: %r0
%0(s8) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = G_SEXT %0(s8)
; CHECK: [[VREGEXT:%[0-9]+]] = SXTB [[VREGX]], 0, 14, _
%r0 = COPY %1(s32)
; CHECK: %r0 = COPY [[VREGEXT]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_zext_s16
# CHECK-LABEL: name: test_zext_s16
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
body: |
bb.0:
liveins: %r0
%0(s16) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = G_ZEXT %0(s16)
; CHECK: [[VREGEXT:%[0-9]+]] = UXTH [[VREGX]], 0, 14, _
%r0 = COPY %1(s32)
; CHECK: %r0 = COPY [[VREGEXT]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
[ARM][GlobalISel] Support for G_ANYEXT G_ANYEXT can be introduced by the legalizer when widening scalars. Add support for it in the register bank info (same mapping as everything else) and in the instruction selector. When selecting it, we treat it as a COPY, just like G_TRUNC. On this occasion we get rid of some assertions in selectCopy so we can reuse it. This shouldn't be a problem at the moment since we're not supporting any complicated cases (e.g. FPR, different register banks). We might want to separate the paths when we do. llvm-svn: 302778
2017-05-11 16:28:31 +08:00
name: test_anyext_s8
# CHECK-LABEL: name: test_anyext_s8
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
body: |
bb.0:
liveins: %r0
%0(s8) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = G_ANYEXT %0(s8)
; CHECK: [[VREGEXT:%[0-9]+]] = COPY [[VREGX]]
%r0 = COPY %1(s32)
; CHECK: %r0 = COPY [[VREGEXT]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_anyext_s16
# CHECK-LABEL: name: test_anyext_s16
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
body: |
bb.0:
liveins: %r0
%0(s16) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = G_ANYEXT %0(s16)
; CHECK: [[VREGEXT:%[0-9]+]] = COPY [[VREGX]]
%r0 = COPY %1(s32)
; CHECK: %r0 = COPY [[VREGEXT]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
[ARM] GlobalISel: Add support for G_TRUNC Select them as copies. We only select if both the source and the destination are on the same register bank, so this shouldn't cause any trouble. llvm-svn: 300971
2017-04-21 21:16:50 +08:00
name: test_trunc_s32_16
# CHECK-LABEL: name: test_trunc_s32_16
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
# CHECK-DAG: id: 0, class: gpr
# CHECK-DAG: id: 1, class: gpr
body: |
bb.0:
liveins: %r0
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s16) = G_TRUNC %0(s32)
; CHECK: [[VREGTRUNC:%[0-9]+]] = COPY [[VREGX]]
%r0 = COPY %1(s16)
; CHECK: %r0 = COPY [[VREGTRUNC]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
[ARM] GlobalISel: Select i8 and i16 copies Teach the instruction selector that it's ok to copy small values from physical registers. First part of https://reviews.llvm.org/D27704 llvm-svn: 290104
2016-12-19 22:07:50 +08:00
name: test_add_s8
# CHECK-LABEL: name: test_add_s8
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
[ARM][GlobalISel] Legalize narrow scalar ops by widening This is the same as r292827 for AArch64: we widen 8- and 16-bit ADD, SUB and MUL to 32 bits since we only have TableGen patterns for 32 bits. See the commit message for r292827 for more details. At this point we could just remove some of the tests for regbankselect and instruction-select, since we're not going to see any narrow operations at those levels anymore. Instead I decided to update them with G_ANYEXT/G_TRUNC operations, so we can validate the full sequences generated by the legalizer. llvm-svn: 302782
2017-05-11 17:45:57 +08:00
- { id: 3, class: gprb }
- { id: 4, class: gprb }
- { id: 5, class: gprb }
[ARM] GlobalISel: Select i8 and i16 copies Teach the instruction selector that it's ok to copy small values from physical registers. First part of https://reviews.llvm.org/D27704 llvm-svn: 290104
2016-12-19 22:07:50 +08:00
# CHECK-DAG: id: 0, class: gpr
# CHECK-DAG: id: 1, class: gpr
# CHECK-DAG: id: 2, class: gpr
[ARM][GlobalISel] Legalize narrow scalar ops by widening This is the same as r292827 for AArch64: we widen 8- and 16-bit ADD, SUB and MUL to 32 bits since we only have TableGen patterns for 32 bits. See the commit message for r292827 for more details. At this point we could just remove some of the tests for regbankselect and instruction-select, since we're not going to see any narrow operations at those levels anymore. Instead I decided to update them with G_ANYEXT/G_TRUNC operations, so we can validate the full sequences generated by the legalizer. llvm-svn: 302782
2017-05-11 17:45:57 +08:00
# CHECK-DAG: id: 3, class: gpr
# CHECK-DAG: id: 4, class: gpr
# CHECK-DAG: id: 5, class: gpr
[ARM] GlobalISel: Select i8 and i16 copies Teach the instruction selector that it's ok to copy small values from physical registers. First part of https://reviews.llvm.org/D27704 llvm-svn: 290104
2016-12-19 22:07:50 +08:00
body: |
bb.0:
liveins: %r0, %r1
%0(s8) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
[ARM] GlobalISel: Allow i8 and i16 adds Teach the instruction selector and legalizer that it's ok to have adds with 8 or 16-bit integers. This is the second part of https://reviews.llvm.org/D27704 llvm-svn: 290105
2016-12-19 22:07:56 +08:00
%1(s8) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
[ARM][GlobalISel] Legalize narrow scalar ops by widening This is the same as r292827 for AArch64: we widen 8- and 16-bit ADD, SUB and MUL to 32 bits since we only have TableGen patterns for 32 bits. See the commit message for r292827 for more details. At this point we could just remove some of the tests for regbankselect and instruction-select, since we're not going to see any narrow operations at those levels anymore. Instead I decided to update them with G_ANYEXT/G_TRUNC operations, so we can validate the full sequences generated by the legalizer. llvm-svn: 302782
2017-05-11 17:45:57 +08:00
%2(s32) = G_ANYEXT %0(s8)
; CHECK: [[VREGXEXT:%[0-9]+]] = COPY [[VREGX]]
[ARM] GlobalISel: Allow i8 and i16 adds Teach the instruction selector and legalizer that it's ok to have adds with 8 or 16-bit integers. This is the second part of https://reviews.llvm.org/D27704 llvm-svn: 290105
2016-12-19 22:07:56 +08:00
[ARM][GlobalISel] Legalize narrow scalar ops by widening This is the same as r292827 for AArch64: we widen 8- and 16-bit ADD, SUB and MUL to 32 bits since we only have TableGen patterns for 32 bits. See the commit message for r292827 for more details. At this point we could just remove some of the tests for regbankselect and instruction-select, since we're not going to see any narrow operations at those levels anymore. Instead I decided to update them with G_ANYEXT/G_TRUNC operations, so we can validate the full sequences generated by the legalizer. llvm-svn: 302782
2017-05-11 17:45:57 +08:00
%3(s32) = G_ANYEXT %1(s8)
; CHECK: [[VREGYEXT:%[0-9]+]] = COPY [[VREGY]]
%4(s32) = G_ADD %2, %3
; CHECK: [[VREGSUM:%[0-9]+]] = ADDrr [[VREGXEXT]], [[VREGYEXT]], 14, _, _
%5(s8) = G_TRUNC %4(s32)
; CHECK: [[VREGSUMTR:%[0-9]+]] = COPY [[VREGSUM]]
%r0 = COPY %5(s8)
; CHECK: %r0 = COPY [[VREGSUMTR]]
[ARM] GlobalISel: Select i8 and i16 copies Teach the instruction selector that it's ok to copy small values from physical registers. First part of https://reviews.llvm.org/D27704 llvm-svn: 290104
2016-12-19 22:07:50 +08:00
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_add_s16
# CHECK-LABEL: name: test_add_s16
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
[ARM][GlobalISel] Legalize narrow scalar ops by widening This is the same as r292827 for AArch64: we widen 8- and 16-bit ADD, SUB and MUL to 32 bits since we only have TableGen patterns for 32 bits. See the commit message for r292827 for more details. At this point we could just remove some of the tests for regbankselect and instruction-select, since we're not going to see any narrow operations at those levels anymore. Instead I decided to update them with G_ANYEXT/G_TRUNC operations, so we can validate the full sequences generated by the legalizer. llvm-svn: 302782
2017-05-11 17:45:57 +08:00
- { id: 3, class: gprb }
- { id: 4, class: gprb }
- { id: 5, class: gprb }
[ARM] GlobalISel: Select i8 and i16 copies Teach the instruction selector that it's ok to copy small values from physical registers. First part of https://reviews.llvm.org/D27704 llvm-svn: 290104
2016-12-19 22:07:50 +08:00
# CHECK-DAG: id: 0, class: gpr
# CHECK-DAG: id: 1, class: gpr
# CHECK-DAG: id: 2, class: gpr
[ARM][GlobalISel] Legalize narrow scalar ops by widening This is the same as r292827 for AArch64: we widen 8- and 16-bit ADD, SUB and MUL to 32 bits since we only have TableGen patterns for 32 bits. See the commit message for r292827 for more details. At this point we could just remove some of the tests for regbankselect and instruction-select, since we're not going to see any narrow operations at those levels anymore. Instead I decided to update them with G_ANYEXT/G_TRUNC operations, so we can validate the full sequences generated by the legalizer. llvm-svn: 302782
2017-05-11 17:45:57 +08:00
# CHECK-DAG: id: 3, class: gpr
# CHECK-DAG: id: 4, class: gpr
# CHECK-DAG: id: 5, class: gpr
[ARM] GlobalISel: Select i8 and i16 copies Teach the instruction selector that it's ok to copy small values from physical registers. First part of https://reviews.llvm.org/D27704 llvm-svn: 290104
2016-12-19 22:07:50 +08:00
body: |
bb.0:
liveins: %r0, %r1
%0(s16) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
[ARM] GlobalISel: Allow i8 and i16 adds Teach the instruction selector and legalizer that it's ok to have adds with 8 or 16-bit integers. This is the second part of https://reviews.llvm.org/D27704 llvm-svn: 290105
2016-12-19 22:07:56 +08:00
%1(s16) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
[ARM][GlobalISel] Legalize narrow scalar ops by widening This is the same as r292827 for AArch64: we widen 8- and 16-bit ADD, SUB and MUL to 32 bits since we only have TableGen patterns for 32 bits. See the commit message for r292827 for more details. At this point we could just remove some of the tests for regbankselect and instruction-select, since we're not going to see any narrow operations at those levels anymore. Instead I decided to update them with G_ANYEXT/G_TRUNC operations, so we can validate the full sequences generated by the legalizer. llvm-svn: 302782
2017-05-11 17:45:57 +08:00
%2(s32) = G_ANYEXT %0(s16)
; CHECK: [[VREGXEXT:%[0-9]+]] = COPY [[VREGX]]
[ARM] GlobalISel: Allow i8 and i16 adds Teach the instruction selector and legalizer that it's ok to have adds with 8 or 16-bit integers. This is the second part of https://reviews.llvm.org/D27704 llvm-svn: 290105
2016-12-19 22:07:56 +08:00
[ARM][GlobalISel] Legalize narrow scalar ops by widening This is the same as r292827 for AArch64: we widen 8- and 16-bit ADD, SUB and MUL to 32 bits since we only have TableGen patterns for 32 bits. See the commit message for r292827 for more details. At this point we could just remove some of the tests for regbankselect and instruction-select, since we're not going to see any narrow operations at those levels anymore. Instead I decided to update them with G_ANYEXT/G_TRUNC operations, so we can validate the full sequences generated by the legalizer. llvm-svn: 302782
2017-05-11 17:45:57 +08:00
%3(s32) = G_ANYEXT %1(s16)
; CHECK: [[VREGYEXT:%[0-9]+]] = COPY [[VREGY]]
%4(s32) = G_ADD %2, %3
; CHECK: [[VREGSUM:%[0-9]+]] = ADDrr [[VREGXEXT]], [[VREGYEXT]], 14, _, _
%5(s16) = G_TRUNC %4(s32)
; CHECK: [[VREGSUMTR:%[0-9]+]] = COPY [[VREGSUM]]
%r0 = COPY %5(s16)
; CHECK: %r0 = COPY [[VREGSUMTR]]
[ARM] GlobalISel: Select i8 and i16 copies Teach the instruction selector that it's ok to copy small values from physical registers. First part of https://reviews.llvm.org/D27704 llvm-svn: 290104
2016-12-19 22:07:50 +08:00
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_add_s32
# CHECK-LABEL: name: test_add_s32
[ARM] GlobalISel: Select add i32, i32 Add the minimal support necessary to select a function that returns the sum of two i32 values. This includes some support for argument/return lowering of i32 values through registers, as well as the handling of copy and add instructions throughout the GlobalISel pipeline. Differential Revision: https://reviews.llvm.org/D26677 llvm-svn: 289940
2016-12-16 20:54:46 +08:00
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
[ARM] GlobalISel: Minor style fixup in test llvm-svn: 290107
2016-12-19 22:08:06 +08:00
# CHECK: id: 0, class: gpr
# CHECK: id: 1, class: gpr
# CHECK: id: 2, class: gpr
[ARM] GlobalISel: Select add i32, i32 Add the minimal support necessary to select a function that returns the sum of two i32 values. This includes some support for argument/return lowering of i32 values through registers, as well as the handling of copy and add instructions throughout the GlobalISel pipeline. Differential Revision: https://reviews.llvm.org/D26677 llvm-svn: 289940
2016-12-16 20:54:46 +08:00
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
%2(s32) = G_ADD %0, %1
; CHECK: [[VREGSUM:%[0-9]+]] = ADDrr [[VREGX]], [[VREGY]], 14, _, _
%r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGSUM]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
[ARM] GlobalISel: Support loading from the stack Add support for selecting simple G_LOAD and G_FRAME_INDEX instructions (32-bit scalars only). This will be useful for functions that need to pass arguments on the stack. First part of https://reviews.llvm.org/D27195. llvm-svn: 290096
2016-12-19 19:26:31 +08:00
---
[ARM] GlobalISel: Add FPR reg bank Add a register bank for floating point values and select simple instructions using them (add, copies from GPR). This assumes that the hardware can cope with a single precision add (VADDS) instruction, so the legalizer will treat G_FADD as legal and the instruction selector will refuse to select if the hardware doesn't support it. In the future we'll want to be more careful about this, and legalize to libcalls if we have to use soft float. llvm-svn: 294442
2017-02-08 21:23:04 +08:00
name: test_fadd_s32
# CHECK-LABEL: name: test_fadd_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
# CHECK: id: 0, class: spr
# CHECK: id: 1, class: spr
# CHECK: id: 2, class: spr
body: |
bb.0:
liveins: %s0, %s1
%0(s32) = COPY %s0
; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
%1(s32) = COPY %s1
; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
%2(s32) = G_FADD %0, %1
; CHECK: [[VREGSUM:%[0-9]+]] = VADDS [[VREGX]], [[VREGY]], 14, _
%s0 = COPY %2(s32)
; CHECK: %s0 = COPY [[VREGSUM]]
BX_RET 14, _, implicit %s0
; CHECK: BX_RET 14, _, implicit %s0
...
---
[ARM] GlobalISel: Select double G_FADD and copies Just use VADDD if available, bail out if not. llvm-svn: 295309
2017-02-16 20:19:52 +08:00
name: test_fadd_s64
# CHECK-LABEL: name: test_fadd_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
# CHECK: id: 0, class: dpr
# CHECK: id: 1, class: dpr
# CHECK: id: 2, class: dpr
body: |
bb.0:
liveins: %d0, %d1
%0(s64) = COPY %d0
; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
%1(s64) = COPY %d1
; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
%2(s64) = G_FADD %0, %1
; CHECK: [[VREGSUM:%[0-9]+]] = VADDD [[VREGX]], [[VREGY]], 14, _
%d0 = COPY %2(s64)
; CHECK: %d0 = COPY [[VREGSUM]]
BX_RET 14, _, implicit %d0
; CHECK: BX_RET 14, _, implicit %d0
...
---
[ARM] GlobalISel: Add support for G_SUB Support G_SUB throughout the GlobalISel pipeline. It is exactly the same as G_ADD, nothing fancy. llvm-svn: 300546
2017-04-18 20:35:28 +08:00
name: test_sub_s8
# CHECK-LABEL: name: test_sub_s8
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
[ARM][GlobalISel] Legalize narrow scalar ops by widening This is the same as r292827 for AArch64: we widen 8- and 16-bit ADD, SUB and MUL to 32 bits since we only have TableGen patterns for 32 bits. See the commit message for r292827 for more details. At this point we could just remove some of the tests for regbankselect and instruction-select, since we're not going to see any narrow operations at those levels anymore. Instead I decided to update them with G_ANYEXT/G_TRUNC operations, so we can validate the full sequences generated by the legalizer. llvm-svn: 302782
2017-05-11 17:45:57 +08:00
- { id: 3, class: gprb }
- { id: 4, class: gprb }
- { id: 5, class: gprb }
[ARM] GlobalISel: Add support for G_SUB Support G_SUB throughout the GlobalISel pipeline. It is exactly the same as G_ADD, nothing fancy. llvm-svn: 300546
2017-04-18 20:35:28 +08:00
# CHECK-DAG: id: 0, class: gpr
# CHECK-DAG: id: 1, class: gpr
# CHECK-DAG: id: 2, class: gpr
[ARM][GlobalISel] Legalize narrow scalar ops by widening This is the same as r292827 for AArch64: we widen 8- and 16-bit ADD, SUB and MUL to 32 bits since we only have TableGen patterns for 32 bits. See the commit message for r292827 for more details. At this point we could just remove some of the tests for regbankselect and instruction-select, since we're not going to see any narrow operations at those levels anymore. Instead I decided to update them with G_ANYEXT/G_TRUNC operations, so we can validate the full sequences generated by the legalizer. llvm-svn: 302782
2017-05-11 17:45:57 +08:00
# CHECK-DAG: id: 3, class: gpr
# CHECK-DAG: id: 4, class: gpr
# CHECK-DAG: id: 5, class: gpr
[ARM] GlobalISel: Add support for G_SUB Support G_SUB throughout the GlobalISel pipeline. It is exactly the same as G_ADD, nothing fancy. llvm-svn: 300546
2017-04-18 20:35:28 +08:00
body: |
bb.0:
liveins: %r0, %r1
%0(s8) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s8) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
[ARM][GlobalISel] Legalize narrow scalar ops by widening This is the same as r292827 for AArch64: we widen 8- and 16-bit ADD, SUB and MUL to 32 bits since we only have TableGen patterns for 32 bits. See the commit message for r292827 for more details. At this point we could just remove some of the tests for regbankselect and instruction-select, since we're not going to see any narrow operations at those levels anymore. Instead I decided to update them with G_ANYEXT/G_TRUNC operations, so we can validate the full sequences generated by the legalizer. llvm-svn: 302782
2017-05-11 17:45:57 +08:00
%2(s32) = G_ANYEXT %0(s8)
; CHECK: [[VREGXEXT:%[0-9]+]] = COPY [[VREGX]]
[ARM] GlobalISel: Add support for G_SUB Support G_SUB throughout the GlobalISel pipeline. It is exactly the same as G_ADD, nothing fancy. llvm-svn: 300546
2017-04-18 20:35:28 +08:00
[ARM][GlobalISel] Legalize narrow scalar ops by widening This is the same as r292827 for AArch64: we widen 8- and 16-bit ADD, SUB and MUL to 32 bits since we only have TableGen patterns for 32 bits. See the commit message for r292827 for more details. At this point we could just remove some of the tests for regbankselect and instruction-select, since we're not going to see any narrow operations at those levels anymore. Instead I decided to update them with G_ANYEXT/G_TRUNC operations, so we can validate the full sequences generated by the legalizer. llvm-svn: 302782
2017-05-11 17:45:57 +08:00
%3(s32) = G_ANYEXT %1(s8)
; CHECK: [[VREGYEXT:%[0-9]+]] = COPY [[VREGY]]
%4(s32) = G_SUB %2, %3
; CHECK: [[VREGRES:%[0-9]+]] = SUBrr [[VREGXEXT]], [[VREGYEXT]], 14, _, _
%5(s8) = G_TRUNC %4(s32)
; CHECK: [[VREGRESTR:%[0-9]+]] = COPY [[VREGRES]]
%r0 = COPY %5(s8)
; CHECK: %r0 = COPY [[VREGRESTR]]
[ARM] GlobalISel: Add support for G_SUB Support G_SUB throughout the GlobalISel pipeline. It is exactly the same as G_ADD, nothing fancy. llvm-svn: 300546
2017-04-18 20:35:28 +08:00
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_sub_s16
# CHECK-LABEL: name: test_sub_s16
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
[ARM][GlobalISel] Legalize narrow scalar ops by widening This is the same as r292827 for AArch64: we widen 8- and 16-bit ADD, SUB and MUL to 32 bits since we only have TableGen patterns for 32 bits. See the commit message for r292827 for more details. At this point we could just remove some of the tests for regbankselect and instruction-select, since we're not going to see any narrow operations at those levels anymore. Instead I decided to update them with G_ANYEXT/G_TRUNC operations, so we can validate the full sequences generated by the legalizer. llvm-svn: 302782
2017-05-11 17:45:57 +08:00
- { id: 3, class: gprb }
- { id: 4, class: gprb }
- { id: 5, class: gprb }
[ARM] GlobalISel: Add support for G_SUB Support G_SUB throughout the GlobalISel pipeline. It is exactly the same as G_ADD, nothing fancy. llvm-svn: 300546
2017-04-18 20:35:28 +08:00
# CHECK-DAG: id: 0, class: gpr
# CHECK-DAG: id: 1, class: gpr
# CHECK-DAG: id: 2, class: gpr
[ARM][GlobalISel] Legalize narrow scalar ops by widening This is the same as r292827 for AArch64: we widen 8- and 16-bit ADD, SUB and MUL to 32 bits since we only have TableGen patterns for 32 bits. See the commit message for r292827 for more details. At this point we could just remove some of the tests for regbankselect and instruction-select, since we're not going to see any narrow operations at those levels anymore. Instead I decided to update them with G_ANYEXT/G_TRUNC operations, so we can validate the full sequences generated by the legalizer. llvm-svn: 302782
2017-05-11 17:45:57 +08:00
# CHECK-DAG: id: 3, class: gpr
# CHECK-DAG: id: 4, class: gpr
# CHECK-DAG: id: 5, class: gpr
[ARM] GlobalISel: Add support for G_SUB Support G_SUB throughout the GlobalISel pipeline. It is exactly the same as G_ADD, nothing fancy. llvm-svn: 300546
2017-04-18 20:35:28 +08:00
body: |
bb.0:
liveins: %r0, %r1
%0(s16) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s16) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
[ARM][GlobalISel] Legalize narrow scalar ops by widening This is the same as r292827 for AArch64: we widen 8- and 16-bit ADD, SUB and MUL to 32 bits since we only have TableGen patterns for 32 bits. See the commit message for r292827 for more details. At this point we could just remove some of the tests for regbankselect and instruction-select, since we're not going to see any narrow operations at those levels anymore. Instead I decided to update them with G_ANYEXT/G_TRUNC operations, so we can validate the full sequences generated by the legalizer. llvm-svn: 302782
2017-05-11 17:45:57 +08:00
%2(s32) = G_ANYEXT %0(s16)
; CHECK: [[VREGXEXT:%[0-9]+]] = COPY [[VREGX]]
[ARM] GlobalISel: Add support for G_SUB Support G_SUB throughout the GlobalISel pipeline. It is exactly the same as G_ADD, nothing fancy. llvm-svn: 300546
2017-04-18 20:35:28 +08:00
[ARM][GlobalISel] Legalize narrow scalar ops by widening This is the same as r292827 for AArch64: we widen 8- and 16-bit ADD, SUB and MUL to 32 bits since we only have TableGen patterns for 32 bits. See the commit message for r292827 for more details. At this point we could just remove some of the tests for regbankselect and instruction-select, since we're not going to see any narrow operations at those levels anymore. Instead I decided to update them with G_ANYEXT/G_TRUNC operations, so we can validate the full sequences generated by the legalizer. llvm-svn: 302782
2017-05-11 17:45:57 +08:00
%3(s32) = G_ANYEXT %1(s16)
; CHECK: [[VREGYEXT:%[0-9]+]] = COPY [[VREGY]]
%4(s32) = G_SUB %2, %3
; CHECK: [[VREGRES:%[0-9]+]] = SUBrr [[VREGXEXT]], [[VREGYEXT]], 14, _, _
%5(s16) = G_TRUNC %4(s32)
; CHECK: [[VREGRESTR:%[0-9]+]] = COPY [[VREGRES]]
%r0 = COPY %5(s16)
; CHECK: %r0 = COPY [[VREGRESTR]]
[ARM] GlobalISel: Add support for G_SUB Support G_SUB throughout the GlobalISel pipeline. It is exactly the same as G_ADD, nothing fancy. llvm-svn: 300546
2017-04-18 20:35:28 +08:00
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_sub_s32
# CHECK-LABEL: name: test_sub_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
# CHECK: id: 0, class: gpr
# CHECK: id: 1, class: gpr
# CHECK: id: 2, class: gpr
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
%2(s32) = G_SUB %0, %1
; CHECK: [[VREGRES:%[0-9]+]] = SUBrr [[VREGX]], [[VREGY]], 14, _, _
%r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGRES]]
BX_RET 14, _, implicit %r0
[ARM] GlobalISel: Add support for G_MUL Support G_MUL, very similar to G_ADD and G_SUB. The only difference is in the instruction selector, where we have to select either MUL or MULv5 depending on the target. llvm-svn: 300665
2017-04-19 15:29:46 +08:00
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_mul_s8
# CHECK-LABEL: name: test_mul_s8
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
[ARM][GlobalISel] Legalize narrow scalar ops by widening This is the same as r292827 for AArch64: we widen 8- and 16-bit ADD, SUB and MUL to 32 bits since we only have TableGen patterns for 32 bits. See the commit message for r292827 for more details. At this point we could just remove some of the tests for regbankselect and instruction-select, since we're not going to see any narrow operations at those levels anymore. Instead I decided to update them with G_ANYEXT/G_TRUNC operations, so we can validate the full sequences generated by the legalizer. llvm-svn: 302782
2017-05-11 17:45:57 +08:00
- { id: 3, class: gprb }
- { id: 4, class: gprb }
- { id: 5, class: gprb }
# CHECK-DAG: id: 0, class: gpr
# CHECK-DAG: id: 1, class: gpr
[ARM] GlobalISel: Add support for G_MUL Support G_MUL, very similar to G_ADD and G_SUB. The only difference is in the instruction selector, where we have to select either MUL or MULv5 depending on the target. llvm-svn: 300665
2017-04-19 15:29:46 +08:00
# CHECK-DAG: id: 2, class: gprnopc
[ARM][GlobalISel] Legalize narrow scalar ops by widening This is the same as r292827 for AArch64: we widen 8- and 16-bit ADD, SUB and MUL to 32 bits since we only have TableGen patterns for 32 bits. See the commit message for r292827 for more details. At this point we could just remove some of the tests for regbankselect and instruction-select, since we're not going to see any narrow operations at those levels anymore. Instead I decided to update them with G_ANYEXT/G_TRUNC operations, so we can validate the full sequences generated by the legalizer. llvm-svn: 302782
2017-05-11 17:45:57 +08:00
# CHECK-DAG: id: 3, class: gprnopc
# CHECK-DAG: id: 4, class: gprnopc
# CHECK-DAG: id: 5, class: gpr
[ARM] GlobalISel: Add support for G_MUL Support G_MUL, very similar to G_ADD and G_SUB. The only difference is in the instruction selector, where we have to select either MUL or MULv5 depending on the target. llvm-svn: 300665
2017-04-19 15:29:46 +08:00
body: |
bb.0:
liveins: %r0, %r1
%0(s8) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s8) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
[ARM][GlobalISel] Legalize narrow scalar ops by widening This is the same as r292827 for AArch64: we widen 8- and 16-bit ADD, SUB and MUL to 32 bits since we only have TableGen patterns for 32 bits. See the commit message for r292827 for more details. At this point we could just remove some of the tests for regbankselect and instruction-select, since we're not going to see any narrow operations at those levels anymore. Instead I decided to update them with G_ANYEXT/G_TRUNC operations, so we can validate the full sequences generated by the legalizer. llvm-svn: 302782
2017-05-11 17:45:57 +08:00
%2(s32) = G_ANYEXT %0(s8)
; CHECK: [[VREGXEXT:%[0-9]+]] = COPY [[VREGX]]
[ARM] GlobalISel: Add support for G_MUL Support G_MUL, very similar to G_ADD and G_SUB. The only difference is in the instruction selector, where we have to select either MUL or MULv5 depending on the target. llvm-svn: 300665
2017-04-19 15:29:46 +08:00
[ARM][GlobalISel] Legalize narrow scalar ops by widening This is the same as r292827 for AArch64: we widen 8- and 16-bit ADD, SUB and MUL to 32 bits since we only have TableGen patterns for 32 bits. See the commit message for r292827 for more details. At this point we could just remove some of the tests for regbankselect and instruction-select, since we're not going to see any narrow operations at those levels anymore. Instead I decided to update them with G_ANYEXT/G_TRUNC operations, so we can validate the full sequences generated by the legalizer. llvm-svn: 302782
2017-05-11 17:45:57 +08:00
%3(s32) = G_ANYEXT %1(s8)
; CHECK: [[VREGYEXT:%[0-9]+]] = COPY [[VREGY]]
%4(s32) = G_MUL %2, %3
; CHECK: [[VREGRES:%[0-9]+]] = MUL [[VREGXEXT]], [[VREGYEXT]], 14, _, _
%5(s8) = G_TRUNC %4(s32)
; CHECK: [[VREGRESTR:%[0-9]+]] = COPY [[VREGRES]]
%r0 = COPY %5(s8)
; CHECK: %r0 = COPY [[VREGRESTR]]
[ARM] GlobalISel: Add support for G_MUL Support G_MUL, very similar to G_ADD and G_SUB. The only difference is in the instruction selector, where we have to select either MUL or MULv5 depending on the target. llvm-svn: 300665
2017-04-19 15:29:46 +08:00
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_mul_s16
# CHECK-LABEL: name: test_mul_s16
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
[ARM][GlobalISel] Legalize narrow scalar ops by widening This is the same as r292827 for AArch64: we widen 8- and 16-bit ADD, SUB and MUL to 32 bits since we only have TableGen patterns for 32 bits. See the commit message for r292827 for more details. At this point we could just remove some of the tests for regbankselect and instruction-select, since we're not going to see any narrow operations at those levels anymore. Instead I decided to update them with G_ANYEXT/G_TRUNC operations, so we can validate the full sequences generated by the legalizer. llvm-svn: 302782
2017-05-11 17:45:57 +08:00
- { id: 3, class: gprb }
- { id: 4, class: gprb }
- { id: 5, class: gprb }
# CHECK-DAG: id: 0, class: gpr
# CHECK-DAG: id: 1, class: gpr
[ARM] GlobalISel: Add support for G_MUL Support G_MUL, very similar to G_ADD and G_SUB. The only difference is in the instruction selector, where we have to select either MUL or MULv5 depending on the target. llvm-svn: 300665
2017-04-19 15:29:46 +08:00
# CHECK-DAG: id: 2, class: gprnopc
[ARM][GlobalISel] Legalize narrow scalar ops by widening This is the same as r292827 for AArch64: we widen 8- and 16-bit ADD, SUB and MUL to 32 bits since we only have TableGen patterns for 32 bits. See the commit message for r292827 for more details. At this point we could just remove some of the tests for regbankselect and instruction-select, since we're not going to see any narrow operations at those levels anymore. Instead I decided to update them with G_ANYEXT/G_TRUNC operations, so we can validate the full sequences generated by the legalizer. llvm-svn: 302782
2017-05-11 17:45:57 +08:00
# CHECK-DAG: id: 3, class: gprnopc
# CHECK-DAG: id: 4, class: gprnopc
# CHECK-DAG: id: 5, class: gpr
[ARM] GlobalISel: Add support for G_MUL Support G_MUL, very similar to G_ADD and G_SUB. The only difference is in the instruction selector, where we have to select either MUL or MULv5 depending on the target. llvm-svn: 300665
2017-04-19 15:29:46 +08:00
body: |
bb.0:
liveins: %r0, %r1
%0(s16) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s16) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
[ARM][GlobalISel] Legalize narrow scalar ops by widening This is the same as r292827 for AArch64: we widen 8- and 16-bit ADD, SUB and MUL to 32 bits since we only have TableGen patterns for 32 bits. See the commit message for r292827 for more details. At this point we could just remove some of the tests for regbankselect and instruction-select, since we're not going to see any narrow operations at those levels anymore. Instead I decided to update them with G_ANYEXT/G_TRUNC operations, so we can validate the full sequences generated by the legalizer. llvm-svn: 302782
2017-05-11 17:45:57 +08:00
%2(s32) = G_ANYEXT %0(s16)
; CHECK: [[VREGXEXT:%[0-9]+]] = COPY [[VREGX]]
[ARM] GlobalISel: Add support for G_MUL Support G_MUL, very similar to G_ADD and G_SUB. The only difference is in the instruction selector, where we have to select either MUL or MULv5 depending on the target. llvm-svn: 300665
2017-04-19 15:29:46 +08:00
[ARM][GlobalISel] Legalize narrow scalar ops by widening This is the same as r292827 for AArch64: we widen 8- and 16-bit ADD, SUB and MUL to 32 bits since we only have TableGen patterns for 32 bits. See the commit message for r292827 for more details. At this point we could just remove some of the tests for regbankselect and instruction-select, since we're not going to see any narrow operations at those levels anymore. Instead I decided to update them with G_ANYEXT/G_TRUNC operations, so we can validate the full sequences generated by the legalizer. llvm-svn: 302782
2017-05-11 17:45:57 +08:00
%3(s32) = G_ANYEXT %1(s16)
; CHECK: [[VREGYEXT:%[0-9]+]] = COPY [[VREGY]]
%4(s32) = G_MUL %2, %3
; CHECK: [[VREGRES:%[0-9]+]] = MUL [[VREGXEXT]], [[VREGYEXT]], 14, _, _
%5(s16) = G_TRUNC %4(s32)
; CHECK: [[VREGRESTR:%[0-9]+]] = COPY [[VREGRES]]
%r0 = COPY %5(s16)
; CHECK: %r0 = COPY [[VREGRESTR]]
[ARM] GlobalISel: Add support for G_MUL Support G_MUL, very similar to G_ADD and G_SUB. The only difference is in the instruction selector, where we have to select either MUL or MULv5 depending on the target. llvm-svn: 300665
2017-04-19 15:29:46 +08:00
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_mul_s32
# CHECK-LABEL: name: test_mul_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
# CHECK: id: 0, class: gprnopc
# CHECK: id: 1, class: gprnopc
# CHECK: id: 2, class: gprnopc
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
%2(s32) = G_MUL %0, %1
; CHECK: [[VREGRES:%[0-9]+]] = MUL [[VREGX]], [[VREGY]], 14, _, _
%r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGRES]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_mulv5_s32
# CHECK-LABEL: name: test_mulv5_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
# CHECK: id: 0, class: gprnopc
# CHECK: id: 1, class: gprnopc
# CHECK: id: 2, class: gprnopc
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
%2(s32) = G_MUL %0, %1
; CHECK: early-clobber [[VREGRES:%[0-9]+]] = MULv5 [[VREGX]], [[VREGY]], 14, _, _
%r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGRES]]
BX_RET 14, _, implicit %r0
[ARM] GlobalISel: Add support for G_SUB Support G_SUB throughout the GlobalISel pipeline. It is exactly the same as G_ADD, nothing fancy. llvm-svn: 300546
2017-04-18 20:35:28 +08:00
; CHECK: BX_RET 14, _, implicit %r0
...
---
[ARM] GlobalISel: Support G_(S|U)DIV for s32 Add support for both targets with hardware division and without. For hardware division we have to add support throughout the pipeline (legalizer, reg bank select, instruction select). For targets without hardware division, we only need to mark it as a libcall. llvm-svn: 301164
2017-04-24 16:20:05 +08:00
name: test_sdiv_s32
# CHECK-LABEL: name: test_sdiv_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
# CHECK: id: 0, class: gpr
# CHECK: id: 1, class: gpr
# CHECK: id: 2, class: gpr
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
%2(s32) = G_SDIV %0, %1
; CHECK: [[VREGRES:%[0-9]+]] = SDIV [[VREGX]], [[VREGY]], 14, _
%r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGRES]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_udiv_s32
# CHECK-LABEL: name: test_udiv_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
# CHECK: id: 0, class: gpr
# CHECK: id: 1, class: gpr
# CHECK: id: 2, class: gpr
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
%2(s32) = G_UDIV %0, %1
; CHECK: [[VREGRES:%[0-9]+]] = UDIV [[VREGX]], [[VREGY]], 14, _
%r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGRES]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
[ARM] GlobalISel: Support G_AND This is identical to the support for the other binary operators: - widen to s32 - map into GPR - select ANDrr (via TableGen'erated code) llvm-svn: 304885
2017-06-07 17:17:41 +08:00
name: test_and_s32
# CHECK-LABEL: name: test_and_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
# CHECK: id: 0, class: gpr
# CHECK: id: 1, class: gpr
# CHECK: id: 2, class: gpr
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
%2(s32) = G_AND %0, %1
; CHECK: [[VREGRES:%[0-9]+]] = ANDrr [[VREGX]], [[VREGY]], 14, _
%r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGRES]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
[ARM] GlobalISel: Support G_OR Same as the other binary operators: - legalize to 32 bits - map to GPRs - select ORRrr thanks to TableGen'erated code llvm-svn: 304890
2017-06-07 18:14:23 +08:00
name: test_or_s32
# CHECK-LABEL: name: test_or_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
# CHECK: id: 0, class: gpr
# CHECK: id: 1, class: gpr
# CHECK: id: 2, class: gpr
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
%2(s32) = G_OR %0, %1
; CHECK: [[VREGRES:%[0-9]+]] = ORRrr [[VREGX]], [[VREGY]], 14, _
%r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGRES]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
[ARM] GlobalISel: Support G_XOR Same as the other binary operators: - legalize to 32 bits - map to GPRs - select to EORrr via TableGen'erated code llvm-svn: 304898
2017-06-07 19:57:30 +08:00
name: test_xor_s32
# CHECK-LABEL: name: test_xor_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
# CHECK: id: 0, class: gpr
# CHECK: id: 1, class: gpr
# CHECK: id: 2, class: gpr
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
%2(s32) = G_XOR %0, %1
; CHECK: [[VREGRES:%[0-9]+]] = EORrr [[VREGX]], [[VREGY]], 14, _
%r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGRES]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
[ARM] GlobalISel: Support loading from the stack Add support for selecting simple G_LOAD and G_FRAME_INDEX instructions (32-bit scalars only). This will be useful for functions that need to pass arguments on the stack. First part of https://reviews.llvm.org/D27195. llvm-svn: 290096
2016-12-19 19:26:31 +08:00
name: test_load_from_stack
# CHECK-LABEL: name: test_load_from_stack
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
[ARM] GlobalISel: Add more checks to test llvm-svn: 290108
2016-12-19 22:08:11 +08:00
# CHECK-DAG: id: 0, class: gpr
# CHECK-DAG: id: 1, class: gpr
# CHECK-DAG: id: 2, class: gpr
# CHECK-DAG: id: 3, class: gpr
[ARM] GlobalISel: Support loading from the stack Add support for selecting simple G_LOAD and G_FRAME_INDEX instructions (32-bit scalars only). This will be useful for functions that need to pass arguments on the stack. First part of https://reviews.llvm.org/D27195. llvm-svn: 290096
2016-12-19 19:26:31 +08:00
fixedStack:
[ARM] GlobalISel: Load i1, i8 and i16 args from stack Add support for loading i1, i8 and i16 arguments from the stack, with or without the ABI extension flags. When the ABI extension flags are present, we load a 4-byte value, otherwise we preserve the size of the load and let the instruction selector replace it with a LDRB/LDRH. This generates the same thing as DAGISel. Differential Revision: https://reviews.llvm.org/D27803 llvm-svn: 293163
2017-01-26 17:20:47 +08:00
- { id: 0, offset: 0, size: 1, alignment: 4, isImmutable: true, isAliased: false }
[ARM] GlobalISel: Support loading from the stack Add support for selecting simple G_LOAD and G_FRAME_INDEX instructions (32-bit scalars only). This will be useful for functions that need to pass arguments on the stack. First part of https://reviews.llvm.org/D27195. llvm-svn: 290096
2016-12-19 19:26:31 +08:00
- { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
- { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false }
[Improve CodeGen Testing] This patch renables MIRPrinter print fields which have value equal to its default. If -simplify-mir option is passed then MIRPrinter will not print such fields. This change also required some lit test cases in CodeGen directory to be changed. Reviewed By: MatzeB Differential Revision: https://reviews.llvm.org/D32304 llvm-svn: 304779
2017-06-06 16:16:19 +08:00
# CHECK-DAG: id: [[FI1:[0-9]+]], type: default, offset: 0, size: 1
# CHECK-DAG: id: [[FI32:[0-9]+]], type: default, offset: 8
[ARM] GlobalISel: Support loading from the stack Add support for selecting simple G_LOAD and G_FRAME_INDEX instructions (32-bit scalars only). This will be useful for functions that need to pass arguments on the stack. First part of https://reviews.llvm.org/D27195. llvm-svn: 290096
2016-12-19 19:26:31 +08:00
body: |
bb.0:
liveins: %r0, %r1, %r2, %r3
%0(p0) = G_FRAME_INDEX %fixed-stack.2
[ARM] GlobalISel: Load i1, i8 and i16 args from stack Add support for loading i1, i8 and i16 arguments from the stack, with or without the ABI extension flags. When the ABI extension flags are present, we load a 4-byte value, otherwise we preserve the size of the load and let the instruction selector replace it with a LDRB/LDRH. This generates the same thing as DAGISel. Differential Revision: https://reviews.llvm.org/D27803 llvm-svn: 293163
2017-01-26 17:20:47 +08:00
; CHECK: [[FI32VREG:%[0-9]+]] = ADDri %fixed-stack.[[FI32]], 0, 14, _, _
[ARM] GlobalISel: Support loading from the stack Add support for selecting simple G_LOAD and G_FRAME_INDEX instructions (32-bit scalars only). This will be useful for functions that need to pass arguments on the stack. First part of https://reviews.llvm.org/D27195. llvm-svn: 290096
2016-12-19 19:26:31 +08:00
GlobalISel: verify that generic loads & stores have a mem operand. The mem operand is used by GlobalISel to convey atomic constraints so dropping it is invalid. llvm-svn: 295476
2017-02-18 02:50:15 +08:00
%1(s32) = G_LOAD %0(p0) :: (load 4)
[GlobalISel] Don't select trivially dead instructions. Folding instructions when selecting can cause them to become dead. Don't select these dead instructions (if they don't have other side effects, and don't define physical registers). Preserve existing tests by adding COPYs. In some tests, the G_CONSTANT vregs never get constrained to a class: the only use of the vreg was folded into another instruction, so the G_CONSTANT, now dead, never gets selected. llvm-svn: 298224
2017-03-20 00:13:00 +08:00
; CHECK: [[LD32VREG:%[0-9]+]] = LDRi12 [[FI32VREG]], 0, 14, _
%r0 = COPY %1
; CHECK: %r0 = COPY [[LD32VREG]]
[ARM] GlobalISel: Load i1, i8 and i16 args from stack Add support for loading i1, i8 and i16 arguments from the stack, with or without the ABI extension flags. When the ABI extension flags are present, we load a 4-byte value, otherwise we preserve the size of the load and let the instruction selector replace it with a LDRB/LDRH. This generates the same thing as DAGISel. Differential Revision: https://reviews.llvm.org/D27803 llvm-svn: 293163
2017-01-26 17:20:47 +08:00
%2(p0) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[FI1VREG:%[0-9]+]] = ADDri %fixed-stack.[[FI1]], 0, 14, _, _
GlobalISel: verify that generic loads & stores have a mem operand. The mem operand is used by GlobalISel to convey atomic constraints so dropping it is invalid. llvm-svn: 295476
2017-02-18 02:50:15 +08:00
%3(s1) = G_LOAD %2(p0) :: (load 1)
[GlobalISel] Don't select trivially dead instructions. Folding instructions when selecting can cause them to become dead. Don't select these dead instructions (if they don't have other side effects, and don't define physical registers). Preserve existing tests by adding COPYs. In some tests, the G_CONSTANT vregs never get constrained to a class: the only use of the vreg was folded into another instruction, so the G_CONSTANT, now dead, never gets selected. llvm-svn: 298224
2017-03-20 00:13:00 +08:00
; CHECK: [[LD1VREG:%[0-9]+]] = LDRBi12 [[FI1VREG]], 0, 14, _
%r0 = COPY %3
; CHECK: %r0 = COPY [[LD1VREG]]
[ARM] GlobalISel: Support loading from the stack Add support for selecting simple G_LOAD and G_FRAME_INDEX instructions (32-bit scalars only). This will be useful for functions that need to pass arguments on the stack. First part of https://reviews.llvm.org/D27195. llvm-svn: 290096
2016-12-19 19:26:31 +08:00
BX_RET 14, _
; CHECK: BX_RET 14, _
...
[ARM] GlobalISel: Select G_SEQUENCE and G_EXTRACT Since they're only used for passing around double precision floating point values into the general purpose registers, we'll lower them to VMOVDRR and VMOVRRD. llvm-svn: 295310
2017-02-16 20:19:57 +08:00
---
[ARM] GlobalISel: Select floating point loads llvm-svn: 295321
2017-02-16 22:10:50 +08:00
name: test_load_f32
# CHECK-LABEL: name: test_load_f32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: fprb }
# CHECK-DAG: id: [[P:[0-9]+]], class: gpr
# CHECK-DAG: id: [[V:[0-9]+]], class: spr
body: |
bb.0:
liveins: %r0, %r1, %r2, %r3
%0(p0) = COPY %r0
GlobalISel: verify that generic loads & stores have a mem operand. The mem operand is used by GlobalISel to convey atomic constraints so dropping it is invalid. llvm-svn: 295476
2017-02-18 02:50:15 +08:00
%1(s32) = G_LOAD %0(p0) :: (load 4)
[ARM] GlobalISel: Select floating point loads llvm-svn: 295321
2017-02-16 22:10:50 +08:00
; CHECK: %[[V]] = VLDRS %[[P]], 0, 14, _
%s0 = COPY %1
; CHECK: %s0 = COPY %[[V]]
BX_RET 14, _, implicit %s0
; CHECK: BX_RET 14, _, implicit %s0
...
---
name: test_load_f64
# CHECK-LABEL: name: test_load_f64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: fprb }
# CHECK-DAG: id: [[P:[0-9]+]], class: gpr
# CHECK-DAG: id: [[V:[0-9]+]], class: dpr
body: |
bb.0:
liveins: %r0, %r1, %r2, %r3
%0(p0) = COPY %r0
GlobalISel: verify that generic loads & stores have a mem operand. The mem operand is used by GlobalISel to convey atomic constraints so dropping it is invalid. llvm-svn: 295476
2017-02-18 02:50:15 +08:00
%1(s64) = G_LOAD %0(p0) :: (load 8)
[ARM] GlobalISel: Select floating point loads llvm-svn: 295321
2017-02-16 22:10:50 +08:00
; CHECK: %[[V]] = VLDRD %[[P]], 0, 14, _
%d0 = COPY %1
; CHECK: %d0 = COPY %[[V]]
BX_RET 14, _, implicit %d0
; CHECK: BX_RET 14, _, implicit %d0
...
---
[ARM] GlobalISel: Select G_STORE Same as selecting G_LOAD. llvm-svn: 296122
2017-02-24 22:01:27 +08:00
name: test_stores
# CHECK-LABEL: name: test_stores
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
- { id: 4, class: fprb }
- { id: 5, class: fprb }
# CHECK: id: [[P:[0-9]+]], class: gpr
# CHECK: id: [[I8:[0-9]+]], class: gpr
# CHECK: id: [[I16:[0-9]+]], class: gpr
# CHECK: id: [[I32:[0-9]+]], class: gpr
# CHECK: id: [[F32:[0-9]+]], class: spr
# CHECK: id: [[F64:[0-9]+]], class: dpr
body: |
bb.0:
liveins: %r0, %r1, %r2, %r3
%0(p0) = COPY %r0
%1(s8) = COPY %r3
%2(s16) = COPY %r2
%3(s32) = COPY %r1
%4(s32) = COPY %s0
%5(s64) = COPY %d2
G_STORE %1(s8), %0(p0) :: (store 1)
; CHECK: STRBi12 %[[I8]], %[[P]], 0, 14, _
G_STORE %2(s16), %0(p0) :: (store 2)
; CHECK: STRH %[[I16]], %[[P]], _, 0, 14, _
G_STORE %3(s32), %0(p0) :: (store 4)
; CHECK: STRi12 %[[I32]], %[[P]], 0, 14, _
G_STORE %4(s32), %0(p0) :: (store 4)
; CHECK: VSTRS %[[F32]], %[[P]], 0, 14, _
G_STORE %5(s64), %0(p0) :: (store 8)
; CHECK: VSTRD %[[F64]], %[[P]], 0, 14, _
BX_RET 14, _
...
---
[ARM] GlobalISel: Select G_GEP At this point, G_GEP is just an add, so we treat it exactly like a G_ADD. llvm-svn: 296462
2017-02-28 18:14:38 +08:00
name: test_gep
# CHECK-LABEL: name: test_gep
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
# CHECK: id: [[PTR:[0-9]+]], class: gpr
# CHECK: id: [[OFF:[0-9]+]], class: gpr
# CHECK: id: [[GEP:[0-9]+]], class: gpr
body: |
bb.0:
liveins: %r0, %r1
%0(p0) = COPY %r0
%1(s32) = COPY %r1
%2(p0) = G_GEP %0, %1(s32)
; CHECK: %[[GEP]] = ADDrr %[[PTR]], %[[OFF]], 14, _, _
%r0 = COPY %2(p0)
BX_RET 14, _, implicit %r0
...
---
[ARM] GlobalISel: Select G_CONSTANT with CImm operands When selecting a G_CONSTANT to a MOVi, we need the value to be an Imm operand. We used to just leave the G_CONSTANT operand unchanged, which works in some cases (such as the GEP offsets that we create when referring to stack slots). However, in many other places the G_CONSTANTs are created with CImm operands. This patch makes sure to handle those as well, and to error out gracefully if in the end we don't end up with an Imm operand. Thanks to Oliver Stannard for reporting this issue. llvm-svn: 301162
2017-04-24 14:30:56 +08:00
name: test_constant_imm
# CHECK-LABEL: name: test_constant_imm
[ARM] GlobalISel: Select 32-bit G_CONSTANT Put it into a register by means of a MOVi. llvm-svn: 296471
2017-02-28 21:05:42 +08:00
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
# CHECK: id: [[C:[0-9]+]], class: gpr
body: |
bb.0:
%0(s32) = G_CONSTANT 42
; CHECK: %[[C]] = MOVi 42, 14, _, _
%r0 = COPY %0(s32)
BX_RET 14, _, implicit %r0
...
---
[ARM] GlobalISel: Select G_CONSTANT with CImm operands When selecting a G_CONSTANT to a MOVi, we need the value to be an Imm operand. We used to just leave the G_CONSTANT operand unchanged, which works in some cases (such as the GEP offsets that we create when referring to stack slots). However, in many other places the G_CONSTANTs are created with CImm operands. This patch makes sure to handle those as well, and to error out gracefully if in the end we don't end up with an Imm operand. Thanks to Oliver Stannard for reporting this issue. llvm-svn: 301162
2017-04-24 14:30:56 +08:00
name: test_constant_cimm
# CHECK-LABEL: name: test_constant_cimm
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
# CHECK: id: [[C:[0-9]+]], class: gpr
body: |
bb.0:
; Adding a type on G_CONSTANT changes its operand from an Imm into a CImm.
; We still want to see the same thing in the output though.
%0(s32) = G_CONSTANT i32 42
; CHECK: %[[C]] = MOVi 42, 14, _, _
%r0 = COPY %0(s32)
BX_RET 14, _, implicit %r0
...
---
[ARM] GlobalISel: Select G_SEQUENCE and G_EXTRACT Since they're only used for passing around double precision floating point values into the general purpose registers, we'll lower them to VMOVDRR and VMOVRRD. llvm-svn: 295310
2017-02-16 20:19:57 +08:00
name: test_soft_fp_double
# CHECK-LABEL: name: test_soft_fp_double
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: fprb }
- { id: 3, class: gprb }
- { id: 4, class: gprb }
# CHECK-DAG: id: {{[0-9]+}}, class: gpr
# CHECK-DAG: id: {{[0-9]+}}, class: gpr
# CHECK-DAG: id: {{[0-9]+}}, class: gpr
# CHECK-DAG: id: {{[0-9]+}}, class: gpr
# CHECK-DAG: id: [[DREG:[0-9]+]], class: dpr
body: |
bb.0:
liveins: %r0, %r1, %r2, %r3
%0(s32) = COPY %r2
; CHECK: [[IN1:%[0-9]+]] = COPY %r2
%1(s32) = COPY %r3
; CHECK: [[IN2:%[0-9]+]] = COPY %r3
[ARM] GlobalISel: Purge G_SEQUENCE According to the commit message from r296921, G_MERGE_VALUES and G_INSERT are to be preferred over G_SEQUENCE. Therefore, stop generating G_SEQUENCE in the ARM backend and remove the code dealing with it. This boils down to the code breaking up double values for the soft float calling convention. Use G_MERGE_VALUES + G_UNMERGE_VALUES instead of G_SEQUENCE + G_EXTRACT for it. This maps very nicely to VMOVDRR + VMOVRRD and simplifies the code in the instruction selector. There's one occurence of G_SEQUENCE left in arm-irtranslator.ll, but that is part of the target-independent code for translating constant structs. Therefore, it is beyond the scope of this commit. llvm-svn: 304902
2017-06-07 20:35:05 +08:00
%2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
[ARM] GlobalISel: Select G_SEQUENCE and G_EXTRACT Since they're only used for passing around double precision floating point values into the general purpose registers, we'll lower them to VMOVDRR and VMOVRRD. llvm-svn: 295310
2017-02-16 20:19:57 +08:00
; CHECK: %[[DREG]] = VMOVDRR [[IN1]], [[IN2]]
[ARM] GlobalISel: Purge G_SEQUENCE According to the commit message from r296921, G_MERGE_VALUES and G_INSERT are to be preferred over G_SEQUENCE. Therefore, stop generating G_SEQUENCE in the ARM backend and remove the code dealing with it. This boils down to the code breaking up double values for the soft float calling convention. Use G_MERGE_VALUES + G_UNMERGE_VALUES instead of G_SEQUENCE + G_EXTRACT for it. This maps very nicely to VMOVDRR + VMOVRRD and simplifies the code in the instruction selector. There's one occurence of G_SEQUENCE left in arm-irtranslator.ll, but that is part of the target-independent code for translating constant structs. Therefore, it is beyond the scope of this commit. llvm-svn: 304902
2017-06-07 20:35:05 +08:00
%3(s32), %4(s32) = G_UNMERGE_VALUES %2(s64)
; CHECK: [[OUT1:%[0-9]+]], [[OUT2:%[0-9]+]] = VMOVRRD %[[DREG]]
[ARM] GlobalISel: Select G_SEQUENCE and G_EXTRACT Since they're only used for passing around double precision floating point values into the general purpose registers, we'll lower them to VMOVDRR and VMOVRRD. llvm-svn: 295310
2017-02-16 20:19:57 +08:00
%r0 = COPY %3
; CHECK: %r0 = COPY [[OUT1]]
%r1 = COPY %4
; CHECK: %r1 = COPY [[OUT2]]
BX_RET 14, _, implicit %r0, implicit %r1
; CHECK: BX_RET 14, _, implicit %r0, implicit %r1
...