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llvm-project/llvm/test/MC/ARM/basic-arm-instructions-v8.s

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Add AArch32 DCPS{1,2,3} and HLT instructions. These were pretty straightforward instructions, with some assembly support required for HLT. The ARM assembler is keen to split the instruction mnemonic into a (non-existent) 'H' instruction with the LT condition code. An exception for HLT is needed. HLT follows the same rules as BKPT when in IT blocks, so the special BKPT hadling code has been adapted to handle HLT also. Regression tests added including diagnostic tests for out of range immediates and illegal condition codes, as well as negative tests for pre-ARMv8. llvm-svn: 190053
2013-09-05 22:14:19 +08:00
@ New ARMv8 A32 encodings
Test cleanup for v8 instructions Add some missing tests, factor out a test not specific to v8 into its own file. llvm-svn: 193611
2013-10-29 22:16:09 +08:00
@ RUN: llvm-mc -triple armv8 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-V8
Add AArch32 DCPS{1,2,3} and HLT instructions. These were pretty straightforward instructions, with some assembly support required for HLT. The ARM assembler is keen to split the instruction mnemonic into a (non-existent) 'H' instruction with the LT condition code. An exception for HLT is needed. HLT follows the same rules as BKPT when in IT blocks, so the special BKPT hadling code has been adapted to handle HLT also. Regression tests added including diagnostic tests for out of range immediates and illegal condition codes, as well as negative tests for pre-ARMv8. llvm-svn: 190053
2013-09-05 22:14:19 +08:00
@ RUN: not llvm-mc -triple armv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
@ HLT
hlt #0
hlt #65535
@ CHECK-V8: hlt #0 @ encoding: [0x70,0x00,0x00,0xe1]
@ CHECK-V8: hlt #65535 @ encoding: [0x7f,0xff,0x0f,0xe1]
@ CHECK-V7: error: instruction requires: armv8
@ CHECK-V7: error: instruction requires: armv8
@ AL condition code allowable
hltal #0
@ CHECK-V8: hlt #0 @ encoding: [0x70,0x00,0x00,0xe1]
@ CHECK-V7: error: instruction requires: armv8
[ARMv8] Implement the new DMB/DSB operands. This removes the custom ISD Node: MEMBARRIER and replaces it with an intrinsic. llvm-svn: 190055
2013-09-05 23:35:24 +08:00
@------------------------------------------------------------------------------
@ DMB (v8 barriers)
@------------------------------------------------------------------------------
dmb ishld
dmb oshld
dmb nshld
dmb ld
@ CHECK-V8: dmb ishld @ encoding: [0x59,0xf0,0x7f,0xf5]
@ CHECK-V8: dmb oshld @ encoding: [0x51,0xf0,0x7f,0xf5]
@ CHECK-V8: dmb nshld @ encoding: [0x55,0xf0,0x7f,0xf5]
@ CHECK-V8: dmb ld @ encoding: [0x5d,0xf0,0x7f,0xf5]
@ CHECK-V7: error: invalid operand for instruction
@ CHECK-V7: error: invalid operand for instruction
@ CHECK-V7: error: invalid operand for instruction
@ CHECK-V7: error: invalid operand for instruction
@------------------------------------------------------------------------------
@ DSB (v8 barriers)
@------------------------------------------------------------------------------
dsb ishld
dsb oshld
dsb nshld
dsb ld
@ CHECK-V8: dsb ishld @ encoding: [0x49,0xf0,0x7f,0xf5]
@ CHECK-V8: dsb oshld @ encoding: [0x41,0xf0,0x7f,0xf5]
@ CHECK-V8: dsb nshld @ encoding: [0x45,0xf0,0x7f,0xf5]
@ CHECK-V8: dsb ld @ encoding: [0x4d,0xf0,0x7f,0xf5]
@ CHECK-V7: error: invalid operand for instruction
@ CHECK-V7: error: invalid operand for instruction
@ CHECK-V7: error: invalid operand for instruction
Test cleanup for v8 instructions Add some missing tests, factor out a test not specific to v8 into its own file. llvm-svn: 193611
2013-10-29 22:16:09 +08:00
@ CHECK-V7: error: invalid operand for instruction
[ARM] Introduce the 'sevl' instruction in ARMv8. This also removes the restriction on the immediate field of the 'hint' instruction. llvm-svn: 191744
2013-10-01 20:39:11 +08:00
@------------------------------------------------------------------------------
@ SEVL
@------------------------------------------------------------------------------
sevl
Test cleanup for v8 instructions Add some missing tests, factor out a test not specific to v8 into its own file. llvm-svn: 193611
2013-10-29 22:16:09 +08:00
@ CHECK-V8: sevl @ encoding: [0x05,0xf0,0x20,0xe3]
@ CHECK-V7: error: instruction requires: armv8