2012-02-19 10:03:36 +08:00
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//===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
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2010-02-10 07:52:19 +08:00
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//
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2019-01-19 16:50:56 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2012-02-18 20:03:15 +08:00
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//
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2010-02-10 07:52:19 +08:00
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//===----------------------------------------------------------------------===//
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//
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// This file provides pattern fragments useful for SIMD instructions.
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//
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//===----------------------------------------------------------------------===//
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2015-02-05 21:22:50 +08:00
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//===----------------------------------------------------------------------===//
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// MMX specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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// Low word of MMX to GPR.
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def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
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[SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
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2015-02-05 21:23:07 +08:00
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// GPR to low word of MMX.
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def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
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[SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
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2015-02-05 21:22:50 +08:00
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2010-02-10 07:52:19 +08:00
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//===----------------------------------------------------------------------===//
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// MMX Pattern Fragments
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//===----------------------------------------------------------------------===//
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2010-10-01 07:57:10 +08:00
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def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
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2010-07-13 07:41:28 +08:00
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//===----------------------------------------------------------------------===//
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// SSE specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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2017-03-13 07:05:00 +08:00
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def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>,
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SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
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SDTCisVT<3, i8>]>;
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2010-07-13 07:41:28 +08:00
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def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
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def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
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2017-02-22 14:54:18 +08:00
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def X86fmins : SDNode<"X86ISD::FMINS", SDTFPBinOp>;
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def X86fmaxs : SDNode<"X86ISD::FMAXS", SDTFPBinOp>;
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2012-08-19 21:06:16 +08:00
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// Commutative and Associative FMIN and FMAX.
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def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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2010-07-13 07:41:28 +08:00
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def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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2016-08-15 12:47:28 +08:00
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def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp>;
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2010-07-13 07:41:28 +08:00
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def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
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def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
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2011-09-23 04:15:48 +08:00
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def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
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def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
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2011-11-19 17:02:40 +08:00
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def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
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def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
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2010-07-13 07:41:28 +08:00
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def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
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def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
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2013-12-16 21:52:35 +08:00
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def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
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2010-07-13 07:41:28 +08:00
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def X86pshufb : SDNode<"X86ISD::PSHUFB",
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2015-11-26 15:58:20 +08:00
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SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i8>, SDTCisSameAs<0,1>,
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2010-07-13 07:41:28 +08:00
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SDTCisSameAs<0,2>]>>;
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[x86] Implement a faster vector population count based on the PSHUFB
in-register LUT technique.
Summary:
A description of this technique can be found here:
http://wm.ite.pl/articles/sse-popcount.html
The core of the idea is to use an in-register lookup table and the
PSHUFB instruction to compute the population count for the low and high
nibbles of each byte, and then to use horizontal sums to aggregate these
into vector population counts with wider element types.
On x86 there is an instruction that will directly compute the horizontal
sum for the low 8 and high 8 bytes, giving vNi64 popcount very easily.
Various tricks are used to get vNi32 and vNi16 from the vNi8 that the
LUT computes.
The base implemantion of this, and most of the work, was done by Bruno
in a follow up to D6531. See Bruno's detailed post there for lots of
timing information about these changes.
I have extended Bruno's patch in the following ways:
0) I committed the new tests with baseline sequences so this shows
a diff, and regenerated the tests using the update scripts.
1) Bruno had noticed and mentioned in IRC a redundant mask that
I removed.
2) I introduced a particular optimization for the i32 vector cases where
we use PSHL + PSADBW to compute the the low i32 popcounts, and PSHUFD
+ PSADBW to compute doubled high i32 popcounts. This takes advantage
of the fact that to line up the high i32 popcounts we have to shift
them anyways, and we can shift them by one fewer bit to effectively
divide the count by two. While the PSHUFD based horizontal add is no
faster, it doesn't require registers or load traffic the way a mask
would, and provides more ILP as it happens on different ports with
high throughput.
3) I did some code cleanups throughout to simplify the implementation
logic.
4) I refactored it to continue to use the parallel bitmath lowering when
SSSE3 is not available to preserve the performance of that version on
SSE2 targets where it is still much better than scalarizing as we'll
still do a bitmath implementation of popcount even in scalar code
there.
With #1 and #2 above, I analyzed the result in IACA for sandybridge,
ivybridge, and haswell. In every case I measured, the throughput is the
same or better using the LUT lowering, even v2i64 and v4i64, and even
compared with using the native popcnt instruction! The latency of the
LUT lowering is often higher than the latency of the scalarized popcnt
instruction sequence, but I think those latency measurements are deeply
misleading. Keeping the operation fully in the vector unit and having
many chances for increased throughput seems much more likely to win.
With this, we can lower every integer vector popcount implementation
using the LUT strategy if we have SSSE3 or better (and thus have
PSHUFB). I've updated the operation lowering to reflect this. This also
fixes an issue where we were scalarizing horribly some AVX lowerings.
Finally, there are some remaining cleanups. There is duplication between
the two techniques in how they perform the horizontal sum once the byte
population count is computed. I'm going to factor and merge those two in
a separate follow-up commit.
Differential Revision: http://reviews.llvm.org/D10084
llvm-svn: 238636
2015-05-30 11:20:59 +08:00
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def X86psadbw : SDNode<"X86ISD::PSADBW",
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2015-11-26 15:02:21 +08:00
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SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
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SDTCVecEltisVT<1, i8>,
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SDTCisSameSizeAs<0,1>,
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2016-08-15 12:47:30 +08:00
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SDTCisSameAs<1,2>]>, [SDNPCommutative]>;
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2015-08-31 21:09:30 +08:00
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def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW",
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2015-11-26 15:02:21 +08:00
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SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i16>,
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SDTCVecEltisVT<1, i8>,
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SDTCisSameSizeAs<0,1>,
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2019-01-14 10:59:08 +08:00
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SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>>;
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2011-07-14 05:36:47 +08:00
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def X86andnp : SDNode<"X86ISD::ANDNP",
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2011-07-14 05:36:51 +08:00
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SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
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2010-12-18 06:55:37 +08:00
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SDTCisSameAs<0,2>]>>;
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2016-02-01 23:48:21 +08:00
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def X86multishift : SDNode<"X86ISD::MULTISHIFT",
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SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
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SDTCisSameAs<1,2>]>>;
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2010-07-13 07:41:28 +08:00
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def X86pextrb : SDNode<"X86ISD::PEXTRB",
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2015-11-26 15:58:20 +08:00
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SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v16i8>,
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SDTCisPtrTy<2>]>>;
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2010-07-13 07:41:28 +08:00
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def X86pextrw : SDNode<"X86ISD::PEXTRW",
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2015-11-26 15:58:20 +08:00
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SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v8i16>,
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SDTCisPtrTy<2>]>>;
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2010-07-13 07:41:28 +08:00
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def X86pinsrb : SDNode<"X86ISD::PINSRB",
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SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
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SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
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def X86pinsrw : SDNode<"X86ISD::PINSRW",
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SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
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SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
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2014-04-22 04:07:29 +08:00
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def X86insertps : SDNode<"X86ISD::INSERTPS",
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2010-07-13 07:41:28 +08:00
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SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
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[x86] Fix a pretty horrible bug and inconsistency in the x86 asm
parsing (and latent bug in the instruction definitions).
This is effectively a revert of r136287 which tried to address
a specific and narrow case of immediate operands failing to be accepted
by x86 instructions with a pretty heavy hammer: it introduced a new kind
of operand that behaved differently. All of that is removed with this
commit, but the test cases are both preserved and enhanced.
The core problem that r136287 and this commit are trying to handle is
that gas accepts both of the following instructions:
insertps $192, %xmm0, %xmm1
insertps $-64, %xmm0, %xmm1
These will encode to the same byte sequence, with the immediate
occupying an 8-bit entry. The first form was fixed by r136287 but that
broke the prior handling of the second form! =[ Ironically, we would
still emit the second form in some cases and then be unable to
re-assemble the output.
The reason why the first instruction failed to be handled is because
prior to r136287 the operands ere marked 'i32i8imm' which forces them to
be sign-extenable. Clearly, that won't work for 192 in a single byte.
However, making thim zero-extended or "unsigned" doesn't really address
the core issue either because it breaks negative immediates. The correct
fix is to make these operands 'i8imm' reflecting that they can be either
signed or unsigned but must be 8-bit immediates. This patch backs out
r136287 and then changes those places as well as some others to use
'i8imm' rather than one of the extended variants.
Naturally, this broke something else. The custom DAG nodes had to be
updated to have a much more accurate type constraint of an i8 node, and
a bunch of Pat immediates needed to be specified as i8 values.
The fallout didn't end there though. We also then ceased to be able to
match the instruction-specific intrinsics to the instructions so
modified. Digging, this is because they too used i32 rather than i8 in
their signature. So I've also switched those intrinsics to i8 arguments
in line with the instructions.
In order to make the intrinsic adjustments of course, I also had to add
auto upgrading for the intrinsics.
I suspect that the intrinsic argument types may have led everything down
this rabbit hole. Pretty happy with the result.
llvm-svn: 217310
2014-09-06 18:00:01 +08:00
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SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
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2010-07-13 07:41:28 +08:00
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def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
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SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
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2012-04-22 17:39:03 +08:00
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2019-07-15 10:02:31 +08:00
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def X86vzld : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
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[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
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def X86vextractst : SDNode<"X86ISD::VEXTRACT_STORE", SDTStore,
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[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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2019-10-02 00:28:20 +08:00
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def X86VBroadcastld : SDNode<"X86ISD::VBROADCAST_LOAD", SDTLoad,
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[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
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2012-08-15 05:24:47 +08:00
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2015-07-25 01:24:15 +08:00
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def SDTVtrunc : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
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2019-01-12 08:55:27 +08:00
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SDTCisInt<0>, SDTCisInt<1>,
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SDTCisOpSmallerThanOp<0, 1>]>;
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def SDTVmtrunc : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
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SDTCisInt<0>, SDTCisInt<1>,
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SDTCisOpSmallerThanOp<0, 1>,
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SDTCisSameAs<0, 2>,
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SDTCVecEltisVT<3, i1>,
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SDTCisSameNumEltsAs<1, 3>]>;
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2015-07-25 01:24:15 +08:00
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def X86vtrunc : SDNode<"X86ISD::VTRUNC", SDTVtrunc>;
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def X86vtruncs : SDNode<"X86ISD::VTRUNCS", SDTVtrunc>;
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def X86vtruncus : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>;
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2019-01-12 08:55:27 +08:00
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def X86vmtrunc : SDNode<"X86ISD::VMTRUNC", SDTVmtrunc>;
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def X86vmtruncs : SDNode<"X86ISD::VMTRUNCS", SDTVmtrunc>;
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def X86vmtruncus : SDNode<"X86ISD::VMTRUNCUS", SDTVmtrunc>;
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2015-07-25 01:24:15 +08:00
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2012-08-15 05:24:47 +08:00
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def X86vfpext : SDNode<"X86ISD::VFPEXT",
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2016-05-09 13:34:14 +08:00
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SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f64>,
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SDTCVecEltisVT<1, f32>,
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SDTCisSameSizeAs<0, 1>]>>;
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2012-10-11 00:53:28 +08:00
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def X86vfpround: SDNode<"X86ISD::VFPROUND",
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2016-05-09 13:34:14 +08:00
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SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>,
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SDTCVecEltisVT<1, f64>,
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2019-01-22 04:14:09 +08:00
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SDTCisOpSmallerThanOp<0, 1>]>>;
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2012-08-15 05:24:47 +08:00
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2019-03-11 12:36:51 +08:00
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def X86frounds : SDNode<"X86ISD::VFPROUNDS",
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SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>,
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SDTCisSameAs<0, 1>,
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SDTCVecEltisVT<2, f64>,
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SDTCisSameSizeAs<0, 2>]>>;
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def X86froundsRnd: SDNode<"X86ISD::VFPROUNDS_RND",
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2016-05-09 13:34:12 +08:00
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SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>,
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SDTCisSameAs<0, 1>,
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2015-09-20 22:31:19 +08:00
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SDTCVecEltisVT<2, f64>,
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2016-05-09 13:34:12 +08:00
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SDTCisSameSizeAs<0, 2>,
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2016-05-09 13:34:14 +08:00
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SDTCisVT<3, i32>]>>;
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2015-09-20 22:31:19 +08:00
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2019-03-11 12:36:51 +08:00
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def X86fpexts : SDNode<"X86ISD::VFPEXTS",
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SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f64>,
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2016-05-09 13:34:12 +08:00
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SDTCisSameAs<0, 1>,
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2015-09-20 22:31:19 +08:00
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SDTCVecEltisVT<2, f32>,
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2019-03-11 12:36:51 +08:00
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SDTCisSameSizeAs<0, 2>]>>;
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def X86fpextsSAE : SDNode<"X86ISD::VFPEXTS_SAE",
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SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f64>,
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SDTCisSameAs<0, 1>,
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SDTCVecEltisVT<2, f32>,
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SDTCisSameSizeAs<0, 2>]>>;
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2015-09-20 22:31:19 +08:00
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2019-01-13 10:59:57 +08:00
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def X86vmfpround: SDNode<"X86ISD::VMFPROUND",
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SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>,
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SDTCVecEltisVT<1, f64>,
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SDTCisSameSizeAs<0, 1>,
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SDTCisSameAs<0, 2>,
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SDTCVecEltisVT<3, i1>,
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SDTCisSameNumEltsAs<1, 3>]>>;
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2017-09-18 13:50:54 +08:00
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def X86vshiftimm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
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SDTCisVT<2, i8>, SDTCisInt<0>]>;
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def X86vshldq : SDNode<"X86ISD::VSHLDQ", X86vshiftimm>;
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def X86vshrdq : SDNode<"X86ISD::VSRLDQ", X86vshiftimm>;
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2012-01-23 07:36:02 +08:00
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def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
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2012-01-23 06:42:16 +08:00
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def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
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|
|
|
def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
|
2010-07-13 07:41:28 +08:00
|
|
|
|
2013-12-16 21:52:35 +08:00
|
|
|
def X86CmpMaskCC :
|
2015-05-07 19:24:42 +08:00
|
|
|
SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
|
|
|
|
|
SDTCisVec<1>, SDTCisSameAs<2, 1>,
|
|
|
|
|
SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
|
2013-12-16 21:52:35 +08:00
|
|
|
def X86CmpMaskCCScalar :
|
2017-09-18 13:50:54 +08:00
|
|
|
SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisFP<1>, SDTCisSameAs<1, 2>,
|
|
|
|
|
SDTCisVT<3, i8>]>;
|
2013-12-16 21:52:35 +08:00
|
|
|
|
2015-09-20 23:15:10 +08:00
|
|
|
def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
|
2019-03-11 12:36:49 +08:00
|
|
|
def X86cmpmSAE : SDNode<"X86ISD::CMPM_SAE", X86CmpMaskCC>;
|
2016-09-21 14:37:54 +08:00
|
|
|
def X86cmpms : SDNode<"X86ISD::FSETCCM", X86CmpMaskCCScalar>;
|
2019-03-11 12:36:49 +08:00
|
|
|
def X86cmpmsSAE : SDNode<"X86ISD::FSETCCM_SAE", X86CmpMaskCCScalar>;
|
2013-08-13 21:24:07 +08:00
|
|
|
|
2017-11-23 21:50:27 +08:00
|
|
|
def X86phminpos: SDNode<"X86ISD::PHMINPOS",
|
|
|
|
|
SDTypeProfile<1, 1, [SDTCisVT<0, v8i16>, SDTCisVT<1, v8i16>]>>;
|
|
|
|
|
|
2017-09-18 13:50:54 +08:00
|
|
|
def X86vshiftuniform : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
|
|
|
|
|
SDTCisVec<2>, SDTCisInt<0>,
|
2019-01-05 09:40:29 +08:00
|
|
|
SDTCisInt<2>]>;
|
2017-09-18 13:50:54 +08:00
|
|
|
|
|
|
|
|
def X86vshl : SDNode<"X86ISD::VSHL", X86vshiftuniform>;
|
|
|
|
|
def X86vsrl : SDNode<"X86ISD::VSRL", X86vshiftuniform>;
|
|
|
|
|
def X86vsra : SDNode<"X86ISD::VSRA", X86vshiftuniform>;
|
2012-01-23 03:15:14 +08:00
|
|
|
|
2017-09-18 13:50:54 +08:00
|
|
|
def X86vshiftvariable : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
|
|
|
|
|
SDTCisSameAs<0,2>, SDTCisInt<0>]>;
|
2016-06-20 15:05:43 +08:00
|
|
|
|
2019-01-17 05:46:32 +08:00
|
|
|
def X86vshlv : SDNode<"X86ISD::VSHLV", X86vshiftvariable>;
|
|
|
|
|
def X86vsrlv : SDNode<"X86ISD::VSRLV", X86vshiftvariable>;
|
2017-09-18 13:50:54 +08:00
|
|
|
def X86vsrav : SDNode<"X86ISD::VSRAV", X86vshiftvariable>;
|
|
|
|
|
|
|
|
|
|
def X86vshli : SDNode<"X86ISD::VSHLI", X86vshiftimm>;
|
|
|
|
|
def X86vsrli : SDNode<"X86ISD::VSRLI", X86vshiftimm>;
|
|
|
|
|
def X86vsrai : SDNode<"X86ISD::VSRAI", X86vshiftimm>;
|
2012-01-23 03:15:14 +08:00
|
|
|
|
2017-01-30 08:06:01 +08:00
|
|
|
def X86kshiftl : SDNode<"X86ISD::KSHIFTL",
|
|
|
|
|
SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>,
|
|
|
|
|
SDTCisSameAs<0, 1>,
|
|
|
|
|
SDTCisVT<2, i8>]>>;
|
|
|
|
|
def X86kshiftr : SDNode<"X86ISD::KSHIFTR",
|
|
|
|
|
SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>,
|
|
|
|
|
SDTCisSameAs<0, 1>,
|
|
|
|
|
SDTCisVT<2, i8>]>>;
|
|
|
|
|
|
2018-02-12 09:33:38 +08:00
|
|
|
def X86kadd : SDNode<"X86ISD::KADD", SDTIntBinOp, [SDNPCommutative]>;
|
|
|
|
|
|
2017-09-18 13:50:54 +08:00
|
|
|
def X86vrotli : SDNode<"X86ISD::VROTLI", X86vshiftimm>;
|
|
|
|
|
def X86vrotri : SDNode<"X86ISD::VROTRI", X86vshiftimm>;
|
2016-01-13 05:19:17 +08:00
|
|
|
|
2017-09-18 13:50:54 +08:00
|
|
|
def X86vpshl : SDNode<"X86ISD::VPSHL", X86vshiftvariable>;
|
|
|
|
|
def X86vpsha : SDNode<"X86ISD::VPSHA", X86vshiftvariable>;
|
2015-09-30 16:17:50 +08:00
|
|
|
|
2015-10-11 22:15:17 +08:00
|
|
|
def X86vpcom : SDNode<"X86ISD::VPCOM",
|
|
|
|
|
SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
|
2015-11-26 15:58:20 +08:00
|
|
|
SDTCisSameAs<0,2>,
|
2017-09-18 13:50:54 +08:00
|
|
|
SDTCisVT<3, i8>, SDTCisInt<0>]>>;
|
2015-10-11 22:15:17 +08:00
|
|
|
def X86vpcomu : SDNode<"X86ISD::VPCOMU",
|
|
|
|
|
SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
|
2015-11-26 15:58:20 +08:00
|
|
|
SDTCisSameAs<0,2>,
|
2017-09-18 13:50:54 +08:00
|
|
|
SDTCisVT<3, i8>, SDTCisInt<0>]>>;
|
2016-06-03 16:06:03 +08:00
|
|
|
def X86vpermil2 : SDNode<"X86ISD::VPERMIL2",
|
|
|
|
|
SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
|
|
|
|
|
SDTCisSameAs<0,2>,
|
2017-02-19 06:53:43 +08:00
|
|
|
SDTCisFP<0>, SDTCisInt<3>,
|
2018-06-12 03:20:15 +08:00
|
|
|
SDTCisSameNumEltsAs<0, 3>,
|
|
|
|
|
SDTCisSameSizeAs<0,3>,
|
2016-06-03 16:06:03 +08:00
|
|
|
SDTCisVT<4, i8>]>>;
|
2016-03-24 19:52:43 +08:00
|
|
|
def X86vpperm : SDNode<"X86ISD::VPPERM",
|
|
|
|
|
SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
|
2017-02-19 09:54:47 +08:00
|
|
|
SDTCisSameAs<0,2>, SDTCisSameAs<0, 3>]>>;
|
2016-03-24 19:52:43 +08:00
|
|
|
|
2010-07-13 07:41:28 +08:00
|
|
|
def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
|
2010-08-11 07:25:42 +08:00
|
|
|
SDTCisVec<1>,
|
|
|
|
|
SDTCisSameAs<2, 1>]>;
|
2016-03-03 22:18:38 +08:00
|
|
|
|
2016-08-15 12:47:30 +08:00
|
|
|
def X86mulhrs : SDNode<"X86ISD::MULHRS", SDTIntBinOp, [SDNPCommutative]>;
|
|
|
|
|
def X86avg : SDNode<"X86ISD::AVG" , SDTIntBinOp, [SDNPCommutative]>;
|
2010-07-13 07:41:28 +08:00
|
|
|
def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
|
2010-08-11 07:25:42 +08:00
|
|
|
def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
|
2013-08-05 16:52:21 +08:00
|
|
|
def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
|
2015-08-31 21:30:19 +08:00
|
|
|
def X86ktest : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>;
|
2016-03-03 22:18:38 +08:00
|
|
|
|
2016-04-04 02:22:03 +08:00
|
|
|
def X86movmsk : SDNode<"X86ISD::MOVMSK",
|
|
|
|
|
SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVec<1>]>>;
|
|
|
|
|
|
2016-09-25 05:42:47 +08:00
|
|
|
def X86selects : SDNode<"X86ISD::SELECTS",
|
2017-05-19 20:35:15 +08:00
|
|
|
SDTypeProfile<1, 3, [SDTCisVT<1, v1i1>,
|
2016-05-18 14:55:59 +08:00
|
|
|
SDTCisSameAs<0, 2>,
|
|
|
|
|
SDTCisSameAs<2, 3>]>>;
|
2010-07-13 07:41:28 +08:00
|
|
|
|
2012-02-05 11:14:49 +08:00
|
|
|
def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
|
2015-11-26 15:58:20 +08:00
|
|
|
SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
|
2018-03-08 16:02:52 +08:00
|
|
|
SDTCisSameAs<0,1>,
|
2016-08-15 12:47:30 +08:00
|
|
|
SDTCisSameAs<1,2>]>,
|
|
|
|
|
[SDNPCommutative]>;
|
2014-04-26 22:12:19 +08:00
|
|
|
def X86pmuldq : SDNode<"X86ISD::PMULDQ",
|
2015-11-26 15:58:20 +08:00
|
|
|
SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
|
2018-03-08 16:02:52 +08:00
|
|
|
SDTCisSameAs<0,1>,
|
2016-08-15 12:47:30 +08:00
|
|
|
SDTCisSameAs<1,2>]>,
|
|
|
|
|
[SDNPCommutative]>;
|
2012-02-05 11:14:49 +08:00
|
|
|
|
2015-07-07 04:46:41 +08:00
|
|
|
def X86extrqi : SDNode<"X86ISD::EXTRQI",
|
|
|
|
|
SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
|
|
|
|
|
SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>;
|
|
|
|
|
def X86insertqi : SDNode<"X86ISD::INSERTQI",
|
|
|
|
|
SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
|
|
|
|
|
SDTCisSameAs<1,2>, SDTCisVT<3, i8>,
|
|
|
|
|
SDTCisVT<4, i8>]>>;
|
|
|
|
|
|
2010-08-21 06:55:05 +08:00
|
|
|
// Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
|
|
|
|
|
// translated into one of the target nodes below during lowering.
|
|
|
|
|
// Note: this is a work in progress...
|
|
|
|
|
def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
|
|
|
|
|
def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
|
|
|
|
|
SDTCisSameAs<0,2>]>;
|
2018-07-21 01:57:53 +08:00
|
|
|
def SDTShuff2OpFP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisFP<0>,
|
|
|
|
|
SDTCisSameAs<0,1>, SDTCisSameAs<0,2>]>;
|
2010-08-21 06:55:05 +08:00
|
|
|
|
2014-09-23 18:08:29 +08:00
|
|
|
def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
|
2018-06-12 03:20:15 +08:00
|
|
|
SDTCisFP<0>, SDTCisInt<2>,
|
2017-02-19 09:54:47 +08:00
|
|
|
SDTCisSameNumEltsAs<0,2>,
|
2018-06-12 03:20:15 +08:00
|
|
|
SDTCisSameSizeAs<0,2>]>;
|
2010-08-21 06:55:05 +08:00
|
|
|
def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
|
2015-11-26 15:58:20 +08:00
|
|
|
SDTCisSameAs<0,1>, SDTCisVT<2, i8>]>;
|
2010-08-21 06:55:05 +08:00
|
|
|
def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
|
2015-11-26 15:58:20 +08:00
|
|
|
SDTCisSameAs<0,2>, SDTCisVT<3, i8>]>;
|
2017-11-13 10:02:58 +08:00
|
|
|
def SDTFPBinOpImm: SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>,
|
|
|
|
|
SDTCisSameAs<0,1>,
|
|
|
|
|
SDTCisSameAs<0,2>,
|
|
|
|
|
SDTCisVT<3, i32>]>;
|
2019-03-11 12:36:47 +08:00
|
|
|
def SDTFPTernaryOpImm: SDTypeProfile<1, 4, [SDTCisFP<0>, SDTCisSameAs<0,1>,
|
|
|
|
|
SDTCisSameAs<0,2>,
|
|
|
|
|
SDTCisInt<3>,
|
|
|
|
|
SDTCisSameSizeAs<0, 3>,
|
|
|
|
|
SDTCisSameNumEltsAs<0, 3>,
|
|
|
|
|
SDTCisVT<4, i32>]>;
|
2019-06-09 07:53:31 +08:00
|
|
|
def SDTFPUnaryOpImm: SDTypeProfile<1, 2, [SDTCisFP<0>,
|
2017-11-13 10:02:58 +08:00
|
|
|
SDTCisSameAs<0,1>,
|
|
|
|
|
SDTCisVT<2, i32>]>;
|
2010-08-21 06:55:05 +08:00
|
|
|
|
2013-08-07 20:34:55 +08:00
|
|
|
def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
|
2015-11-18 17:42:45 +08:00
|
|
|
def SDTVBroadcastm : SDTypeProfile<1, 1, [SDTCisVec<0>,
|
|
|
|
|
SDTCisInt<0>, SDTCisInt<1>]>;
|
2013-08-07 20:34:55 +08:00
|
|
|
|
2012-04-11 14:40:27 +08:00
|
|
|
def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
|
[x86] Fix a pretty horrible bug and inconsistency in the x86 asm
parsing (and latent bug in the instruction definitions).
This is effectively a revert of r136287 which tried to address
a specific and narrow case of immediate operands failing to be accepted
by x86 instructions with a pretty heavy hammer: it introduced a new kind
of operand that behaved differently. All of that is removed with this
commit, but the test cases are both preserved and enhanced.
The core problem that r136287 and this commit are trying to handle is
that gas accepts both of the following instructions:
insertps $192, %xmm0, %xmm1
insertps $-64, %xmm0, %xmm1
These will encode to the same byte sequence, with the immediate
occupying an 8-bit entry. The first form was fixed by r136287 but that
broke the prior handling of the second form! =[ Ironically, we would
still emit the second form in some cases and then be unable to
re-assemble the output.
The reason why the first instruction failed to be handled is because
prior to r136287 the operands ere marked 'i32i8imm' which forces them to
be sign-extenable. Clearly, that won't work for 192 in a single byte.
However, making thim zero-extended or "unsigned" doesn't really address
the core issue either because it breaks negative immediates. The correct
fix is to make these operands 'i8imm' reflecting that they can be either
signed or unsigned but must be 8-bit immediates. This patch backs out
r136287 and then changes those places as well as some others to use
'i8imm' rather than one of the extended variants.
Naturally, this broke something else. The custom DAG nodes had to be
updated to have a much more accurate type constraint of an i8 node, and
a bunch of Pat immediates needed to be specified as i8 values.
The fallout didn't end there though. We also then ceased to be able to
match the instruction-specific intrinsics to the instructions so
modified. Digging, this is because they too used i32 rather than i8 in
their signature. So I've also switched those intrinsics to i8 arguments
in line with the instructions.
In order to make the intrinsic adjustments of course, I also had to add
auto upgrading for the intrinsics.
I suspect that the intrinsic argument types may have led everything down
this rabbit hole. Pretty happy with the result.
llvm-svn: 217310
2014-09-06 18:00:01 +08:00
|
|
|
SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
|
2012-08-01 20:06:00 +08:00
|
|
|
|
2017-02-19 09:54:47 +08:00
|
|
|
def SDTTernlog : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisVec<0>,
|
|
|
|
|
SDTCisSameAs<0,1>, SDTCisSameAs<0,2>,
|
|
|
|
|
SDTCisSameAs<0,3>, SDTCisVT<4, i8>]>;
|
2015-10-15 20:33:24 +08:00
|
|
|
|
2015-02-18 15:59:20 +08:00
|
|
|
def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc.
|
2016-05-18 14:56:01 +08:00
|
|
|
SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisVT<3, i32>]>;
|
2015-02-18 15:59:20 +08:00
|
|
|
|
2015-06-03 21:41:48 +08:00
|
|
|
def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [ // fsqrt_round, fgetexp_round, etc.
|
2016-05-18 14:56:01 +08:00
|
|
|
SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisVT<2, i32>]>;
|
2015-06-03 21:41:48 +08:00
|
|
|
|
2015-01-28 18:21:27 +08:00
|
|
|
def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
|
2016-05-18 14:56:01 +08:00
|
|
|
SDTCisSameAs<1,2>, SDTCisSameAs<1,3>,
|
2017-02-19 09:54:47 +08:00
|
|
|
SDTCisFP<0>, SDTCisVT<4, i32>]>;
|
2011-08-17 10:29:19 +08:00
|
|
|
|
2017-08-17 09:48:00 +08:00
|
|
|
def X86PAlignr : SDNode<"X86ISD::PALIGNR",
|
|
|
|
|
SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i8>,
|
|
|
|
|
SDTCisSameAs<0,1>,
|
|
|
|
|
SDTCisSameAs<0,2>,
|
|
|
|
|
SDTCisVT<3, i8>]>>;
|
2014-08-06 01:22:55 +08:00
|
|
|
def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
|
2015-09-03 17:05:31 +08:00
|
|
|
|
2017-11-21 17:48:44 +08:00
|
|
|
def X86VShld : SDNode<"X86ISD::VSHLD", SDTShuff3OpI>;
|
|
|
|
|
def X86VShrd : SDNode<"X86ISD::VSHRD", SDTShuff3OpI>;
|
|
|
|
|
def X86VShldv : SDNode<"X86ISD::VSHLDV",
|
|
|
|
|
SDTypeProfile<1, 3, [SDTCisVec<0>,
|
|
|
|
|
SDTCisSameAs<0,1>,
|
|
|
|
|
SDTCisSameAs<0,2>,
|
|
|
|
|
SDTCisSameAs<0,3>]>>;
|
|
|
|
|
def X86VShrdv : SDNode<"X86ISD::VSHRDV",
|
|
|
|
|
SDTypeProfile<1, 3, [SDTCisVec<0>,
|
|
|
|
|
SDTCisSameAs<0,1>,
|
|
|
|
|
SDTCisSameAs<0,2>,
|
|
|
|
|
SDTCisSameAs<0,3>]>>;
|
|
|
|
|
|
2015-09-03 17:05:31 +08:00
|
|
|
def X86Conflict : SDNode<"X86ISD::CONFLICT", SDTIntUnaryOp>;
|
2010-08-21 06:55:05 +08:00
|
|
|
|
|
|
|
|
def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
|
|
|
|
|
def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
|
|
|
|
|
def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
|
|
|
|
|
|
2015-06-03 18:56:40 +08:00
|
|
|
def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
|
|
|
|
|
def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>;
|
2010-08-21 06:55:05 +08:00
|
|
|
|
|
|
|
|
def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
|
|
|
|
|
def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
|
|
|
|
|
def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
|
|
|
|
|
|
2019-05-16 05:16:28 +08:00
|
|
|
def X86Movsd : SDNode<"X86ISD::MOVSD",
|
|
|
|
|
SDTypeProfile<1, 2, [SDTCisVT<0, v2f64>,
|
|
|
|
|
SDTCisVT<1, v2f64>,
|
|
|
|
|
SDTCisVT<2, v2f64>]>>;
|
|
|
|
|
def X86Movss : SDNode<"X86ISD::MOVSS",
|
|
|
|
|
SDTypeProfile<1, 2, [SDTCisVT<0, v4f32>,
|
|
|
|
|
SDTCisVT<1, v4f32>,
|
|
|
|
|
SDTCisVT<2, v4f32>]>>;
|
|
|
|
|
|
|
|
|
|
def X86Movlhps : SDNode<"X86ISD::MOVLHPS",
|
|
|
|
|
SDTypeProfile<1, 2, [SDTCisVT<0, v4f32>,
|
|
|
|
|
SDTCisVT<1, v4f32>,
|
|
|
|
|
SDTCisVT<2, v4f32>]>>;
|
|
|
|
|
def X86Movhlps : SDNode<"X86ISD::MOVHLPS",
|
|
|
|
|
SDTypeProfile<1, 2, [SDTCisVT<0, v4f32>,
|
|
|
|
|
SDTCisVT<1, v4f32>,
|
|
|
|
|
SDTCisVT<2, v4f32>]>>;
|
2010-08-21 06:55:05 +08:00
|
|
|
|
2017-02-19 09:54:47 +08:00
|
|
|
def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<0>,
|
|
|
|
|
SDTCisVec<1>, SDTCisInt<1>,
|
2015-11-26 15:58:20 +08:00
|
|
|
SDTCisSameSizeAs<0,1>,
|
2017-02-19 09:54:47 +08:00
|
|
|
SDTCisSameAs<1,2>,
|
|
|
|
|
SDTCisOpSmallerThanOp<0, 1>]>;
|
2014-06-20 09:05:28 +08:00
|
|
|
def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
|
|
|
|
|
def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
|
|
|
|
|
|
2011-12-06 16:21:25 +08:00
|
|
|
def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
|
|
|
|
|
def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
|
2010-08-21 06:55:05 +08:00
|
|
|
|
2017-02-19 09:54:47 +08:00
|
|
|
def X86vpmaddubsw : SDNode<"X86ISD::VPMADDUBSW",
|
|
|
|
|
SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>,
|
|
|
|
|
SDTCVecEltisVT<1, i8>,
|
|
|
|
|
SDTCisSameSizeAs<0,1>,
|
|
|
|
|
SDTCisSameAs<1,2>]>>;
|
|
|
|
|
def X86vpmaddwd : SDNode<"X86ISD::VPMADDWD",
|
|
|
|
|
SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i32>,
|
|
|
|
|
SDTCVecEltisVT<1, i16>,
|
|
|
|
|
SDTCisSameSizeAs<0,1>,
|
|
|
|
|
SDTCisSameAs<1,2>]>,
|
|
|
|
|
[SDNPCommutative]>;
|
2015-07-21 15:11:28 +08:00
|
|
|
|
2014-09-23 18:08:29 +08:00
|
|
|
def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
|
2014-09-23 06:29:42 +08:00
|
|
|
def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
|
2015-11-30 06:53:22 +08:00
|
|
|
def X86VPermv : SDNode<"X86ISD::VPERMV",
|
|
|
|
|
SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<1>,
|
|
|
|
|
SDTCisSameNumEltsAs<0,1>,
|
|
|
|
|
SDTCisSameSizeAs<0,1>,
|
|
|
|
|
SDTCisSameAs<0,2>]>>;
|
2014-09-23 06:29:42 +08:00
|
|
|
def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
|
2015-11-27 04:02:01 +08:00
|
|
|
def X86VPermt2 : SDNode<"X86ISD::VPERMV3",
|
|
|
|
|
SDTypeProfile<1, 3, [SDTCisVec<0>,
|
2015-11-25 16:17:56 +08:00
|
|
|
SDTCisSameAs<0,1>, SDTCisInt<2>,
|
|
|
|
|
SDTCisVec<2>, SDTCisSameNumEltsAs<0, 2>,
|
2015-11-26 15:58:20 +08:00
|
|
|
SDTCisSameSizeAs<0,2>,
|
2015-11-25 16:17:56 +08:00
|
|
|
SDTCisSameAs<0,3>]>, []>;
|
|
|
|
|
|
2015-10-15 20:33:24 +08:00
|
|
|
def X86vpternlog : SDNode<"X86ISD::VPTERNLOG", SDTTernlog>;
|
Add support for 256-bit versions of VPERMIL instruction. This is a new
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:
Instead of:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vextractf128 $1, %ymm0, %xmm1
shufps $1, %xmm1, %xmm1
movss %xmm1, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm1, 16(%rsp)
vextractf128 $0, %ymm0, %xmm0
shufps $1, %xmm0, %xmm0
movss %xmm0, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm0, (%rsp)
vmovaps (%rsp), %ymm0
We get:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vpermilps $85, %ymm0, %ymm0
llvm-svn: 135662
2011-07-21 09:55:47 +08:00
|
|
|
|
2011-11-30 15:47:51 +08:00
|
|
|
def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
|
2011-08-13 05:48:26 +08:00
|
|
|
|
2019-03-11 12:36:47 +08:00
|
|
|
def X86VFixupimm : SDNode<"X86ISD::VFIXUPIMM", SDTFPTernaryOpImm>;
|
|
|
|
|
def X86VFixupimmSAE : SDNode<"X86ISD::VFIXUPIMM_SAE", SDTFPTernaryOpImm>;
|
|
|
|
|
def X86VFixupimms : SDNode<"X86ISD::VFIXUPIMMS", SDTFPTernaryOpImm>;
|
|
|
|
|
def X86VFixupimmSAEs : SDNode<"X86ISD::VFIXUPIMMS_SAE", SDTFPTernaryOpImm>;
|
2017-11-13 10:02:58 +08:00
|
|
|
def X86VRange : SDNode<"X86ISD::VRANGE", SDTFPBinOpImm>;
|
2019-03-11 12:36:55 +08:00
|
|
|
def X86VRangeSAE : SDNode<"X86ISD::VRANGE_SAE", SDTFPBinOpImm>;
|
2017-11-13 10:02:58 +08:00
|
|
|
def X86VReduce : SDNode<"X86ISD::VREDUCE", SDTFPUnaryOpImm>;
|
2019-03-11 12:36:55 +08:00
|
|
|
def X86VReduceSAE : SDNode<"X86ISD::VREDUCE_SAE", SDTFPUnaryOpImm>;
|
2017-11-13 10:02:58 +08:00
|
|
|
def X86VRndScale : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImm>;
|
2019-03-11 12:36:55 +08:00
|
|
|
def X86VRndScaleSAE: SDNode<"X86ISD::VRNDSCALE_SAE", SDTFPUnaryOpImm>;
|
2017-11-13 10:02:58 +08:00
|
|
|
def X86VGetMant : SDNode<"X86ISD::VGETMANT", SDTFPUnaryOpImm>;
|
2019-03-11 12:36:55 +08:00
|
|
|
def X86VGetMantSAE : SDNode<"X86ISD::VGETMANT_SAE", SDTFPUnaryOpImm>;
|
2015-11-27 02:31:19 +08:00
|
|
|
def X86Vfpclass : SDNode<"X86ISD::VFPCLASS",
|
2017-02-19 09:54:47 +08:00
|
|
|
SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>,
|
|
|
|
|
SDTCisFP<1>,
|
2015-11-27 03:41:34 +08:00
|
|
|
SDTCisSameNumEltsAs<0,1>,
|
|
|
|
|
SDTCisVT<2, i32>]>, []>;
|
|
|
|
|
def X86Vfpclasss : SDNode<"X86ISD::VFPCLASSS",
|
2017-05-19 20:35:15 +08:00
|
|
|
SDTypeProfile<1, 2, [SDTCisVT<0, v1i1>,
|
2015-11-27 03:41:34 +08:00
|
|
|
SDTCisFP<1>, SDTCisVT<2, i32>]>,[]>;
|
2015-06-01 14:50:49 +08:00
|
|
|
|
2015-05-18 14:42:57 +08:00
|
|
|
def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
|
|
|
|
|
SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
|
|
|
|
|
SDTCisSubVecOfVec<1, 0>]>, []>;
|
2015-11-02 15:39:36 +08:00
|
|
|
|
2011-08-17 10:29:19 +08:00
|
|
|
def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
|
2015-11-18 17:42:45 +08:00
|
|
|
def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>;
|
2011-08-17 10:29:19 +08:00
|
|
|
|
2012-12-05 17:24:57 +08:00
|
|
|
def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
|
2019-01-17 05:46:28 +08:00
|
|
|
def X86Blendv : SDNode<"X86ISD::BLENDV",
|
|
|
|
|
SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<1>,
|
|
|
|
|
SDTCisSameAs<0, 2>,
|
|
|
|
|
SDTCisSameAs<2, 3>,
|
|
|
|
|
SDTCisSameNumEltsAs<0, 1>,
|
|
|
|
|
SDTCisSameSizeAs<0, 1>]>>;
|
2014-09-16 04:09:47 +08:00
|
|
|
|
|
|
|
|
def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
|
|
|
|
|
|
2015-02-18 15:59:20 +08:00
|
|
|
def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>;
|
2019-03-11 12:36:44 +08:00
|
|
|
def X86fadds : SDNode<"X86ISD::FADDS", SDTFPBinOp>;
|
2017-02-24 15:21:10 +08:00
|
|
|
def X86faddRnds : SDNode<"X86ISD::FADDS_RND", SDTFPBinOpRound>;
|
2015-02-18 15:59:20 +08:00
|
|
|
def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>;
|
2019-03-11 12:36:44 +08:00
|
|
|
def X86fsubs : SDNode<"X86ISD::FSUBS", SDTFPBinOp>;
|
2017-02-24 15:21:10 +08:00
|
|
|
def X86fsubRnds : SDNode<"X86ISD::FSUBS_RND", SDTFPBinOpRound>;
|
2015-02-18 15:59:20 +08:00
|
|
|
def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>;
|
2019-03-11 12:36:44 +08:00
|
|
|
def X86fmuls : SDNode<"X86ISD::FMULS", SDTFPBinOp>;
|
2017-02-24 15:21:10 +08:00
|
|
|
def X86fmulRnds : SDNode<"X86ISD::FMULS_RND", SDTFPBinOpRound>;
|
2015-02-18 15:59:20 +08:00
|
|
|
def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>;
|
2019-03-11 12:36:44 +08:00
|
|
|
def X86fdivs : SDNode<"X86ISD::FDIVS", SDTFPBinOp>;
|
2017-02-24 15:21:10 +08:00
|
|
|
def X86fdivRnds : SDNode<"X86ISD::FDIVS_RND", SDTFPBinOpRound>;
|
2019-03-11 12:36:44 +08:00
|
|
|
def X86fmaxSAE : SDNode<"X86ISD::FMAX_SAE", SDTFPBinOp>;
|
|
|
|
|
def X86fmaxSAEs : SDNode<"X86ISD::FMAXS_SAE", SDTFPBinOp>;
|
|
|
|
|
def X86fminSAE : SDNode<"X86ISD::FMIN_SAE", SDTFPBinOp>;
|
|
|
|
|
def X86fminSAEs : SDNode<"X86ISD::FMINS_SAE", SDTFPBinOp>;
|
2019-03-11 12:36:59 +08:00
|
|
|
def X86scalef : SDNode<"X86ISD::SCALEF", SDTFPBinOp>;
|
|
|
|
|
def X86scalefRnd : SDNode<"X86ISD::SCALEF_RND", SDTFPBinOpRound>;
|
|
|
|
|
def X86scalefs : SDNode<"X86ISD::SCALEFS", SDTFPBinOp>;
|
|
|
|
|
def X86scalefsRnd: SDNode<"X86ISD::SCALEFS_RND", SDTFPBinOpRound>;
|
2015-09-20 17:13:41 +08:00
|
|
|
def X86fsqrtRnd : SDNode<"X86ISD::FSQRT_RND", SDTFPUnaryOpRound>;
|
2019-03-11 12:36:44 +08:00
|
|
|
def X86fsqrts : SDNode<"X86ISD::FSQRTS", SDTFPBinOp>;
|
2016-09-23 14:24:35 +08:00
|
|
|
def X86fsqrtRnds : SDNode<"X86ISD::FSQRTS_RND", SDTFPBinOpRound>;
|
2019-03-11 12:36:57 +08:00
|
|
|
def X86fgetexp : SDNode<"X86ISD::FGETEXP", SDTFPUnaryOp>;
|
|
|
|
|
def X86fgetexpSAE : SDNode<"X86ISD::FGETEXP_SAE", SDTFPUnaryOp>;
|
|
|
|
|
def X86fgetexps : SDNode<"X86ISD::FGETEXPS", SDTFPBinOp>;
|
|
|
|
|
def X86fgetexpSAEs : SDNode<"X86ISD::FGETEXPS_SAE", SDTFPBinOp>;
|
2015-02-18 15:59:20 +08:00
|
|
|
|
2017-09-04 14:59:50 +08:00
|
|
|
def X86Fmadd : SDNode<"ISD::FMA", SDTFPTernaryOp, [SDNPCommutative]>;
|
|
|
|
|
def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFPTernaryOp, [SDNPCommutative]>;
|
|
|
|
|
def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFPTernaryOp, [SDNPCommutative]>;
|
|
|
|
|
def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFPTernaryOp, [SDNPCommutative]>;
|
|
|
|
|
def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFPTernaryOp, [SDNPCommutative]>;
|
|
|
|
|
def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFPTernaryOp, [SDNPCommutative]>;
|
|
|
|
|
|
|
|
|
|
def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound, [SDNPCommutative]>;
|
|
|
|
|
def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound, [SDNPCommutative]>;
|
|
|
|
|
def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound, [SDNPCommutative]>;
|
|
|
|
|
def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound, [SDNPCommutative]>;
|
|
|
|
|
def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound, [SDNPCommutative]>;
|
|
|
|
|
def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound, [SDNPCommutative]>;
|
2017-11-26 02:32:43 +08:00
|
|
|
|
2019-05-31 10:50:41 +08:00
|
|
|
def X86vp2intersect : SDNode<"X86ISD::VP2INTERSECT",
|
|
|
|
|
SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
|
|
|
|
|
SDTCisVec<1>, SDTCisSameAs<1, 2>]>>;
|
|
|
|
|
|
2017-02-19 09:54:47 +08:00
|
|
|
def SDTIFma : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0,1>,
|
|
|
|
|
SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
|
2017-09-25 03:30:55 +08:00
|
|
|
def x86vpmadd52l : SDNode<"X86ISD::VPMADD52L", SDTIFma, [SDNPCommutative]>;
|
|
|
|
|
def x86vpmadd52h : SDNode<"X86ISD::VPMADD52H", SDTIFma, [SDNPCommutative]>;
|
2016-01-25 19:14:24 +08:00
|
|
|
|
2017-11-05 02:26:41 +08:00
|
|
|
def X86rsqrt14 : SDNode<"X86ISD::RSQRT14", SDTFPUnaryOp>;
|
|
|
|
|
def X86rcp14 : SDNode<"X86ISD::RCP14", SDTFPUnaryOp>;
|
2017-11-21 18:04:28 +08:00
|
|
|
|
|
|
|
|
// VNNI
|
|
|
|
|
def SDTVnni : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
|
|
|
|
|
SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
|
|
|
|
|
def X86Vpdpbusd : SDNode<"X86ISD::VPDPBUSD", SDTVnni>;
|
|
|
|
|
def X86Vpdpbusds : SDNode<"X86ISD::VPDPBUSDS", SDTVnni>;
|
|
|
|
|
def X86Vpdpwssd : SDNode<"X86ISD::VPDPWSSD", SDTVnni>;
|
|
|
|
|
def X86Vpdpwssds : SDNode<"X86ISD::VPDPWSSDS", SDTVnni>;
|
|
|
|
|
|
2019-03-11 12:36:57 +08:00
|
|
|
def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", SDTFPUnaryOp>;
|
|
|
|
|
def X86rsqrt28SAE: SDNode<"X86ISD::RSQRT28_SAE", SDTFPUnaryOp>;
|
|
|
|
|
def X86rcp28 : SDNode<"X86ISD::RCP28", SDTFPUnaryOp>;
|
|
|
|
|
def X86rcp28SAE : SDNode<"X86ISD::RCP28_SAE", SDTFPUnaryOp>;
|
|
|
|
|
def X86exp2 : SDNode<"X86ISD::EXP2", SDTFPUnaryOp>;
|
|
|
|
|
def X86exp2SAE : SDNode<"X86ISD::EXP2_SAE", SDTFPUnaryOp>;
|
2014-11-26 18:46:49 +08:00
|
|
|
|
2017-11-05 02:26:41 +08:00
|
|
|
def X86rsqrt14s : SDNode<"X86ISD::RSQRT14S", SDTFPBinOp>;
|
|
|
|
|
def X86rcp14s : SDNode<"X86ISD::RCP14S", SDTFPBinOp>;
|
2019-03-11 12:36:57 +08:00
|
|
|
def X86rsqrt28s : SDNode<"X86ISD::RSQRT28S", SDTFPBinOp>;
|
|
|
|
|
def X86rsqrt28SAEs : SDNode<"X86ISD::RSQRT28S_SAE", SDTFPBinOp>;
|
|
|
|
|
def X86rcp28s : SDNode<"X86ISD::RCP28S", SDTFPBinOp>;
|
|
|
|
|
def X86rcp28SAEs : SDNode<"X86ISD::RCP28S_SAE", SDTFPBinOp>;
|
2017-11-13 10:02:58 +08:00
|
|
|
def X86Ranges : SDNode<"X86ISD::VRANGES", SDTFPBinOpImm>;
|
|
|
|
|
def X86RndScales : SDNode<"X86ISD::VRNDSCALES", SDTFPBinOpImm>;
|
|
|
|
|
def X86Reduces : SDNode<"X86ISD::VREDUCES", SDTFPBinOpImm>;
|
|
|
|
|
def X86GetMants : SDNode<"X86ISD::VGETMANTS", SDTFPBinOpImm>;
|
2019-03-11 12:36:55 +08:00
|
|
|
def X86RangesSAE : SDNode<"X86ISD::VRANGES_SAE", SDTFPBinOpImm>;
|
|
|
|
|
def X86RndScalesSAE : SDNode<"X86ISD::VRNDSCALES_SAE", SDTFPBinOpImm>;
|
|
|
|
|
def X86ReducesSAE : SDNode<"X86ISD::VREDUCES_SAE", SDTFPBinOpImm>;
|
|
|
|
|
def X86GetMantsSAE : SDNode<"X86ISD::VGETMANTS_SAE", SDTFPBinOpImm>;
|
2014-11-12 15:31:03 +08:00
|
|
|
|
2019-01-22 04:02:28 +08:00
|
|
|
def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 3,
|
|
|
|
|
[SDTCisSameAs<0, 1>, SDTCisVec<1>,
|
|
|
|
|
SDTCisSameAs<0, 2>, SDTCVecEltisVT<3, i1>,
|
|
|
|
|
SDTCisSameNumEltsAs<0, 3>]>, []>;
|
|
|
|
|
def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 3,
|
|
|
|
|
[SDTCisSameAs<0, 1>, SDTCisVec<1>,
|
|
|
|
|
SDTCisSameAs<0, 2>, SDTCVecEltisVT<3, i1>,
|
|
|
|
|
SDTCisSameNumEltsAs<0, 3>]>, []>;
|
2014-12-11 23:02:24 +08:00
|
|
|
|
2017-11-23 19:15:50 +08:00
|
|
|
// vpshufbitqmb
|
|
|
|
|
def X86Vpshufbitqmb : SDNode<"X86ISD::VPSHUFBITQMB",
|
|
|
|
|
SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
|
|
|
|
|
SDTCisSameAs<1,2>,
|
|
|
|
|
SDTCVecEltisVT<0,i1>,
|
|
|
|
|
SDTCisSameNumEltsAs<0,1>]>>;
|
|
|
|
|
|
2019-03-11 12:37:01 +08:00
|
|
|
def SDTintToFP: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisFP<0>,
|
|
|
|
|
SDTCisSameAs<0,1>, SDTCisInt<2>]>;
|
2015-06-14 20:44:55 +08:00
|
|
|
def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
|
2015-11-27 02:31:19 +08:00
|
|
|
SDTCisSameAs<0,1>, SDTCisInt<2>,
|
|
|
|
|
SDTCisVT<3, i32>]>;
|
2015-06-14 20:44:55 +08:00
|
|
|
|
2015-07-13 21:26:20 +08:00
|
|
|
def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
|
2016-05-19 14:13:58 +08:00
|
|
|
SDTCisInt<0>, SDTCisFP<1>]>;
|
2015-07-13 21:26:20 +08:00
|
|
|
def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
|
2016-05-19 14:13:58 +08:00
|
|
|
SDTCisInt<0>, SDTCisFP<1>,
|
|
|
|
|
SDTCisVT<2, i32>]>;
|
2018-08-15 09:23:00 +08:00
|
|
|
def SDTSFloatToInt: SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisFP<1>,
|
|
|
|
|
SDTCisVec<1>]>;
|
2015-09-20 22:31:19 +08:00
|
|
|
def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>,
|
2016-05-19 14:13:58 +08:00
|
|
|
SDTCisVec<1>, SDTCisVT<2, i32>]>;
|
2016-11-24 20:13:46 +08:00
|
|
|
|
|
|
|
|
def SDTVintToFP: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
|
|
|
|
|
SDTCisFP<0>, SDTCisInt<1>]>;
|
2015-07-13 21:26:20 +08:00
|
|
|
def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
|
2016-05-19 14:13:58 +08:00
|
|
|
SDTCisFP<0>, SDTCisInt<1>,
|
2016-05-18 14:56:01 +08:00
|
|
|
SDTCisVT<2, i32>]>;
|
2015-07-13 21:26:20 +08:00
|
|
|
|
|
|
|
|
// Scalar
|
2019-03-11 12:37:01 +08:00
|
|
|
def X86SintToFp : SDNode<"X86ISD::SCALAR_SINT_TO_FP", SDTintToFP>;
|
2016-09-23 14:24:39 +08:00
|
|
|
def X86SintToFpRnd : SDNode<"X86ISD::SCALAR_SINT_TO_FP_RND", SDTintToFPRound>;
|
2019-03-11 12:37:01 +08:00
|
|
|
def X86UintToFp : SDNode<"X86ISD::SCALAR_UINT_TO_FP", SDTintToFP>;
|
2016-09-23 14:24:39 +08:00
|
|
|
def X86UintToFpRnd : SDNode<"X86ISD::SCALAR_UINT_TO_FP_RND", SDTintToFPRound>;
|
2015-07-13 21:26:20 +08:00
|
|
|
|
2018-08-15 09:23:00 +08:00
|
|
|
def X86cvtts2Int : SDNode<"X86ISD::CVTTS2SI", SDTSFloatToInt>;
|
|
|
|
|
def X86cvtts2UInt : SDNode<"X86ISD::CVTTS2UI", SDTSFloatToInt>;
|
2019-03-11 12:36:51 +08:00
|
|
|
def X86cvtts2IntSAE : SDNode<"X86ISD::CVTTS2SI_SAE", SDTSFloatToInt>;
|
|
|
|
|
def X86cvtts2UIntSAE : SDNode<"X86ISD::CVTTS2UI_SAE", SDTSFloatToInt>;
|
2016-02-07 22:59:13 +08:00
|
|
|
|
2018-08-15 09:23:00 +08:00
|
|
|
def X86cvts2si : SDNode<"X86ISD::CVTS2SI", SDTSFloatToInt>;
|
|
|
|
|
def X86cvts2usi : SDNode<"X86ISD::CVTS2UI", SDTSFloatToInt>;
|
|
|
|
|
def X86cvts2siRnd : SDNode<"X86ISD::CVTS2SI_RND", SDTSFloatToIntRnd>;
|
|
|
|
|
def X86cvts2usiRnd : SDNode<"X86ISD::CVTS2UI_RND", SDTSFloatToIntRnd>;
|
2016-02-07 22:59:13 +08:00
|
|
|
|
2015-07-13 21:26:20 +08:00
|
|
|
// Vector with rounding mode
|
|
|
|
|
|
|
|
|
|
// cvtt fp-to-int staff
|
2019-03-11 12:36:51 +08:00
|
|
|
def X86cvttp2siSAE : SDNode<"X86ISD::CVTTP2SI_SAE", SDTFloatToInt>;
|
|
|
|
|
def X86cvttp2uiSAE : SDNode<"X86ISD::CVTTP2UI_SAE", SDTFloatToInt>;
|
2015-07-13 21:26:20 +08:00
|
|
|
|
2016-09-23 14:24:39 +08:00
|
|
|
def X86VSintToFpRnd : SDNode<"X86ISD::SINT_TO_FP_RND", SDTVintToFPRound>;
|
|
|
|
|
def X86VUintToFpRnd : SDNode<"X86ISD::UINT_TO_FP_RND", SDTVintToFPRound>;
|
2015-07-13 21:26:20 +08:00
|
|
|
|
|
|
|
|
// cvt fp-to-int staff
|
2016-09-23 14:24:39 +08:00
|
|
|
def X86cvtp2IntRnd : SDNode<"X86ISD::CVTP2SI_RND", SDTFloatToIntRnd>;
|
|
|
|
|
def X86cvtp2UIntRnd : SDNode<"X86ISD::CVTP2UI_RND", SDTFloatToIntRnd>;
|
2015-07-13 21:26:20 +08:00
|
|
|
|
|
|
|
|
// Vector without rounding mode
|
2016-11-24 20:13:46 +08:00
|
|
|
|
|
|
|
|
// cvtt fp-to-int staff
|
|
|
|
|
def X86cvttp2si : SDNode<"X86ISD::CVTTP2SI", SDTFloatToInt>;
|
|
|
|
|
def X86cvttp2ui : SDNode<"X86ISD::CVTTP2UI", SDTFloatToInt>;
|
|
|
|
|
|
|
|
|
|
def X86VSintToFP : SDNode<"X86ISD::CVTSI2P", SDTVintToFP>;
|
|
|
|
|
def X86VUintToFP : SDNode<"X86ISD::CVTUI2P", SDTVintToFP>;
|
|
|
|
|
|
|
|
|
|
// cvt int-to-fp staff
|
2016-09-23 14:24:39 +08:00
|
|
|
def X86cvtp2Int : SDNode<"X86ISD::CVTP2SI", SDTFloatToInt>;
|
|
|
|
|
def X86cvtp2UInt : SDNode<"X86ISD::CVTP2UI", SDTFloatToInt>;
|
2015-07-13 21:26:20 +08:00
|
|
|
|
2017-11-07 15:13:03 +08:00
|
|
|
|
2019-01-20 05:26:20 +08:00
|
|
|
// Masked versions of above
|
|
|
|
|
def SDTMVintToFP: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
|
|
|
|
|
SDTCisFP<0>, SDTCisInt<1>,
|
|
|
|
|
SDTCisSameSizeAs<0, 1>,
|
|
|
|
|
SDTCisSameAs<0, 2>,
|
|
|
|
|
SDTCVecEltisVT<3, i1>,
|
|
|
|
|
SDTCisSameNumEltsAs<1, 3>]>;
|
2019-01-13 10:59:59 +08:00
|
|
|
def SDTMFloatToInt: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
|
|
|
|
|
SDTCisInt<0>, SDTCisFP<1>,
|
|
|
|
|
SDTCisSameSizeAs<0, 1>,
|
|
|
|
|
SDTCisSameAs<0, 2>,
|
|
|
|
|
SDTCVecEltisVT<3, i1>,
|
|
|
|
|
SDTCisSameNumEltsAs<1, 3>]>;
|
|
|
|
|
|
2019-01-20 05:26:20 +08:00
|
|
|
def X86VMSintToFP : SDNode<"X86ISD::MCVTSI2P", SDTMVintToFP>;
|
|
|
|
|
def X86VMUintToFP : SDNode<"X86ISD::MCVTUI2P", SDTMVintToFP>;
|
|
|
|
|
|
2019-01-13 10:59:59 +08:00
|
|
|
def X86mcvtp2Int : SDNode<"X86ISD::MCVTP2SI", SDTMFloatToInt>;
|
|
|
|
|
def X86mcvtp2UInt : SDNode<"X86ISD::MCVTP2UI", SDTMFloatToInt>;
|
|
|
|
|
def X86mcvttp2si : SDNode<"X86ISD::MCVTTP2SI", SDTMFloatToInt>;
|
|
|
|
|
def X86mcvttp2ui : SDNode<"X86ISD::MCVTTP2UI", SDTMFloatToInt>;
|
|
|
|
|
|
|
|
|
|
|
2016-09-21 10:05:22 +08:00
|
|
|
def X86cvtph2ps : SDNode<"X86ISD::CVTPH2PS",
|
2017-11-07 15:13:03 +08:00
|
|
|
SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>,
|
|
|
|
|
SDTCVecEltisVT<1, i16>]> >;
|
|
|
|
|
|
2019-03-11 12:36:53 +08:00
|
|
|
def X86cvtph2psSAE : SDNode<"X86ISD::CVTPH2PS_SAE",
|
|
|
|
|
SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>,
|
|
|
|
|
SDTCVecEltisVT<1, i16>]> >;
|
2015-10-22 22:01:16 +08:00
|
|
|
|
2016-09-21 10:05:22 +08:00
|
|
|
def X86cvtps2ph : SDNode<"X86ISD::CVTPS2PH",
|
2016-09-21 11:58:44 +08:00
|
|
|
SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>,
|
2015-10-27 23:37:17 +08:00
|
|
|
SDTCVecEltisVT<1, f32>,
|
2016-09-21 11:58:44 +08:00
|
|
|
SDTCisVT<2, i32>]> >;
|
2019-01-12 16:05:12 +08:00
|
|
|
def X86mcvtps2ph : SDNode<"X86ISD::MCVTPS2PH",
|
|
|
|
|
SDTypeProfile<1, 4, [SDTCVecEltisVT<0, i16>,
|
|
|
|
|
SDTCVecEltisVT<1, f32>,
|
|
|
|
|
SDTCisVT<2, i32>,
|
|
|
|
|
SDTCisSameAs<0, 3>,
|
|
|
|
|
SDTCVecEltisVT<4, i1>,
|
|
|
|
|
SDTCisSameNumEltsAs<1, 4>]> >;
|
2019-03-11 12:36:51 +08:00
|
|
|
def X86vfpextSAE : SDNode<"X86ISD::VFPEXT_SAE",
|
|
|
|
|
SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f64>,
|
2015-11-27 02:31:19 +08:00
|
|
|
SDTCVecEltisVT<1, f32>,
|
2019-03-11 12:36:51 +08:00
|
|
|
SDTCisOpSmallerThanOp<1, 0>]>>;
|
2016-09-23 14:24:43 +08:00
|
|
|
def X86vfproundRnd: SDNode<"X86ISD::VFPROUND_RND",
|
2016-05-19 14:13:48 +08:00
|
|
|
SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>,
|
2015-07-13 21:26:20 +08:00
|
|
|
SDTCVecEltisVT<1, f64>,
|
2015-11-27 02:31:19 +08:00
|
|
|
SDTCisOpSmallerThanOp<0, 1>,
|
|
|
|
|
SDTCisVT<2, i32>]>>;
|
2015-06-14 20:44:55 +08:00
|
|
|
|
Enable AVX512_BF16 instructions, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
VCVTNE2PS2BF16: Convert Two Packed Single Data to One Packed BF16 Data.
VCVTNEPS2BF16: Convert Packed Single Data to Packed BF16 Data.
VDPBF16PS: Dot Product of BF16 Pairs Accumulated into Packed Single Precision.
For more details about BF16 isa, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
Author: LiuTianle
Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, RKSimon, spatel
Reviewed By: craig.topper
Subscribers: kristina, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60550
llvm-svn: 360017
2019-05-06 16:22:37 +08:00
|
|
|
// cvt fp to bfloat16
|
|
|
|
|
def X86cvtne2ps2bf16 : SDNode<"X86ISD::CVTNE2PS2BF16",
|
|
|
|
|
SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
|
|
|
|
|
SDTCisSameAs<1,2>]>>;
|
|
|
|
|
def X86mcvtneps2bf16 : SDNode<"X86ISD::MCVTNEPS2BF16",
|
|
|
|
|
SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i16>,
|
|
|
|
|
SDTCVecEltisVT<1, f32>,
|
|
|
|
|
SDTCisSameAs<0, 2>,
|
|
|
|
|
SDTCVecEltisVT<3, i1>,
|
|
|
|
|
SDTCisSameNumEltsAs<1, 3>]>>;
|
|
|
|
|
def X86cvtneps2bf16 : SDNode<"X86ISD::CVTNEPS2BF16",
|
|
|
|
|
SDTypeProfile<1, 1, [SDTCVecEltisVT<0, i16>,
|
|
|
|
|
SDTCVecEltisVT<1, f32>]>>;
|
|
|
|
|
def X86dpbf16ps : SDNode<"X86ISD::DPBF16PS",
|
|
|
|
|
SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>,
|
|
|
|
|
SDTCisSameAs<0,1>,
|
|
|
|
|
SDTCVecEltisVT<2, i32>,
|
|
|
|
|
SDTCisSameAs<2,3>]>>;
|
|
|
|
|
|
2017-11-26 17:36:41 +08:00
|
|
|
// galois field arithmetic
|
|
|
|
|
def X86GF2P8affineinvqb : SDNode<"X86ISD::GF2P8AFFINEINVQB", SDTBlend>;
|
|
|
|
|
def X86GF2P8affineqb : SDNode<"X86ISD::GF2P8AFFINEQB", SDTBlend>;
|
|
|
|
|
def X86GF2P8mulb : SDNode<"X86ISD::GF2P8MULB", SDTIntBinOp>;
|
|
|
|
|
|
2019-11-21 22:56:37 +08:00
|
|
|
def SDTX86MaskedStore: SDTypeProfile<0, 3, [ // masked store
|
|
|
|
|
SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisVec<2>, SDTCisSameNumEltsAs<0, 2>
|
|
|
|
|
]>;
|
|
|
|
|
|
2010-07-13 07:41:28 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// SSE Complex Patterns
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
|
|
// These are 'extloads' from a scalar to the low element of a vector, zeroing
|
|
|
|
|
// the top elements. These are used for the SSE 'ss' and 'sd' instruction
|
|
|
|
|
// forms.
|
2015-10-14 00:23:00 +08:00
|
|
|
def sse_load_f32 : ComplexPattern<v4f32, 5, "selectScalarSSELoad", [],
|
2010-09-22 04:31:19 +08:00
|
|
|
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
|
2018-06-18 00:29:46 +08:00
|
|
|
SDNPWantRoot, SDNPWantParent]>;
|
2015-10-14 00:23:00 +08:00
|
|
|
def sse_load_f64 : ComplexPattern<v2f64, 5, "selectScalarSSELoad", [],
|
2010-09-22 04:31:19 +08:00
|
|
|
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
|
2018-06-18 00:29:46 +08:00
|
|
|
SDNPWantRoot, SDNPWantParent]>;
|
2010-07-13 07:41:28 +08:00
|
|
|
|
2019-04-09 08:24:17 +08:00
|
|
|
def ssmem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand>;
|
|
|
|
|
def sdmem : X86MemOperand<"printqwordmem", X86Mem64AsmOperand>;
|
2010-07-13 07:41:28 +08:00
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// SSE pattern fragments
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
2010-08-14 04:39:01 +08:00
|
|
|
// 128-bit load pattern fragments
|
2018-10-11 05:48:34 +08:00
|
|
|
def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
|
|
|
|
|
def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
|
|
|
|
|
def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
|
2018-10-23 06:14:05 +08:00
|
|
|
def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
|
|
|
|
|
def loadv8i16 : PatFrag<(ops node:$ptr), (v8i16 (load node:$ptr))>;
|
|
|
|
|
def loadv16i8 : PatFrag<(ops node:$ptr), (v16i8 (load node:$ptr))>;
|
2010-07-13 07:41:28 +08:00
|
|
|
|
2010-08-14 04:39:01 +08:00
|
|
|
// 256-bit load pattern fragments
|
2018-10-23 06:14:05 +08:00
|
|
|
def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
|
|
|
|
|
def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
|
|
|
|
|
def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
|
|
|
|
|
def loadv8i32 : PatFrag<(ops node:$ptr), (v8i32 (load node:$ptr))>;
|
|
|
|
|
def loadv16i16 : PatFrag<(ops node:$ptr), (v16i16 (load node:$ptr))>;
|
|
|
|
|
def loadv32i8 : PatFrag<(ops node:$ptr), (v32i8 (load node:$ptr))>;
|
2010-07-13 07:41:28 +08:00
|
|
|
|
2013-08-11 15:55:09 +08:00
|
|
|
// 512-bit load pattern fragments
|
2018-10-11 05:48:34 +08:00
|
|
|
def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
|
2018-10-23 06:14:05 +08:00
|
|
|
def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
|
|
|
|
|
def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
|
|
|
|
|
def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
|
|
|
|
|
def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
|
|
|
|
|
def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
|
2013-08-11 15:55:09 +08:00
|
|
|
|
|
|
|
|
// 128-/256-/512-bit extload pattern fragments
|
2019-05-31 07:35:24 +08:00
|
|
|
def extloadv2f32 : PatFrag<(ops node:$ptr), (extloadvf32 node:$ptr)>;
|
|
|
|
|
def extloadv4f32 : PatFrag<(ops node:$ptr), (extloadvf32 node:$ptr)>;
|
|
|
|
|
def extloadv8f32 : PatFrag<(ops node:$ptr), (extloadvf32 node:$ptr)>;
|
2012-09-11 02:33:51 +08:00
|
|
|
|
2017-08-20 07:21:21 +08:00
|
|
|
// Like 'store', but always requires vector size alignment.
|
2010-07-13 07:41:28 +08:00
|
|
|
def alignedstore : PatFrag<(ops node:$val, node:$ptr),
|
|
|
|
|
(store node:$val, node:$ptr), [{
|
2017-08-20 07:21:22 +08:00
|
|
|
auto *St = cast<StoreSDNode>(N);
|
2017-08-20 07:21:21 +08:00
|
|
|
return St->getAlignment() >= St->getMemoryVT().getStoreSize();
|
2013-08-11 15:55:09 +08:00
|
|
|
}]>;
|
|
|
|
|
|
2018-10-11 05:48:34 +08:00
|
|
|
// Like 'load', but always requires vector size alignment.
|
|
|
|
|
def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
|
2017-08-20 07:21:22 +08:00
|
|
|
auto *Ld = cast<LoadSDNode>(N);
|
2018-10-11 05:48:34 +08:00
|
|
|
return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize();
|
2013-08-11 15:55:09 +08:00
|
|
|
}]>;
|
|
|
|
|
|
2010-08-14 04:39:01 +08:00
|
|
|
// 128-bit aligned load pattern fragments
|
2012-01-24 11:03:17 +08:00
|
|
|
// NOTE: all 128-bit integer vector loads are promoted to v2i64
|
2010-07-13 07:41:28 +08:00
|
|
|
def alignedloadv4f32 : PatFrag<(ops node:$ptr),
|
2018-10-11 05:48:34 +08:00
|
|
|
(v4f32 (alignedload node:$ptr))>;
|
2010-07-13 07:41:28 +08:00
|
|
|
def alignedloadv2f64 : PatFrag<(ops node:$ptr),
|
2018-10-11 05:48:34 +08:00
|
|
|
(v2f64 (alignedload node:$ptr))>;
|
2010-07-13 07:41:28 +08:00
|
|
|
def alignedloadv2i64 : PatFrag<(ops node:$ptr),
|
2018-10-11 05:48:34 +08:00
|
|
|
(v2i64 (alignedload node:$ptr))>;
|
2018-10-23 06:14:05 +08:00
|
|
|
def alignedloadv4i32 : PatFrag<(ops node:$ptr),
|
|
|
|
|
(v4i32 (alignedload node:$ptr))>;
|
|
|
|
|
def alignedloadv8i16 : PatFrag<(ops node:$ptr),
|
|
|
|
|
(v8i16 (alignedload node:$ptr))>;
|
|
|
|
|
def alignedloadv16i8 : PatFrag<(ops node:$ptr),
|
|
|
|
|
(v16i8 (alignedload node:$ptr))>;
|
2010-07-13 07:41:28 +08:00
|
|
|
|
2010-08-14 04:39:01 +08:00
|
|
|
// 256-bit aligned load pattern fragments
|
2012-01-24 11:03:17 +08:00
|
|
|
// NOTE: all 256-bit integer vector loads are promoted to v4i64
|
2018-10-23 06:14:05 +08:00
|
|
|
def alignedloadv8f32 : PatFrag<(ops node:$ptr),
|
|
|
|
|
(v8f32 (alignedload node:$ptr))>;
|
|
|
|
|
def alignedloadv4f64 : PatFrag<(ops node:$ptr),
|
|
|
|
|
(v4f64 (alignedload node:$ptr))>;
|
|
|
|
|
def alignedloadv4i64 : PatFrag<(ops node:$ptr),
|
|
|
|
|
(v4i64 (alignedload node:$ptr))>;
|
|
|
|
|
def alignedloadv8i32 : PatFrag<(ops node:$ptr),
|
|
|
|
|
(v8i32 (alignedload node:$ptr))>;
|
|
|
|
|
def alignedloadv16i16 : PatFrag<(ops node:$ptr),
|
|
|
|
|
(v16i16 (alignedload node:$ptr))>;
|
|
|
|
|
def alignedloadv32i8 : PatFrag<(ops node:$ptr),
|
|
|
|
|
(v32i8 (alignedload node:$ptr))>;
|
2010-07-13 07:41:28 +08:00
|
|
|
|
2013-08-11 15:55:09 +08:00
|
|
|
// 512-bit aligned load pattern fragments
|
|
|
|
|
def alignedloadv16f32 : PatFrag<(ops node:$ptr),
|
2018-10-11 05:48:34 +08:00
|
|
|
(v16f32 (alignedload node:$ptr))>;
|
2013-08-11 15:55:09 +08:00
|
|
|
def alignedloadv8f64 : PatFrag<(ops node:$ptr),
|
2018-10-11 05:48:34 +08:00
|
|
|
(v8f64 (alignedload node:$ptr))>;
|
2013-08-11 15:55:09 +08:00
|
|
|
def alignedloadv8i64 : PatFrag<(ops node:$ptr),
|
2018-10-11 05:48:34 +08:00
|
|
|
(v8i64 (alignedload node:$ptr))>;
|
2018-10-23 06:14:05 +08:00
|
|
|
def alignedloadv16i32 : PatFrag<(ops node:$ptr),
|
|
|
|
|
(v16i32 (alignedload node:$ptr))>;
|
|
|
|
|
def alignedloadv32i16 : PatFrag<(ops node:$ptr),
|
|
|
|
|
(v32i16 (alignedload node:$ptr))>;
|
|
|
|
|
def alignedloadv64i8 : PatFrag<(ops node:$ptr),
|
|
|
|
|
(v64i8 (alignedload node:$ptr))>;
|
2013-08-11 15:55:09 +08:00
|
|
|
|
2018-10-11 05:48:34 +08:00
|
|
|
// Like 'load', but uses special alignment checks suitable for use in
|
2010-07-13 07:41:28 +08:00
|
|
|
// memory operands in most SSE instructions, which are required to
|
|
|
|
|
// be naturally aligned on some targets but not on others. If the subtarget
|
|
|
|
|
// allows unaligned accesses, match any load, though this may require
|
|
|
|
|
// setting a feature bit in the processor (on startup, for example).
|
|
|
|
|
// Opteron 10h and later implement such a feature.
|
2018-10-11 05:48:34 +08:00
|
|
|
def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
|
2017-08-20 07:21:22 +08:00
|
|
|
auto *Ld = cast<LoadSDNode>(N);
|
2017-06-12 18:01:27 +08:00
|
|
|
return Subtarget->hasSSEUnalignedMem() ||
|
2017-08-20 07:21:22 +08:00
|
|
|
Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize();
|
2010-07-13 07:41:28 +08:00
|
|
|
}]>;
|
|
|
|
|
|
2010-08-14 04:39:01 +08:00
|
|
|
// 128-bit memop pattern fragments
|
2012-01-24 11:03:17 +08:00
|
|
|
// NOTE: all 128-bit integer vector loads are promoted to v2i64
|
2010-07-13 07:41:28 +08:00
|
|
|
def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
|
|
|
|
|
def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
|
|
|
|
|
def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
|
2018-10-23 06:14:05 +08:00
|
|
|
def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
|
|
|
|
|
def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop node:$ptr))>;
|
|
|
|
|
def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
|
2010-07-13 07:41:28 +08:00
|
|
|
|
2017-11-22 15:11:03 +08:00
|
|
|
def X86masked_gather : SDNode<"X86ISD::MGATHER",
|
|
|
|
|
SDTypeProfile<2, 3, [SDTCisVec<0>,
|
|
|
|
|
SDTCisVec<1>, SDTCisInt<1>,
|
|
|
|
|
SDTCisSameAs<0, 2>,
|
|
|
|
|
SDTCisSameAs<1, 3>,
|
|
|
|
|
SDTCisPtrTy<4>]>,
|
2017-11-15 15:46:43 +08:00
|
|
|
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
|
2017-06-22 14:47:41 +08:00
|
|
|
|
2017-11-22 16:10:54 +08:00
|
|
|
def X86masked_scatter : SDNode<"X86ISD::MSCATTER",
|
|
|
|
|
SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
|
|
|
|
|
SDTCisSameAs<0, 2>,
|
|
|
|
|
SDTCVecEltisVT<0, i1>,
|
|
|
|
|
SDTCisPtrTy<3>]>,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
|
|
|
|
|
2015-06-28 18:53:29 +08:00
|
|
|
def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
2017-11-22 15:11:03 +08:00
|
|
|
(X86masked_gather node:$src1, node:$src2, node:$src3) , [{
|
|
|
|
|
X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N);
|
2017-11-19 03:05:12 +08:00
|
|
|
return Mgt->getIndex().getValueType() == MVT::v4i32;
|
2015-06-28 18:53:29 +08:00
|
|
|
}]>;
|
|
|
|
|
|
2015-04-30 16:38:48 +08:00
|
|
|
def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
2017-11-22 15:11:03 +08:00
|
|
|
(X86masked_gather node:$src1, node:$src2, node:$src3) , [{
|
|
|
|
|
X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N);
|
2017-11-19 03:05:12 +08:00
|
|
|
return Mgt->getIndex().getValueType() == MVT::v8i32;
|
2015-04-30 16:38:48 +08:00
|
|
|
}]>;
|
|
|
|
|
|
2015-06-28 18:53:29 +08:00
|
|
|
def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
2017-11-22 15:11:03 +08:00
|
|
|
(X86masked_gather node:$src1, node:$src2, node:$src3) , [{
|
2017-11-19 03:05:12 +08:00
|
|
|
X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N);
|
2017-11-22 15:11:03 +08:00
|
|
|
return Mgt->getIndex().getValueType() == MVT::v2i64;
|
2015-06-28 18:53:29 +08:00
|
|
|
}]>;
|
|
|
|
|
def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
2017-11-22 15:11:03 +08:00
|
|
|
(X86masked_gather node:$src1, node:$src2, node:$src3) , [{
|
|
|
|
|
X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N);
|
2017-11-19 03:05:12 +08:00
|
|
|
return Mgt->getIndex().getValueType() == MVT::v4i64;
|
2015-06-28 18:53:29 +08:00
|
|
|
}]>;
|
2015-04-30 16:38:48 +08:00
|
|
|
def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
2017-11-22 15:11:03 +08:00
|
|
|
(X86masked_gather node:$src1, node:$src2, node:$src3) , [{
|
|
|
|
|
X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N);
|
2017-11-19 03:05:12 +08:00
|
|
|
return Mgt->getIndex().getValueType() == MVT::v8i64;
|
2015-04-30 16:38:48 +08:00
|
|
|
}]>;
|
|
|
|
|
def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
2017-11-22 15:11:03 +08:00
|
|
|
(X86masked_gather node:$src1, node:$src2, node:$src3) , [{
|
|
|
|
|
X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N);
|
2017-11-19 03:05:12 +08:00
|
|
|
return Mgt->getIndex().getValueType() == MVT::v16i32;
|
2015-04-30 16:38:48 +08:00
|
|
|
}]>;
|
|
|
|
|
|
2015-06-29 20:14:24 +08:00
|
|
|
def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
2017-11-22 16:10:54 +08:00
|
|
|
(X86masked_scatter node:$src1, node:$src2, node:$src3) , [{
|
|
|
|
|
X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N);
|
2017-11-19 03:05:12 +08:00
|
|
|
return Sc->getIndex().getValueType() == MVT::v2i64;
|
2015-06-29 20:14:24 +08:00
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
2017-11-22 16:10:54 +08:00
|
|
|
(X86masked_scatter node:$src1, node:$src2, node:$src3) , [{
|
|
|
|
|
X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N);
|
2017-11-19 03:05:12 +08:00
|
|
|
return Sc->getIndex().getValueType() == MVT::v4i32;
|
2015-06-29 20:14:24 +08:00
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
2017-11-22 16:10:54 +08:00
|
|
|
(X86masked_scatter node:$src1, node:$src2, node:$src3) , [{
|
|
|
|
|
X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N);
|
2017-11-19 03:05:12 +08:00
|
|
|
return Sc->getIndex().getValueType() == MVT::v4i64;
|
2015-06-29 20:14:24 +08:00
|
|
|
}]>;
|
|
|
|
|
|
2015-04-30 16:38:48 +08:00
|
|
|
def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
2017-11-22 16:10:54 +08:00
|
|
|
(X86masked_scatter node:$src1, node:$src2, node:$src3) , [{
|
|
|
|
|
X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N);
|
2017-11-19 03:05:12 +08:00
|
|
|
return Sc->getIndex().getValueType() == MVT::v8i32;
|
2015-04-30 16:38:48 +08:00
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
2017-11-22 16:10:54 +08:00
|
|
|
(X86masked_scatter node:$src1, node:$src2, node:$src3) , [{
|
|
|
|
|
X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N);
|
2017-11-19 03:05:12 +08:00
|
|
|
return Sc->getIndex().getValueType() == MVT::v8i64;
|
2015-04-30 16:38:48 +08:00
|
|
|
}]>;
|
|
|
|
|
def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
2017-11-22 16:10:54 +08:00
|
|
|
(X86masked_scatter node:$src1, node:$src2, node:$src3) , [{
|
|
|
|
|
X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N);
|
2017-11-19 03:05:12 +08:00
|
|
|
return Sc->getIndex().getValueType() == MVT::v16i32;
|
2015-04-30 16:38:48 +08:00
|
|
|
}]>;
|
|
|
|
|
|
2010-08-14 04:39:01 +08:00
|
|
|
// 128-bit bitconvert pattern fragments
|
2010-07-13 07:41:28 +08:00
|
|
|
def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
|
|
|
|
|
def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
|
|
|
|
|
def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
|
|
|
|
|
def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
|
|
|
|
|
def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
|
|
|
|
|
def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
|
|
|
|
|
|
2010-08-14 04:39:01 +08:00
|
|
|
// 256-bit bitconvert pattern fragments
|
2011-11-02 12:42:13 +08:00
|
|
|
def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
|
|
|
|
|
def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
|
2010-07-22 07:53:50 +08:00
|
|
|
def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
|
2011-07-13 09:15:33 +08:00
|
|
|
def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
|
2014-01-06 16:45:54 +08:00
|
|
|
def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
|
2018-02-05 16:37:37 +08:00
|
|
|
def bc_v4f64 : PatFrag<(ops node:$in), (v4f64 (bitconvert node:$in))>;
|
2010-07-22 07:53:50 +08:00
|
|
|
|
2013-08-16 14:07:34 +08:00
|
|
|
// 512-bit bitconvert pattern fragments
|
2016-08-29 06:20:51 +08:00
|
|
|
def bc_v64i8 : PatFrag<(ops node:$in), (v64i8 (bitconvert node:$in))>;
|
2018-10-27 01:21:26 +08:00
|
|
|
def bc_v32i16 : PatFrag<(ops node:$in), (v32i16 (bitconvert node:$in))>;
|
2013-08-16 14:07:34 +08:00
|
|
|
def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
|
|
|
|
|
def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
|
2014-01-01 23:12:34 +08:00
|
|
|
def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
|
|
|
|
|
def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
|
2013-08-16 14:07:34 +08:00
|
|
|
|
2019-07-15 10:02:31 +08:00
|
|
|
def X86vzload32 : PatFrag<(ops node:$src),
|
|
|
|
|
(X86vzld node:$src), [{
|
|
|
|
|
return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 4;
|
|
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def X86vzload64 : PatFrag<(ops node:$src),
|
|
|
|
|
(X86vzld node:$src), [{
|
|
|
|
|
return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 8;
|
|
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def X86vextractstore64 : PatFrag<(ops node:$val, node:$ptr),
|
|
|
|
|
(X86vextractst node:$val, node:$ptr), [{
|
|
|
|
|
return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 8;
|
|
|
|
|
}]>;
|
2010-07-13 07:41:28 +08:00
|
|
|
|
2019-10-02 00:28:20 +08:00
|
|
|
def X86VBroadcastld8 : PatFrag<(ops node:$src),
|
|
|
|
|
(X86VBroadcastld node:$src), [{
|
|
|
|
|
return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 1;
|
|
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def X86VBroadcastld16 : PatFrag<(ops node:$src),
|
|
|
|
|
(X86VBroadcastld node:$src), [{
|
|
|
|
|
return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 2;
|
|
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def X86VBroadcastld32 : PatFrag<(ops node:$src),
|
|
|
|
|
(X86VBroadcastld node:$src), [{
|
|
|
|
|
return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 4;
|
|
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def X86VBroadcastld64 : PatFrag<(ops node:$src),
|
|
|
|
|
(X86VBroadcastld node:$src), [{
|
|
|
|
|
return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 8;
|
|
|
|
|
}]>;
|
|
|
|
|
|
2010-07-13 07:41:28 +08:00
|
|
|
|
|
|
|
|
def fp32imm0 : PatLeaf<(f32 fpimm), [{
|
|
|
|
|
return N->isExactlyValue(+0.0);
|
|
|
|
|
}]>;
|
|
|
|
|
|
2016-11-13 22:29:32 +08:00
|
|
|
def fp64imm0 : PatLeaf<(f64 fpimm), [{
|
|
|
|
|
return N->isExactlyValue(+0.0);
|
|
|
|
|
}]>;
|
|
|
|
|
|
2019-09-09 09:35:00 +08:00
|
|
|
def fp128imm0 : PatLeaf<(f128 fpimm), [{
|
|
|
|
|
return N->isExactlyValue(+0.0);
|
|
|
|
|
}]>;
|
|
|
|
|
|
2013-07-31 19:35:14 +08:00
|
|
|
// EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
|
|
|
|
|
// to VEXTRACTF128/VEXTRACTI128 imm.
|
|
|
|
|
def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
|
2017-09-23 13:34:07 +08:00
|
|
|
return getExtractVEXTRACTImmediate(N, 128, SDLoc(N));
|
2011-02-03 23:50:00 +08:00
|
|
|
}]>;
|
|
|
|
|
|
2013-07-31 19:35:14 +08:00
|
|
|
// INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
|
|
|
|
|
// VINSERTF128/VINSERTI128 imm.
|
|
|
|
|
def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
|
2017-09-23 13:34:07 +08:00
|
|
|
return getInsertVINSERTImmediate(N, 128, SDLoc(N));
|
2011-02-05 00:08:29 +08:00
|
|
|
}]>;
|
|
|
|
|
|
2013-07-31 19:35:14 +08:00
|
|
|
// EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
|
|
|
|
|
// to VEXTRACTF64x4 imm.
|
|
|
|
|
def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
|
2017-09-23 13:34:07 +08:00
|
|
|
return getExtractVEXTRACTImmediate(N, 256, SDLoc(N));
|
2013-07-31 19:35:14 +08:00
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
// INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
|
|
|
|
|
// VINSERTF64x4 imm.
|
|
|
|
|
def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
|
2017-09-23 13:34:07 +08:00
|
|
|
return getInsertVINSERTImmediate(N, 256, SDLoc(N));
|
2013-07-31 19:35:14 +08:00
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
|
|
|
|
|
(extract_subvector node:$bigvec,
|
2019-05-23 05:00:18 +08:00
|
|
|
node:$index), [{
|
|
|
|
|
// Index 0 can be handled via extract_subreg.
|
|
|
|
|
return !isNullConstant(N->getOperand(1));
|
|
|
|
|
}], EXTRACT_get_vextract128_imm>;
|
2013-07-31 19:35:14 +08:00
|
|
|
|
|
|
|
|
def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
|
|
|
|
|
node:$index),
|
|
|
|
|
(insert_subvector node:$bigvec, node:$smallvec,
|
2017-09-23 13:34:06 +08:00
|
|
|
node:$index), [{}],
|
|
|
|
|
INSERT_get_vinsert128_imm>;
|
2013-07-31 19:35:14 +08:00
|
|
|
|
|
|
|
|
def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
|
2011-02-03 23:50:00 +08:00
|
|
|
(extract_subvector node:$bigvec,
|
2019-05-23 05:00:18 +08:00
|
|
|
node:$index), [{
|
|
|
|
|
// Index 0 can be handled via extract_subreg.
|
|
|
|
|
return !isNullConstant(N->getOperand(1));
|
|
|
|
|
}], EXTRACT_get_vextract256_imm>;
|
2011-02-05 00:08:29 +08:00
|
|
|
|
2013-07-31 19:35:14 +08:00
|
|
|
def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
|
2011-02-05 00:08:29 +08:00
|
|
|
node:$index),
|
|
|
|
|
(insert_subvector node:$bigvec, node:$smallvec,
|
2017-09-23 13:34:06 +08:00
|
|
|
node:$index), [{}],
|
|
|
|
|
INSERT_get_vinsert256_imm>;
|
2011-07-26 07:05:25 +08:00
|
|
|
|
2019-06-23 14:06:04 +08:00
|
|
|
def masked_load : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
2019-11-21 22:56:37 +08:00
|
|
|
(masked_ld node:$src1, undef, node:$src2, node:$src3), [{
|
2016-10-09 18:48:52 +08:00
|
|
|
return !cast<MaskedLoadSDNode>(N)->isExpandingLoad() &&
|
2019-11-21 22:56:37 +08:00
|
|
|
cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD &&
|
|
|
|
|
cast<MaskedLoadSDNode>(N)->isUnindexed();
|
2016-10-09 18:48:52 +08:00
|
|
|
}]>;
|
|
|
|
|
|
2019-06-23 14:06:04 +08:00
|
|
|
def masked_load_aligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
2015-03-03 23:03:35 +08:00
|
|
|
(masked_load node:$src1, node:$src2, node:$src3), [{
|
2019-06-23 14:06:04 +08:00
|
|
|
// Use the node type to determine the size the alignment needs to match.
|
|
|
|
|
// We can't use memory VT because type widening changes the node VT, but
|
|
|
|
|
// not the memory VT.
|
|
|
|
|
auto *Ld = cast<MaskedLoadSDNode>(N);
|
|
|
|
|
return Ld->getAlignment() >= Ld->getValueType(0).getStoreSize();
|
2016-10-09 18:48:52 +08:00
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def X86mExpandingLoad : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
2019-11-21 22:56:37 +08:00
|
|
|
(masked_ld node:$src1, undef, node:$src2, node:$src3), [{
|
|
|
|
|
return cast<MaskedLoadSDNode>(N)->isExpandingLoad() &&
|
|
|
|
|
cast<MaskedLoadSDNode>(N)->isUnindexed();
|
2015-03-03 23:03:35 +08:00
|
|
|
}]>;
|
|
|
|
|
|
2016-02-02 07:53:35 +08:00
|
|
|
// Masked store fragments.
|
2015-07-25 01:24:15 +08:00
|
|
|
// X86mstore can't be implemented in core DAG files because some targets
|
2016-02-02 07:53:35 +08:00
|
|
|
// do not support vector types (llvm-tblgen will fail).
|
2019-06-23 14:06:04 +08:00
|
|
|
def masked_store : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
2019-11-21 22:56:37 +08:00
|
|
|
(masked_st node:$src1, node:$src2, undef, node:$src3), [{
|
|
|
|
|
return !cast<MaskedStoreSDNode>(N)->isTruncatingStore() &&
|
|
|
|
|
!cast<MaskedStoreSDNode>(N)->isCompressingStore() &&
|
|
|
|
|
cast<MaskedStoreSDNode>(N)->isUnindexed();
|
2015-07-25 01:24:15 +08:00
|
|
|
}]>;
|
|
|
|
|
|
2019-06-23 14:06:04 +08:00
|
|
|
def masked_store_aligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
2016-11-03 11:23:55 +08:00
|
|
|
(masked_store node:$src1, node:$src2, node:$src3), [{
|
2019-06-23 14:06:04 +08:00
|
|
|
// Use the node type to determine the size the alignment needs to match.
|
|
|
|
|
// We can't use memory VT because type widening changes the node VT, but
|
|
|
|
|
// not the memory VT.
|
|
|
|
|
auto *St = cast<MaskedStoreSDNode>(N);
|
|
|
|
|
return St->getAlignment() >= St->getOperand(1).getValueType().getStoreSize();
|
2015-03-03 23:03:35 +08:00
|
|
|
}]>;
|
|
|
|
|
|
2016-09-26 14:22:08 +08:00
|
|
|
def X86mCompressingStore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
2019-11-21 22:56:37 +08:00
|
|
|
(masked_st node:$src1, node:$src2, undef, node:$src3), [{
|
|
|
|
|
return cast<MaskedStoreSDNode>(N)->isCompressingStore() &&
|
|
|
|
|
cast<MaskedStoreSDNode>(N)->isUnindexed();
|
2016-09-26 14:22:08 +08:00
|
|
|
}]>;
|
|
|
|
|
|
2015-07-25 01:24:15 +08:00
|
|
|
// masked truncstore fragments
|
|
|
|
|
// X86mtruncstore can't be implemented in core DAG files because some targets
|
|
|
|
|
// doesn't support vector type ( llvm-tblgen will fail)
|
|
|
|
|
def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
2019-11-21 22:56:37 +08:00
|
|
|
(masked_st node:$src1, node:$src2, undef, node:$src3), [{
|
|
|
|
|
return cast<MaskedStoreSDNode>(N)->isTruncatingStore() &&
|
|
|
|
|
cast<MaskedStoreSDNode>(N)->isUnindexed();
|
2015-07-25 01:24:15 +08:00
|
|
|
}]>;
|
|
|
|
|
def masked_truncstorevi8 :
|
|
|
|
|
PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
|
|
|
|
(X86mtruncstore node:$src1, node:$src2, node:$src3), [{
|
|
|
|
|
return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
|
|
|
|
|
}]>;
|
|
|
|
|
def masked_truncstorevi16 :
|
|
|
|
|
PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
|
|
|
|
(X86mtruncstore node:$src1, node:$src2, node:$src3), [{
|
|
|
|
|
return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
|
|
|
|
|
}]>;
|
|
|
|
|
def masked_truncstorevi32 :
|
|
|
|
|
PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
|
|
|
|
(X86mtruncstore node:$src1, node:$src2, node:$src3), [{
|
|
|
|
|
return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
|
|
|
|
|
}]>;
|
2016-09-13 15:57:00 +08:00
|
|
|
|
2016-12-21 18:43:36 +08:00
|
|
|
def X86TruncSStore : SDNode<"X86ISD::VTRUNCSTORES", SDTStore,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
|
|
|
|
|
|
|
|
|
def X86TruncUSStore : SDNode<"X86ISD::VTRUNCSTOREUS", SDTStore,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
|
|
|
|
|
2019-11-21 22:56:37 +08:00
|
|
|
def X86MTruncSStore : SDNode<"X86ISD::VMTRUNCSTORES", SDTX86MaskedStore,
|
2016-12-21 18:43:36 +08:00
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
|
|
|
|
|
2019-11-21 22:56:37 +08:00
|
|
|
def X86MTruncUSStore : SDNode<"X86ISD::VMTRUNCSTOREUS", SDTX86MaskedStore,
|
2016-12-21 18:43:36 +08:00
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
|
|
|
|
|
|
|
|
|
def truncstore_s_vi8 : PatFrag<(ops node:$val, node:$ptr),
|
|
|
|
|
(X86TruncSStore node:$val, node:$ptr), [{
|
|
|
|
|
return cast<TruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
|
|
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def truncstore_us_vi8 : PatFrag<(ops node:$val, node:$ptr),
|
|
|
|
|
(X86TruncUSStore node:$val, node:$ptr), [{
|
|
|
|
|
return cast<TruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
|
|
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def truncstore_s_vi16 : PatFrag<(ops node:$val, node:$ptr),
|
|
|
|
|
(X86TruncSStore node:$val, node:$ptr), [{
|
|
|
|
|
return cast<TruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
|
|
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def truncstore_us_vi16 : PatFrag<(ops node:$val, node:$ptr),
|
|
|
|
|
(X86TruncUSStore node:$val, node:$ptr), [{
|
|
|
|
|
return cast<TruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
|
|
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def truncstore_s_vi32 : PatFrag<(ops node:$val, node:$ptr),
|
|
|
|
|
(X86TruncSStore node:$val, node:$ptr), [{
|
|
|
|
|
return cast<TruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
|
|
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def truncstore_us_vi32 : PatFrag<(ops node:$val, node:$ptr),
|
|
|
|
|
(X86TruncUSStore node:$val, node:$ptr), [{
|
|
|
|
|
return cast<TruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
|
|
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def masked_truncstore_s_vi8 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
|
|
|
|
(X86MTruncSStore node:$src1, node:$src2, node:$src3), [{
|
|
|
|
|
return cast<MaskedTruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
|
|
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def masked_truncstore_us_vi8 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
|
|
|
|
(X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{
|
|
|
|
|
return cast<MaskedTruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
|
|
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def masked_truncstore_s_vi16 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
|
|
|
|
|
(X86MTruncSStore node:$src1, node:$src2, node:$src3), [{
|
|
|
|
|
return cast<MaskedTruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
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}]>;
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def masked_truncstore_us_vi16 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
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(X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{
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return cast<MaskedTruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
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}]>;
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def masked_truncstore_s_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
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(X86MTruncSStore node:$src1, node:$src2, node:$src3), [{
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|
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return cast<MaskedTruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
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|
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|
}]>;
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|
|
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|
|
def masked_truncstore_us_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
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|
|
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(X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{
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|
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|
return cast<MaskedTruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
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|
|
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|
}]>;
|