2011-03-01 03:06:56 +08:00
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//===-- X86ShuffleDecode.cpp - X86 shuffle decode logic -------------------===//
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2010-09-03 02:40:13 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Define several functions to decode x86 specific shuffle semantics into a
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// generic vector mask.
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//
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//===----------------------------------------------------------------------===//
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2011-02-18 03:18:59 +08:00
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#include "X86ShuffleDecode.h"
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2010-09-03 02:40:13 +08:00
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//===----------------------------------------------------------------------===//
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// Vector Mask Decoding
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//===----------------------------------------------------------------------===//
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2011-02-18 03:18:59 +08:00
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namespace llvm {
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2010-09-03 02:40:13 +08:00
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2010-09-03 06:43:39 +08:00
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void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<unsigned> &ShuffleMask) {
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// Defaults the copying the dest value.
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ShuffleMask.push_back(0);
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ShuffleMask.push_back(1);
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ShuffleMask.push_back(2);
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ShuffleMask.push_back(3);
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// Decode the immediate.
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unsigned ZMask = Imm & 15;
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unsigned CountD = (Imm >> 4) & 3;
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unsigned CountS = (Imm >> 6) & 3;
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// CountS selects which input element to use.
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unsigned InVal = 4+CountS;
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// CountD specifies which element of destination to update.
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ShuffleMask[CountD] = InVal;
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// ZMask zaps values, potentially overriding the CountD elt.
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if (ZMask & 1) ShuffleMask[0] = SM_SentinelZero;
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if (ZMask & 2) ShuffleMask[1] = SM_SentinelZero;
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if (ZMask & 4) ShuffleMask[2] = SM_SentinelZero;
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if (ZMask & 8) ShuffleMask[3] = SM_SentinelZero;
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}
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2010-09-03 05:51:11 +08:00
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// <3,1> or <6,7,2,3>
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2011-02-18 03:18:59 +08:00
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void DecodeMOVHLPSMask(unsigned NElts,
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SmallVectorImpl<unsigned> &ShuffleMask) {
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2010-09-03 05:51:11 +08:00
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for (unsigned i = NElts/2; i != NElts; ++i)
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ShuffleMask.push_back(NElts+i);
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2010-09-03 02:40:13 +08:00
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2010-09-03 05:51:11 +08:00
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for (unsigned i = NElts/2; i != NElts; ++i)
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ShuffleMask.push_back(i);
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2010-09-03 02:40:13 +08:00
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}
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2010-09-03 05:51:11 +08:00
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// <0,2> or <0,1,4,5>
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2011-02-18 03:18:59 +08:00
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void DecodeMOVLHPSMask(unsigned NElts,
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SmallVectorImpl<unsigned> &ShuffleMask) {
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2010-09-03 05:51:11 +08:00
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for (unsigned i = 0; i != NElts/2; ++i)
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ShuffleMask.push_back(i);
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2010-09-03 02:40:13 +08:00
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2010-09-03 05:51:11 +08:00
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for (unsigned i = 0; i != NElts/2; ++i)
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ShuffleMask.push_back(NElts+i);
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2010-09-03 02:40:13 +08:00
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}
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2011-02-18 03:18:59 +08:00
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void DecodePSHUFMask(unsigned NElts, unsigned Imm,
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SmallVectorImpl<unsigned> &ShuffleMask) {
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2010-09-03 02:40:13 +08:00
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for (unsigned i = 0; i != NElts; ++i) {
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ShuffleMask.push_back(Imm % NElts);
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Imm /= NElts;
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}
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}
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2011-02-18 03:18:59 +08:00
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void DecodePSHUFHWMask(unsigned Imm,
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SmallVectorImpl<unsigned> &ShuffleMask) {
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2010-09-03 02:40:13 +08:00
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ShuffleMask.push_back(0);
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ShuffleMask.push_back(1);
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ShuffleMask.push_back(2);
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ShuffleMask.push_back(3);
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for (unsigned i = 0; i != 4; ++i) {
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ShuffleMask.push_back(4+(Imm & 3));
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Imm >>= 2;
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}
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}
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2011-02-18 03:18:59 +08:00
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void DecodePSHUFLWMask(unsigned Imm,
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SmallVectorImpl<unsigned> &ShuffleMask) {
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2010-09-03 02:40:13 +08:00
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for (unsigned i = 0; i != 4; ++i) {
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ShuffleMask.push_back((Imm & 3));
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Imm >>= 2;
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}
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ShuffleMask.push_back(4);
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ShuffleMask.push_back(5);
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ShuffleMask.push_back(6);
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ShuffleMask.push_back(7);
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}
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2011-03-01 03:06:56 +08:00
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void DecodePUNPCKLBWMask(unsigned NElts,
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SmallVectorImpl<unsigned> &ShuffleMask) {
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DecodeUNPCKLPMask(MVT::getVectorVT(MVT::i8, NElts), ShuffleMask);
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}
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void DecodePUNPCKLWDMask(unsigned NElts,
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SmallVectorImpl<unsigned> &ShuffleMask) {
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DecodeUNPCKLPMask(MVT::getVectorVT(MVT::i16, NElts), ShuffleMask);
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}
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void DecodePUNPCKLDQMask(unsigned NElts,
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SmallVectorImpl<unsigned> &ShuffleMask) {
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DecodeUNPCKLPMask(MVT::getVectorVT(MVT::i32, NElts), ShuffleMask);
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}
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void DecodePUNPCKLQDQMask(unsigned NElts,
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SmallVectorImpl<unsigned> &ShuffleMask) {
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DecodeUNPCKLPMask(MVT::getVectorVT(MVT::i64, NElts), ShuffleMask);
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}
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void DecodePUNPCKLMask(EVT VT,
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2011-02-18 03:18:59 +08:00
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SmallVectorImpl<unsigned> &ShuffleMask) {
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2011-03-01 03:06:56 +08:00
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DecodeUNPCKLPMask(VT, ShuffleMask);
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2010-09-03 02:40:13 +08:00
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}
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2011-02-18 03:18:59 +08:00
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void DecodePUNPCKHMask(unsigned NElts,
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SmallVectorImpl<unsigned> &ShuffleMask) {
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2010-09-03 02:40:13 +08:00
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for (unsigned i = 0; i != NElts/2; ++i) {
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ShuffleMask.push_back(i+NElts/2);
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ShuffleMask.push_back(i+NElts+NElts/2);
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}
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}
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2011-02-18 03:18:59 +08:00
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void DecodeSHUFPSMask(unsigned NElts, unsigned Imm,
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SmallVectorImpl<unsigned> &ShuffleMask) {
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2010-09-03 02:40:13 +08:00
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// Part that reads from dest.
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for (unsigned i = 0; i != NElts/2; ++i) {
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ShuffleMask.push_back(Imm % NElts);
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Imm /= NElts;
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}
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// Part that reads from src.
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for (unsigned i = 0; i != NElts/2; ++i) {
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ShuffleMask.push_back(Imm % NElts + NElts);
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Imm /= NElts;
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}
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}
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2011-11-22 09:57:35 +08:00
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void DecodeUNPCKHPMask(EVT VT, SmallVectorImpl<unsigned> &ShuffleMask) {
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unsigned NumElts = VT.getVectorNumElements();
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// Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
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// independently on 128-bit lanes.
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unsigned NumLanes = VT.getSizeInBits() / 128;
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if (NumLanes == 0 ) NumLanes = 1; // Handle MMX
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unsigned NumLaneElts = NumElts / NumLanes;
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for (unsigned s = 0; s < NumLanes; ++s) {
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unsigned Start = s * NumLaneElts + NumLaneElts/2;
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unsigned End = s * NumLaneElts + NumLaneElts;
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for (unsigned i = Start; i != End; ++i) {
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ShuffleMask.push_back(i); // Reads from dest/src1
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ShuffleMask.push_back(i+NumElts); // Reads from src/src2
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}
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2010-09-03 02:40:13 +08:00
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}
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}
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/// DecodeUNPCKLPMask - This decodes the shuffle masks for unpcklps/unpcklpd
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2011-03-01 03:06:56 +08:00
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/// etc. VT indicates the type of the vector allowing it to handle different
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/// datatypes and vector widths.
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2011-11-22 09:57:35 +08:00
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void DecodeUNPCKLPMask(EVT VT, SmallVectorImpl<unsigned> &ShuffleMask) {
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2011-03-03 01:23:43 +08:00
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unsigned NumElts = VT.getVectorNumElements();
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2011-07-27 06:03:40 +08:00
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// Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
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// independently on 128-bit lanes.
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unsigned NumLanes = VT.getSizeInBits() / 128;
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if (NumLanes == 0 ) NumLanes = 1; // Handle MMX
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unsigned NumLaneElts = NumElts / NumLanes;
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2011-03-03 01:23:43 +08:00
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2011-07-27 06:03:40 +08:00
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for (unsigned s = 0; s < NumLanes; ++s) {
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2011-11-22 09:57:35 +08:00
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unsigned Start = s * NumLaneElts;
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unsigned End = s * NumLaneElts + NumLaneElts/2;
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2011-03-03 01:23:43 +08:00
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for (unsigned i = Start; i != End; ++i) {
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2011-11-22 09:57:35 +08:00
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ShuffleMask.push_back(i); // Reads from dest/src1
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ShuffleMask.push_back(i+NumElts); // Reads from src/src2
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2011-03-03 01:23:43 +08:00
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}
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2010-09-03 02:40:13 +08:00
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}
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}
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2011-07-29 09:31:11 +08:00
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// DecodeVPERMILPSMask - Decodes VPERMILPS permutes for any 128-bit 32-bit
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// elements. For 256-bit vectors, it's considered as two 128 lanes, the
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// referenced elements can't cross lanes and the mask of the first lane must
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// be the same of the second.
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void DecodeVPERMILPSMask(unsigned NumElts, unsigned Imm,
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SmallVectorImpl<unsigned> &ShuffleMask) {
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unsigned NumLanes = (NumElts*32)/128;
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unsigned LaneSize = NumElts/NumLanes;
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Add support for 256-bit versions of VPERMIL instruction. This is a new
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:
Instead of:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vextractf128 $1, %ymm0, %xmm1
shufps $1, %xmm1, %xmm1
movss %xmm1, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm1, 16(%rsp)
vextractf128 $0, %ymm0, %xmm0
shufps $1, %xmm0, %xmm0
movss %xmm0, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm0, (%rsp)
vmovaps (%rsp), %ymm0
We get:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vpermilps $85, %ymm0, %ymm0
llvm-svn: 135662
2011-07-21 09:55:47 +08:00
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2011-07-29 09:31:11 +08:00
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for (unsigned l = 0; l != NumLanes; ++l) {
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for (unsigned i = 0; i != LaneSize; ++i) {
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unsigned Idx = (Imm >> (i*2)) & 0x3 ;
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ShuffleMask.push_back(Idx+(l*LaneSize));
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}
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}
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Add support for 256-bit versions of VPERMIL instruction. This is a new
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:
Instead of:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vextractf128 $1, %ymm0, %xmm1
shufps $1, %xmm1, %xmm1
movss %xmm1, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm1, 16(%rsp)
vextractf128 $0, %ymm0, %xmm0
shufps $1, %xmm0, %xmm0
movss %xmm0, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm0, (%rsp)
vmovaps (%rsp), %ymm0
We get:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vpermilps $85, %ymm0, %ymm0
llvm-svn: 135662
2011-07-21 09:55:47 +08:00
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}
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2011-07-29 09:31:11 +08:00
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// DecodeVPERMILPDMask - Decodes VPERMILPD permutes for any 128-bit 64-bit
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// elements. For 256-bit vectors, it's considered as two 128 lanes, the
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// referenced elements can't cross lanes but the mask of the first lane can
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// be the different of the second (not like VPERMILPS).
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void DecodeVPERMILPDMask(unsigned NumElts, unsigned Imm,
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SmallVectorImpl<unsigned> &ShuffleMask) {
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unsigned NumLanes = (NumElts*64)/128;
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unsigned LaneSize = NumElts/NumLanes;
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Add support for 256-bit versions of VPERMIL instruction. This is a new
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:
Instead of:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vextractf128 $1, %ymm0, %xmm1
shufps $1, %xmm1, %xmm1
movss %xmm1, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm1, 16(%rsp)
vextractf128 $0, %ymm0, %xmm0
shufps $1, %xmm0, %xmm0
movss %xmm0, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm0, (%rsp)
vmovaps (%rsp), %ymm0
We get:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vpermilps $85, %ymm0, %ymm0
llvm-svn: 135662
2011-07-21 09:55:47 +08:00
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2011-07-29 09:31:11 +08:00
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for (unsigned l = 0; l < NumLanes; ++l) {
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for (unsigned i = l*LaneSize; i < LaneSize*(l+1); ++i) {
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unsigned Idx = (Imm >> i) & 0x1;
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ShuffleMask.push_back(Idx+(l*LaneSize));
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Add support for 256-bit versions of VPERMIL instruction. This is a new
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:
Instead of:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vextractf128 $1, %ymm0, %xmm1
shufps $1, %xmm1, %xmm1
movss %xmm1, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm1, 16(%rsp)
vextractf128 $0, %ymm0, %xmm0
shufps $1, %xmm0, %xmm0
movss %xmm0, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm0, (%rsp)
vmovaps (%rsp), %ymm0
We get:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vpermilps $85, %ymm0, %ymm0
llvm-svn: 135662
2011-07-21 09:55:47 +08:00
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}
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}
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}
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2011-08-13 05:48:26 +08:00
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void DecodeVPERM2F128Mask(EVT VT, unsigned Imm,
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SmallVectorImpl<unsigned> &ShuffleMask) {
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unsigned HalfSize = VT.getVectorNumElements()/2;
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unsigned FstHalfBegin = (Imm & 0x3) * HalfSize;
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unsigned SndHalfBegin = ((Imm >> 4) & 0x3) * HalfSize;
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for (int i = FstHalfBegin, e = FstHalfBegin+HalfSize; i != e; ++i)
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ShuffleMask.push_back(i);
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for (int i = SndHalfBegin, e = SndHalfBegin+HalfSize; i != e; ++i)
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ShuffleMask.push_back(i);
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}
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void DecodeVPERM2F128Mask(unsigned Imm,
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SmallVectorImpl<unsigned> &ShuffleMask) {
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// VPERM2F128 is used by any 256-bit EVT, but X86InstComments only
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// has information about the instruction and not the types. So for
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// instruction comments purpose, assume the 256-bit vector is v4i64.
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return DecodeVPERM2F128Mask(MVT::v4i64, Imm, ShuffleMask);
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}
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2011-02-18 03:18:59 +08:00
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} // llvm namespace
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