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llvm-project/llvm/lib/Target/X86/X86InstrInfo.td

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Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
2012-02-18 20:03:15 +08:00
//===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
Fix Whitespace. llvm-svn: 116972
2010-10-21 07:40:27 +08:00
//
Added LLVM copyright header. llvm-svn: 9321
2003-10-21 23:17:13 +08:00
// The LLVM Compiler Infrastructure
//
Remove attribution from file headers, per discussion on llvmdev. llvm-svn: 45418
2007-12-30 04:36:04 +08:00
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
Fix Whitespace. llvm-svn: 116972
2010-10-21 07:40:27 +08:00
//
Added LLVM copyright header. llvm-svn: 9321
2003-10-21 23:17:13 +08:00
//===----------------------------------------------------------------------===//
Add new TableGen instruction definitions llvm-svn: 7537
2003-08-04 05:54:21 +08:00
//
// This file describes the X86 instruction set, defining the instructions, and
// properties of the instructions which are needed for code generation, machine
// code emission, and analysis.
//
//===----------------------------------------------------------------------===//
Added support for cmp, test, and conditional move instructions. llvm-svn: 24756
2005-12-17 09:24:02 +08:00
//===----------------------------------------------------------------------===//
// X86 specific DAG Nodes.
//
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS. llvm-svn: 25158
2006-01-10 02:33:28 +08:00
def SDTIntShiftDOp: SDTypeProfile<1, 3,
[SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
SDTCisInt<0>, SDTCisInt<3>]>;
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 08:01:11 +08:00
def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
Added support for cmp, test, and conditional move instructions. llvm-svn: 24756
2005-12-17 09:24:02 +08:00
AVX-512: Added legal type MVT::i1 and VK1 register for it. Added scalar compare VCMPSS, VCMPSD. Implemented LowerSELECT for scalar FP operations. I replaced FSETCCss, FSETCCsd with one node type FSETCCs. Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1. llvm-svn: 197384
2013-12-16 21:52:35 +08:00
def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
//def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
Reapply 132424 with fixes. This fixes PR10068. rdar://problem/5993888 llvm-svn: 132606
2011-06-04 07:53:54 +08:00
Enabling new condition code modeling scheme. llvm-svn: 42459
2007-09-29 08:00:36 +08:00
def SDTX86Cmov : SDTypeProfile<1, 4,
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 09:57:46 +08:00
[SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
Added support for cmp, test, and conditional move instructions. llvm-svn: 24756
2005-12-17 09:24:02 +08:00
Re-apply 66008, now that the unfoldMemoryOperand bug is fixed. llvm-svn: 66058
2009-03-05 03:44:21 +08:00
// Unary and binary operator instructions that set EFLAGS as a side-effect.
Switch SDTUnaryArithWithFlags to being modeled as a two-result ISD node. The only change in the generated isel code are comments like: < // Src: (X86dec_flag:i16 GR16:i16:$src) --- > // Src: (X86dec_flag:i16:i32 GR16:i16:$src) because now it knows that X86dec_flag returns both an i16 (for the result) and an i32 (for EFLAGS) in this case. Wewt. llvm-svn: 99369
2010-03-24 08:47:47 +08:00
def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
[SDTCisInt<0>, SDTCisVT<1, i32>]>;
switch SDTBinaryArithWithFlags to be a multiple-result node as well. llvm-svn: 99370
2010-03-24 08:49:29 +08:00
def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
[SDTCisSameAs<0, 2>,
SDTCisSameAs<0, 3>,
SDTCisInt<0>, SDTCisVT<1, i32>]>;
Change the X86 backend to stop using the evil ADDC/ADDE/SUBC/SUBE nodes (which their carry depenedencies with MVT::Flag operands) and use clean and beautiful EFLAGS dependences instead. We do this by changing the modelling of SBB/ADC to have EFLAGS input and outputs (which is what requires the previous scheduler change) and change X86 ISelLowering to custom lower ADDC and friends down to X86ISD::ADD/ADC/SUB/SBB nodes. With the previous series of changes, this causes no changes in the testsuite, woo. llvm-svn: 122213
2010-12-20 08:59:46 +08:00
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
// SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
Change the X86 backend to stop using the evil ADDC/ADDE/SUBC/SUBE nodes (which their carry depenedencies with MVT::Flag operands) and use clean and beautiful EFLAGS dependences instead. We do this by changing the modelling of SBB/ADC to have EFLAGS input and outputs (which is what requires the previous scheduler change) and change X86 ISelLowering to custom lower ADDC and friends down to X86ISD::ADD/ADC/SUB/SBB nodes. With the previous series of changes, this causes no changes in the testsuite, woo. llvm-svn: 122213
2010-12-20 08:59:46 +08:00
def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
[SDTCisSameAs<0, 2>,
SDTCisSameAs<0, 3>,
SDTCisInt<0>,
SDTCisVT<1, i32>,
SDTCisVT<4, i32>]>;
it turns out that when ".with.overflow" intrinsics were added to the X86 backend that they were all implemented except umul. This one fell back to the default implementation that did a hi/lo multiply and compared the top. Fix this to check the overflow flag that the 'mul' instruction sets, so we can avoid an explicit test. Now we compile: void *func(long count) { return new int[count]; } into: __Z4funcl: ## @_Z4funcl movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00] movq %rdi, %rax ## encoding: [0x48,0x89,0xf8] mulq %rcx ## encoding: [0x48,0xf7,0xe1] seto %cl ## encoding: [0x0f,0x90,0xc1] testb %cl, %cl ## encoding: [0x84,0xc9] movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff] cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8] jmp __Znam ## TAILCALL instead of: __Z4funcl: ## @_Z4funcl movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00] movq %rdi, %rax ## encoding: [0x48,0x89,0xf8] mulq %rcx ## encoding: [0x48,0xf7,0xe1] testq %rdx, %rdx ## encoding: [0x48,0x85,0xd2] movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff] cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8] jmp __Znam ## TAILCALL Other than the silly seto+test, this is using the o bit directly, so it's going in the right direction. llvm-svn: 120935
2010-12-05 15:30:36 +08:00
// RES1, RES2, FLAGS = op LHS, RHS
def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
[SDTCisSameAs<0, 1>,
SDTCisSameAs<0, 2>,
SDTCisSameAs<0, 3>,
SDTCisInt<0>, SDTCisVT<1, i32>]>;
Enabling new condition code modeling scheme. llvm-svn: 42459
2007-09-29 08:00:36 +08:00
def SDTX86BrCond : SDTypeProfile<0, 3,
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 09:57:46 +08:00
[SDTCisVT<0, OtherVT>,
SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
Added support for cmp, test, and conditional move instructions. llvm-svn: 24756
2005-12-17 09:24:02 +08:00
Enabling new condition code modeling scheme. llvm-svn: 42459
2007-09-29 08:00:36 +08:00
def SDTX86SetCC : SDTypeProfile<1, 2,
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 09:57:46 +08:00
[SDTCisVT<0, i8>,
SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
Re-enable 91381 with fixes. llvm-svn: 91489
2009-12-16 08:53:11 +08:00
def SDTX86SetCC_C : SDTypeProfile<1, 2,
[SDTCisInt<0>,
SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
* Added support for X86 RET with an additional operand to specify number of bytes to pop off stack. * Added support for X86 SETCC. llvm-svn: 24917
2005-12-22 04:21:51 +08:00
X86: Don't emit conditional floating point moves on when targeting pre-pentiumpro architectures. * Model FPSW (the FPU status word) as a register. * Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions. * During Legalize/Lowering, build a node sequence to transfer the comparison result from FPSW into EFLAGS. If you're wondering about the right-shift: That's an implicit sub-register extraction (%ax -> %ah) which is handled later on by the instruction selector. Fixes PR6679. Patch by Christoph Erhardt! llvm-svn: 155704
2012-04-27 20:07:43 +08:00
def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
Add intrinsics for Ivy Bridge's rdrand instruction. The rdrand/cmov sequence is the same that is emitted by both GCC and ICC. Fixes PR13284. llvm-svn: 160117
2012-07-12 17:31:43 +08:00
def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
Fix Whitespace. llvm-svn: 116972
2010-10-21 07:40:27 +08:00
def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
all but CAS working on x86 llvm-svn: 47798
2008-03-02 05:52:34 +08:00
SDTCisVT<2, i8>]>;
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction. llvm-svn: 138660
2011-08-27 05:21:21 +08:00
def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
all but CAS working on x86 llvm-svn: 47798
2008-03-02 05:52:34 +08:00
Handle some 64-bit atomics on x86-32, some of the time. llvm-svn: 56963
2008-10-03 02:53:47 +08:00
def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
Change the model for FP Stack return to use fp operands on the RET instruction instead of using FpSET_ST0_32. This also generalizes the code to handling returning of multiple FP results. llvm-svn: 48209
2008-03-11 11:23:40 +08:00
def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
X86 conditional branch support. llvm-svn: 24870
2005-12-20 07:12:38 +08:00
Test commit: fixed spacing. llvm-svn: 74022
2009-06-24 07:25:37 +08:00
def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
SDTCisVT<1, i32>]>;
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS. llvm-svn: 25158
2006-01-10 02:33:28 +08:00
Fix a tblgen problem handling variable_ops in tblgen instruction definitions. This adds a new construct, "discard", for indicating that a named node in the input matching pattern is to be discarded, instead of corresponding to a node in the output pattern. This allows tblgen to know where the arguments for the varaible_ops are supposed to begin. This fixes "rdar://5791600", whatever that is ;-). llvm-svn: 51699
2008-05-30 03:57:41 +08:00
def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS. llvm-svn: 25158
2006-01-10 02:33:28 +08:00
On x86-64, for a varargs function, don't store the xmm registers to the register save area if %al is 0. This avoids touching xmm regsiters when they aren't actually used. llvm-svn: 79061
2009-08-15 09:38:56 +08:00
def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
SDTCisVT<1, iPTR>,
SDTCisVT<2, iPTR>]>;
Initial va_arg support for x86-64. Patch by David Meyer! llvm-svn: 116319
2010-10-13 02:00:49 +08:00
def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
SDTCisPtrTy<1>,
SDTCisVT<2, i32>,
SDTCisVT<3, i8>,
SDTCisVT<4, i32>]>;
revert r99743, this is saying that the repmovs instructinos have an *input* of other type, which is the VT. llvm-svn: 99749
2010-03-28 15:38:39 +08:00
def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
Lower dynamic stack allocation on mingw32 to separate instruction. We cannot use a normal call here since it has extra unmodelled side effects (it changes stack pointer). This should fix PR5292. llvm-svn: 97884
2010-03-07 03:32:29 +08:00
def SDTX86Void : SDTypeProfile<0, 0, []>;
* Added lowering hook for external weak global address. It inserts a load for Darwin. * Added lowering hook for ISD::RET. It inserts CopyToRegs for the return value (or store / fld / copy to ST(0) for floating point value). This eliminate the need to write C++ code to handle RET with variable number of operands. llvm-svn: 24888
2005-12-21 10:39:21 +08:00
* Allow mul, shl nodes to be codegen'd as LEA (if appropriate). * Add patterns to handle GlobalAddress, ConstantPool, etc. MOV32ri to materialize these nodes in registers. ADD32ri to handle %reg + GA, etc. MOV32mi to handle store GA, etc. to memory. llvm-svn: 26374
2006-02-25 18:02:21 +08:00
def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
For general dynamic TLS access we must use leaq foo@TLSGD(%rip), %rdi as part of the instruction sequence. Using a register other than %rdi and then copying it to %rdi is not valid. llvm-svn: 69350
2009-04-17 22:35:58 +08:00
def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
Implement "general dynamic", "initial exec" and "local exec" TLS models for X86 32 bits. llvm-svn: 36283
2007-04-21 05:38:10 +08:00
Implement the local-dynamic TLS model for x86 (PR3985) This implements codegen support for accesses to thread-local variables using the local-dynamic model, and adds a clean-up pass so that the base address for the TLS block can be re-used between local-dynamic access on an execution path. llvm-svn: 157818
2012-06-02 00:27:21 +08:00
def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
Rewrite the darwin tlv support to use a chain and return to copying the output to the correct register. Fixes a hidden problem uncovered by the last patch where we'd try to DAG combine our MVT::Other node oddly. llvm-svn: 121358
2010-12-09 14:25:53 +08:00
def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
Add first pass at darwin tls compiler support. llvm-svn: 105381
2010-06-03 12:07:48 +08:00
Adds a SelectionDAG node X86SegAlloca which will be custom lowered from DYNAMIC_STACKALLOC. Two new pseudo instructions (SEG_ALLOCA_32 and SEG_ALLOCA_64) which will match X86SegAlloca (based on word size) are also added. They will be custom emitted to inject the actual stack handling code. Patch by Sanjoy Das. llvm-svn: 138814
2011-08-31 03:43:21 +08:00
def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
Add WIN_FTOL_* psudo-instructions to model the unique calling convention used by the Win32 _ftol2 runtime function. Patch by Joe Groff! llvm-svn: 151382
2012-02-25 03:01:22 +08:00
def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
Long live the exception handling! This patch fills the last necessary bits to enable exceptions handling in LLVM. Currently only on x86-32/linux. In fact, this patch adds necessary intrinsics (and their lowering) which represent really weird target-specific gcc builtins used inside unwinder. After corresponding llvm-gcc patch will land (easy) exceptions should be more or less workable. However, exceptions handling support should not be thought as 'finished': I expect many small and not so small glitches everywhere. llvm-svn: 39855
2007-07-14 22:06:15 +08:00
def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
Added tail call optimization to the x86 back end. It can be enabled by passing -tailcallopt to llc. The optimization is performed if the following conditions are satisfied: * caller/callee are fastcc * elf/pic is disabled OR elf/pic enabled + callee is in module + callee has visibility protected or hidden llvm-svn: 42870
2007-10-12 03:40:01 +08:00
def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
Custom lower the memory barrier instructions and add support for lowering without sse2. Add a couple of new testcases. Fixes a few libgomp tests and latent bugs. Remove a few todos. llvm-svn: 109078
2010-07-22 10:48:34 +08:00
def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
X86MemBarrier has unmodeled side effects. llvm-svn: 162514
2012-08-24 08:31:10 +08:00
[SDNPHasChain,SDNPSideEffect]>;
Custom lower the memory barrier instructions and add support for lowering without sse2. Add a couple of new testcases. Fixes a few libgomp tests and latent bugs. Remove a few todos. llvm-svn: 109078
2010-07-22 10:48:34 +08:00
def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
[SDNPHasChain]>;
def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
[SDNPHasChain]>;
def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
[SDNPHasChain]>;
fix some modelling problems exposed by a patch I'm working on. bsr/bsf/ptest nodes all have an EFLAGS result when made by isel lowering. llvm-svn: 99736
2010-03-28 13:07:17 +08:00
def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS. llvm-svn: 25158
2006-01-10 02:33:28 +08:00
def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
* Added lowering hook for external weak global address. It inserts a load for Darwin. * Added lowering hook for ISD::RET. It inserts CopyToRegs for the return value (or store / fld / copy to ST(0) for floating point value). This eliminate the need to write C++ code to handle RET with variable number of operands. llvm-svn: 24888
2005-12-21 10:39:21 +08:00
Enabling new condition code modeling scheme. llvm-svn: 42459
2007-09-29 08:00:36 +08:00
def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
Add instruction patterns and encodings for the x86 bt instructions. llvm-svn: 61400
2008-12-24 06:45:23 +08:00
def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
Enabling new condition code modeling scheme. llvm-svn: 42459
2007-09-29 08:00:36 +08:00
def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS. llvm-svn: 25158
2006-01-10 02:33:28 +08:00
def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 09:57:46 +08:00
[SDNPHasChain]>;
Enabling new condition code modeling scheme. llvm-svn: 42459
2007-09-29 08:00:36 +08:00
def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
Re-enable 91381 with fixes. llvm-svn: 91489
2009-12-16 08:53:11 +08:00
def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
* Added lowering hook for external weak global address. It inserts a load for Darwin. * Added lowering hook for ISD::RET. It inserts CopyToRegs for the return value (or store / fld / copy to ST(0) for floating point value). This eliminate the need to write C++ code to handle RET with variable number of operands. llvm-svn: 24888
2005-12-21 10:39:21 +08:00
X86: Don't emit conditional floating point moves on when targeting pre-pentiumpro architectures. * Model FPSW (the FPU status word) as a register. * Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions. * During Legalize/Lowering, build a node sequence to transfer the comparison result from FPSW into EFLAGS. If you're wondering about the right-shift: That's an implicit sub-register extraction (%ax -> %ah) which is handled later on by the instruction selector. Fixes PR6679. Patch by Christoph Erhardt! llvm-svn: 155704
2012-04-27 20:07:43 +08:00
def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
Give the rdrand instructions a SideEffect flag and a chain so MachineCSE and MachineLICM don't touch it. I already had the necessary things in place for IR-level passes but missed the machine passes. llvm-svn: 160137
2012-07-13 02:14:57 +08:00
def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand,
[SDNPHasChain, SDNPSideEffect]>;
Add intrinsics for Ivy Bridge's rdrand instruction. The rdrand/cmov sequence is the same that is emitted by both GCC and ICC. Fixes PR13284. llvm-svn: 160117
2012-07-12 17:31:43 +08:00
Add support of RDSEED defined in AVX2 extension llvm-svn: 178314
2013-03-29 07:41:26 +08:00
def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand,
[SDNPHasChain, SDNPSideEffect]>;
all but CAS working on x86 llvm-svn: 47798
2008-03-02 05:52:34 +08:00
def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
Flag -> Glue, the ongoing saga llvm-svn: 122513
2010-12-24 02:28:41 +08:00
[SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
give VZEXT_LOAD a memory operand, it now works with segment registers. llvm-svn: 114515
2010-09-22 08:34:38 +08:00
SDNPMayLoad, SDNPMemOperand]>;
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction. llvm-svn: 138660
2011-08-27 05:21:21 +08:00
def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
Flag -> Glue, the ongoing saga llvm-svn: 122513
2010-12-24 02:28:41 +08:00
[SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
give VZEXT_LOAD a memory operand, it now works with segment registers. llvm-svn: 114515
2010-09-22 08:34:38 +08:00
SDNPMayLoad, SDNPMemOperand]>;
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction. llvm-svn: 138660
2011-08-27 05:21:21 +08:00
def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
[SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
SDNPMayLoad, SDNPMemOperand]>;
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS. llvm-svn: 25158
2006-01-10 02:33:28 +08:00
def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
Flag -> Glue, the ongoing saga llvm-svn: 122513
2010-12-24 02:28:41 +08:00
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
* Added lowering hook for external weak global address. It inserts a load for Darwin. * Added lowering hook for ISD::RET. It inserts CopyToRegs for the return value (or store / fld / copy to ST(0) for floating point value). This eliminate the need to write C++ code to handle RET with variable number of operands. llvm-svn: 24888
2005-12-21 10:39:21 +08:00
On x86-64, for a varargs function, don't store the xmm registers to the register save area if %al is 0. This avoids touching xmm regsiters when they aren't actually used. llvm-svn: 79061
2009-08-15 09:38:56 +08:00
def X86vastart_save_xmm_regs :
SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
SDT_X86VASTART_SAVE_XMM_REGS,
add a new SDNPVariadic SDNP node flag, and use it in dag isel gen instead of instruction properties. This allows the oh-so-useful behavior of matching a variadic non-root node. llvm-svn: 98934
2010-03-19 13:07:09 +08:00
[SDNPHasChain, SDNPVariadic]>;
Initial va_arg support for x86-64. Patch by David Meyer! llvm-svn: 116319
2010-10-13 02:00:49 +08:00
def X86vaarg64 :
SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
[SDNPHasChain, SDNPMayLoad, SDNPMayStore,
SDNPMemOperand]>;
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS. llvm-svn: 25158
2006-01-10 02:33:28 +08:00
def X86callseq_start :
SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
Flag -> Glue, the ongoing saga llvm-svn: 122513
2010-12-24 02:28:41 +08:00
[SDNPHasChain, SDNPOutGlue]>;
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS. llvm-svn: 25158
2006-01-10 02:33:28 +08:00
def X86callseq_end :
SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
Flag -> Glue, the ongoing saga llvm-svn: 122513
2010-12-24 02:28:41 +08:00
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
* Added lowering hook for external weak global address. It inserts a load for Darwin. * Added lowering hook for ISD::RET. It inserts CopyToRegs for the return value (or store / fld / copy to ST(0) for floating point value). This eliminate the need to write C++ code to handle RET with variable number of operands. llvm-svn: 24888
2005-12-21 10:39:21 +08:00
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS. llvm-svn: 25158
2006-01-10 02:33:28 +08:00
def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
Flag -> Glue, the ongoing saga llvm-svn: 122513
2010-12-24 02:28:41 +08:00
[SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
add a new SDNPVariadic SDNP node flag, and use it in dag isel gen instead of instruction properties. This allows the oh-so-useful behavior of matching a variadic non-root node. llvm-svn: 98934
2010-03-19 13:07:09 +08:00
SDNPVariadic]>;
Added support for cmp, test, and conditional move instructions. llvm-svn: 24756
2005-12-17 09:24:02 +08:00
revert r99743, this is saying that the repmovs instructinos have an *input* of other type, which is the VT. llvm-svn: 99749
2010-03-28 15:38:39 +08:00
def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
Flag -> Glue, the ongoing saga llvm-svn: 122513
2010-12-24 02:28:41 +08:00
[SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
revert r99743, this is saying that the repmovs instructinos have an *input* of other type, which is the VT. llvm-svn: 99749
2010-03-28 15:38:39 +08:00
def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
Flag -> Glue, the ongoing saga llvm-svn: 122513
2010-12-24 02:28:41 +08:00
[SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
get def use info more correct. llvm-svn: 45821
2008-01-10 13:12:37 +08:00
SDNPMayLoad]>;
Support for MEMCPY and MEMSET. llvm-svn: 25226
2006-01-12 06:15:48 +08:00
Lower dynamic stack allocation on mingw32 to separate instruction. We cannot use a normal call here since it has extra unmodelled side effects (it changes stack pointer). This should fix PR5292. llvm-svn: 97884
2010-03-07 03:32:29 +08:00
def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
Flag -> Glue, the ongoing saga llvm-svn: 122513
2010-12-24 02:28:41 +08:00
[SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
[X86] Add support for Read Time Stamp Counter x86 builtin intrinsics. This patch: - Adds two new X86 builtin intrinsics ('int_x86_rdtsc' and 'int_x86_rdtscp') as GCCBuiltin intrinsics; - Teaches the backend how to lower the two new builtins; - Introduces a common function to lower READCYCLECOUNTER dag nodes and the two new rdtsc/rdtscp intrinsics; - Improves (and extends) the existing x86 test 'rdtsc.ll'; now test 'rdtsc.ll' correctly verifies that both READCYCLECOUNTER and the two new intrinsics work fine for both 64bit and 32bit Subtargets. llvm-svn: 207127
2014-04-25 01:18:27 +08:00
def X86rdtscp : SDNode<"X86ISD::RDTSCP_DAG", SDTX86Void,
[SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
[X86] Add support for builtin to read performance monitoring counters. This patch adds support for a new builtin instruction called __builtin_ia32_rdpmc. Builtin '__builtin_ia32_rdpmc' is defined as a 'GCC builtin'; on X86, it can be used to read performance monitoring counters. It takes as input the index of the performance counter to read, and returns the value of the specified performance counter as a 64-bit number. Calls to this new builtin will map to instruction RDPMC. The index in input to the builtin call is moved to register %ECX. The result of the builtin call is the value of the specified performance counter (RDPMC would return that quantity in registers RDX:RAX). This patch: - Adds builtin int_x86_rdpmc as a GCCBuiltin; - Adds a new x86 DAG node called 'RDPMC_DAG'; - Teaches how to lower this new builtin; - Adds an ISel pattern to select instruction RDPMC; - Fixes the definition of instruction RDPMC adding %RAX and %RDX as implicit definitions, and adding %ECX as implicit use; - Adds a LLVM test to verify that the new builtin is correctly selected. llvm-svn: 212049
2014-07-01 01:14:21 +08:00
def X86rdpmc : SDNode<"X86ISD::RDPMC_DAG", SDTX86Void,
[X86] Clean up whitespace as well as minor coding style llvm-svn: 223339
2014-12-04 13:20:33 +08:00
[SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
DAG based isel call support. llvm-svn: 25103
2006-01-05 08:27:02 +08:00
- Use a different wrapper node for RIP-relative GV, etc. - Proper support for both small static and PIC modes under X86-64 - Some (non-optimal) support for medium modes. llvm-svn: 32046
2006-12-01 05:55:46 +08:00
def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
* Allow mul, shl nodes to be codegen'd as LEA (if appropriate). * Add patterns to handle GlobalAddress, ConstantPool, etc. MOV32ri to materialize these nodes in registers. ADD32ri to handle %reg + GA, etc. MOV32mi to handle store GA, etc. to memory. llvm-svn: 26374
2006-02-25 18:02:21 +08:00
Implement "general dynamic", "initial exec" and "local exec" TLS models for X86 32 bits. llvm-svn: 36283
2007-04-21 05:38:10 +08:00
def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
Flag -> Glue, the ongoing saga llvm-svn: 122513
2010-12-24 02:28:41 +08:00
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
Implement "general dynamic", "initial exec" and "local exec" TLS models for X86 32 bits. llvm-svn: 36283
2007-04-21 05:38:10 +08:00
Implement the local-dynamic TLS model for x86 (PR3985) This implements codegen support for accesses to thread-local variables using the local-dynamic model, and adds a clean-up pass so that the base address for the TLS block can be re-used between local-dynamic access on an execution path. llvm-svn: 157818
2012-06-02 00:27:21 +08:00
def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
Long live the exception handling! This patch fills the last necessary bits to enable exceptions handling in LLVM. Currently only on x86-32/linux. In fact, this patch adds necessary intrinsics (and their lowering) which represent really weird target-specific gcc builtins used inside unwinder. After corresponding llvm-gcc patch will land (easy) exceptions should be more or less workable. However, exceptions handling support should not be thought as 'finished': I expect many small and not so small glitches everywhere. llvm-svn: 39855
2007-07-14 22:06:15 +08:00
def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
[SDNPHasChain]>;
Add __builtin_setjmp/_longjmp supprt in X86 backend - Besides used in SjLj exception handling, __builtin_setjmp/__longjmp is also used as a light-weight replacement of setjmp/longjmp which are used to implementation continuation, user-level threading, and etc. The support added in this patch ONLY addresses this usage and is NOT intended to support SjLj exception handling as zero-cost DWARF exception handling is used by default in X86. llvm-svn: 165989
2012-10-16 06:39:43 +08:00
def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP",
SDTypeProfile<1, 1, [SDTCisInt<0>,
SDTCisPtrTy<1>]>,
[SDNPHasChain, SDNPSideEffect]>;
def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP",
SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
[SDNPHasChain, SDNPSideEffect]>;
Fix Whitespace. llvm-svn: 116972
2010-10-21 07:40:27 +08:00
def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
Flag -> Glue, the ongoing saga llvm-svn: 122513
2010-12-24 02:28:41 +08:00
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
Implement "general dynamic", "initial exec" and "local exec" TLS models for X86 32 bits. llvm-svn: 36283
2007-04-21 05:38:10 +08:00
Add SDNPCommutative and SDNPAssociative to several X86 target nodes. This lets isel fold loads into them in more cases. llvm-svn: 92506
2010-01-05 04:51:05 +08:00
def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
Remove the SDNPAssociative properties for the flags-producing operators. Eli pointed out that it's not obvious what that would mean. llvm-svn: 92555
2010-01-05 08:44:20 +08:00
[SDNPCommutative]>;
Re-apply 66008, now that the unfoldMemoryOperand bug is fixed. llvm-svn: 66058
2009-03-05 03:44:21 +08:00
def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
Add SDNPCommutative and SDNPAssociative to several X86 target nodes. This lets isel fold loads into them in more cases. llvm-svn: 92506
2010-01-05 04:51:05 +08:00
def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
Remove the SDNPAssociative properties for the flags-producing operators. Eli pointed out that it's not obvious what that would mean. llvm-svn: 92555
2010-01-05 08:44:20 +08:00
[SDNPCommutative]>;
it turns out that when ".with.overflow" intrinsics were added to the X86 backend that they were all implemented except umul. This one fell back to the default implementation that did a hi/lo multiply and compared the top. Fix this to check the overflow flag that the 'mul' instruction sets, so we can avoid an explicit test. Now we compile: void *func(long count) { return new int[count]; } into: __Z4funcl: ## @_Z4funcl movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00] movq %rdi, %rax ## encoding: [0x48,0x89,0xf8] mulq %rcx ## encoding: [0x48,0xf7,0xe1] seto %cl ## encoding: [0x0f,0x90,0xc1] testb %cl, %cl ## encoding: [0x84,0xc9] movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff] cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8] jmp __Znam ## TAILCALL instead of: __Z4funcl: ## @_Z4funcl movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00] movq %rdi, %rax ## encoding: [0x48,0x89,0xf8] mulq %rcx ## encoding: [0x48,0xf7,0xe1] testq %rdx, %rdx ## encoding: [0x48,0x85,0xd2] movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff] cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8] jmp __Znam ## TAILCALL Other than the silly seto+test, this is using the o bit directly, so it's going in the right direction. llvm-svn: 120935
2010-12-05 15:30:36 +08:00
def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
Remove the SDNPAssociative properties for the flags-producing operators. Eli pointed out that it's not obvious what that would mean. llvm-svn: 92555
2010-01-05 08:44:20 +08:00
[SDNPCommutative]>;
Change the X86 backend to stop using the evil ADDC/ADDE/SUBC/SUBE nodes (which their carry depenedencies with MVT::Flag operands) and use clean and beautiful EFLAGS dependences instead. We do this by changing the modelling of SBB/ADC to have EFLAGS input and outputs (which is what requires the previous scheduler change) and change X86 ISelLowering to custom lower ADDC and friends down to X86ISD::ADD/ADC/SUB/SBB nodes. With the previous series of changes, this causes no changes in the testsuite, woo. llvm-svn: 122213
2010-12-20 08:59:46 +08:00
def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
Fix Whitespace. llvm-svn: 116972
2010-10-21 07:40:27 +08:00
Re-apply 66008, now that the unfoldMemoryOperand bug is fixed. llvm-svn: 66058
2009-03-05 03:44:21 +08:00
def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
Add SDNPCommutative and SDNPAssociative to several X86 target nodes. This lets isel fold loads into them in more cases. llvm-svn: 92506
2010-01-05 04:51:05 +08:00
def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
Remove the SDNPAssociative properties for the flags-producing operators. Eli pointed out that it's not obvious what that would mean. llvm-svn: 92555
2010-01-05 08:44:20 +08:00
[SDNPCommutative]>;
Add SDNPCommutative and SDNPAssociative to several X86 target nodes. This lets isel fold loads into them in more cases. llvm-svn: 92506
2010-01-05 04:51:05 +08:00
def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
Remove the SDNPAssociative properties for the flags-producing operators. Eli pointed out that it's not obvious what that would mean. llvm-svn: 92555
2010-01-05 08:44:20 +08:00
[SDNPCommutative]>;
Add SDNPCommutative and SDNPAssociative to several X86 target nodes. This lets isel fold loads into them in more cases. llvm-svn: 92506
2010-01-05 04:51:05 +08:00
def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
Remove the SDNPAssociative properties for the flags-producing operators. Eli pointed out that it's not obvious what that would mean. llvm-svn: 92555
2010-01-05 08:44:20 +08:00
[SDNPCommutative]>;
Redo the arithmetic with overflow architecture. I was changing the semantics of ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
2008-12-12 08:56:36 +08:00
BEXTR should be defined to take same type for bother operands. llvm-svn: 191728
2013-10-01 11:48:26 +08:00
def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>;
Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code. llvm-svn: 142642
2011-10-21 14:55:01 +08:00
When optimzing a mul by immediate into two, the resulting mul's should get a x86 specific node to avoid dag combiner from hacking on them further. llvm-svn: 68066
2009-03-31 05:36:47 +08:00
def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
X86: Add alloca probing to dynamic alloca on Windows. Fixes PR8424. llvm-svn: 116984
2010-10-21 09:41:01 +08:00
def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
Flag -> Glue, the ongoing saga llvm-svn: 122513
2010-12-24 02:28:41 +08:00
[SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
X86: Add alloca probing to dynamic alloca on Windows. Fixes PR8424. llvm-svn: 116984
2010-10-21 09:41:01 +08:00
Adds a SelectionDAG node X86SegAlloca which will be custom lowered from DYNAMIC_STACKALLOC. Two new pseudo instructions (SEG_ALLOCA_32 and SEG_ALLOCA_64) which will match X86SegAlloca (based on word size) are also added. They will be custom emitted to inject the actual stack handling code. Patch by Sanjoy Das. llvm-svn: 138814
2011-08-31 03:43:21 +08:00
def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
[SDNPHasChain]>;
Add first pass at darwin tls compiler support. llvm-svn: 105381
2010-06-03 12:07:48 +08:00
def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
Flag -> Glue, the ongoing saga llvm-svn: 122513
2010-12-24 02:28:41 +08:00
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
Lower dynamic stack allocation on mingw32 to separate instruction. We cannot use a normal call here since it has extra unmodelled side effects (it changes stack pointer). This should fix PR5292. llvm-svn: 97884
2010-03-07 03:32:29 +08:00
Add WIN_FTOL_* psudo-instructions to model the unique calling convention used by the Win32 _ftol2 runtime function. Patch by Joe Groff! llvm-svn: 151382
2012-02-25 03:01:22 +08:00
def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL,
[SDNPHasChain, SDNPOutGlue]>;
Added support for cmp, test, and conditional move instructions. llvm-svn: 24756
2005-12-17 09:24:02 +08:00
//===----------------------------------------------------------------------===//
// X86 Operand Definitions.
//
Add a new register class to describe operands that can't be SP, due to x86 encoding restrictions. This is currently off by default because it may cause code quality regressions. This is for PR4572. llvm-svn: 77565
2009-07-30 09:56:29 +08:00
// A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
// the index operand of an address, to conform to x86 encoding restrictions.
def ptr_rc_nosp : PointerLikeRegClass<1>;
eliminate the "call" operand modifier from the asm descriptions, modeling it as a pcrel immediate instead. This gets pc-rel weirdness out of the main printoperand codepath. llvm-svn: 73829
2009-06-21 03:34:09 +08:00
Convert asmprinter to new style of instruction printer Start asmprintergen'ifying machine instrs with memory operands. llvm-svn: 15646
2004-08-11 10:25:00 +08:00
// *mem - Operand definitions for the funky X86 addressing mode operands.
//
Remove trailing whitespace. llvm-svn: 189178
2013-08-25 03:50:11 +08:00
def X86MemAsmOperand : AsmOperandClass {
Remove some unnecessary PredicateMethod overrides. Add RenderMethod overrides to remove forwarding in the X86AsmParser code itself. No functional change. llvm-svn: 189205
2013-08-26 08:13:09 +08:00
let Name = "Mem";
llvm-mc/AsmMatcher: Change assembler parser match classes to their own record structure. llvm-svn: 78581
2009-08-11 02:41:10 +08:00
}
Remove trailing whitespace. llvm-svn: 189178
2013-08-25 03:50:11 +08:00
def X86Mem8AsmOperand : AsmOperandClass {
Remove some unnecessary PredicateMethod overrides. Add RenderMethod overrides to remove forwarding in the X86AsmParser code itself. No functional change. llvm-svn: 189205
2013-08-26 08:13:09 +08:00
let Name = "Mem8"; let RenderMethod = "addMemOperands";
Add predicate method check match memory operand size, if available. In att style asm syntax memory operand size is derived from suffix attached with mnemonic. In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction. llvm-svn: 148006
2012-01-12 09:51:42 +08:00
}
Remove trailing whitespace. llvm-svn: 189178
2013-08-25 03:50:11 +08:00
def X86Mem16AsmOperand : AsmOperandClass {
Remove some unnecessary PredicateMethod overrides. Add RenderMethod overrides to remove forwarding in the X86AsmParser code itself. No functional change. llvm-svn: 189205
2013-08-26 08:13:09 +08:00
let Name = "Mem16"; let RenderMethod = "addMemOperands";
Add predicate method check match memory operand size, if available. In att style asm syntax memory operand size is derived from suffix attached with mnemonic. In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction. llvm-svn: 148006
2012-01-12 09:51:42 +08:00
}
Remove trailing whitespace. llvm-svn: 189178
2013-08-25 03:50:11 +08:00
def X86Mem32AsmOperand : AsmOperandClass {
Remove some unnecessary PredicateMethod overrides. Add RenderMethod overrides to remove forwarding in the X86AsmParser code itself. No functional change. llvm-svn: 189205
2013-08-26 08:13:09 +08:00
let Name = "Mem32"; let RenderMethod = "addMemOperands";
Add predicate method check match memory operand size, if available. In att style asm syntax memory operand size is derived from suffix attached with mnemonic. In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction. llvm-svn: 148006
2012-01-12 09:51:42 +08:00
}
Remove trailing whitespace. llvm-svn: 189178
2013-08-25 03:50:11 +08:00
def X86Mem64AsmOperand : AsmOperandClass {
Remove some unnecessary PredicateMethod overrides. Add RenderMethod overrides to remove forwarding in the X86AsmParser code itself. No functional change. llvm-svn: 189205
2013-08-26 08:13:09 +08:00
let Name = "Mem64"; let RenderMethod = "addMemOperands";
Add predicate method check match memory operand size, if available. In att style asm syntax memory operand size is derived from suffix attached with mnemonic. In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction. llvm-svn: 148006
2012-01-12 09:51:42 +08:00
}
Remove trailing whitespace. llvm-svn: 189178
2013-08-25 03:50:11 +08:00
def X86Mem80AsmOperand : AsmOperandClass {
Remove some unnecessary PredicateMethod overrides. Add RenderMethod overrides to remove forwarding in the X86AsmParser code itself. No functional change. llvm-svn: 189205
2013-08-26 08:13:09 +08:00
let Name = "Mem80"; let RenderMethod = "addMemOperands";
Add predicate method check match memory operand size, if available. In att style asm syntax memory operand size is derived from suffix attached with mnemonic. In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction. llvm-svn: 148006
2012-01-12 09:51:42 +08:00
}
Remove trailing whitespace. llvm-svn: 189178
2013-08-25 03:50:11 +08:00
def X86Mem128AsmOperand : AsmOperandClass {
Remove some unnecessary PredicateMethod overrides. Add RenderMethod overrides to remove forwarding in the X86AsmParser code itself. No functional change. llvm-svn: 189205
2013-08-26 08:13:09 +08:00
let Name = "Mem128"; let RenderMethod = "addMemOperands";
Add predicate method check match memory operand size, if available. In att style asm syntax memory operand size is derived from suffix attached with mnemonic. In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction. llvm-svn: 148006
2012-01-12 09:51:42 +08:00
}
Remove trailing whitespace. llvm-svn: 189178
2013-08-25 03:50:11 +08:00
def X86Mem256AsmOperand : AsmOperandClass {
Remove some unnecessary PredicateMethod overrides. Add RenderMethod overrides to remove forwarding in the X86AsmParser code itself. No functional change. llvm-svn: 189205
2013-08-26 08:13:09 +08:00
let Name = "Mem256"; let RenderMethod = "addMemOperands";
Add predicate method check match memory operand size, if available. In att style asm syntax memory operand size is derived from suffix attached with mnemonic. In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction. llvm-svn: 148006
2012-01-12 09:51:42 +08:00
}
Put some of the AVX-512 parsing stuff in a more consistent place with the existing functions. llvm-svn: 189204
2013-08-26 07:18:05 +08:00
def X86Mem512AsmOperand : AsmOperandClass {
Remove some unnecessary PredicateMethod overrides. Add RenderMethod overrides to remove forwarding in the X86AsmParser code itself. No functional change. llvm-svn: 189205
2013-08-26 08:13:09 +08:00
let Name = "Mem512"; let RenderMethod = "addMemOperands";
Put some of the AVX-512 parsing stuff in a more consistent place with the existing functions. llvm-svn: 189204
2013-08-26 07:18:05 +08:00
}
Add predicate method check match memory operand size, if available. In att style asm syntax memory operand size is derived from suffix attached with mnemonic. In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction. llvm-svn: 148006
2012-01-12 09:51:42 +08:00
Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. llvm-svn: 160420
2012-07-18 12:11:12 +08:00
// Gather mem operands
def X86MemVX32Operand : AsmOperandClass {
Remove some unnecessary PredicateMethod overrides. Add RenderMethod overrides to remove forwarding in the X86AsmParser code itself. No functional change. llvm-svn: 189205
2013-08-26 08:13:09 +08:00
let Name = "MemVX32"; let RenderMethod = "addMemOperands";
Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. llvm-svn: 160420
2012-07-18 12:11:12 +08:00
}
def X86MemVY32Operand : AsmOperandClass {
Remove some unnecessary PredicateMethod overrides. Add RenderMethod overrides to remove forwarding in the X86AsmParser code itself. No functional change. llvm-svn: 189205
2013-08-26 08:13:09 +08:00
let Name = "MemVY32"; let RenderMethod = "addMemOperands";
Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. llvm-svn: 160420
2012-07-18 12:11:12 +08:00
}
Put some of the AVX-512 parsing stuff in a more consistent place with the existing functions. llvm-svn: 189204
2013-08-26 07:18:05 +08:00
def X86MemVZ32Operand : AsmOperandClass {
Remove some unnecessary PredicateMethod overrides. Add RenderMethod overrides to remove forwarding in the X86AsmParser code itself. No functional change. llvm-svn: 189205
2013-08-26 08:13:09 +08:00
let Name = "MemVZ32"; let RenderMethod = "addMemOperands";
Put some of the AVX-512 parsing stuff in a more consistent place with the existing functions. llvm-svn: 189204
2013-08-26 07:18:05 +08:00
}
Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. llvm-svn: 160420
2012-07-18 12:11:12 +08:00
def X86MemVX64Operand : AsmOperandClass {
Remove some unnecessary PredicateMethod overrides. Add RenderMethod overrides to remove forwarding in the X86AsmParser code itself. No functional change. llvm-svn: 189205
2013-08-26 08:13:09 +08:00
let Name = "MemVX64"; let RenderMethod = "addMemOperands";
Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. llvm-svn: 160420
2012-07-18 12:11:12 +08:00
}
def X86MemVY64Operand : AsmOperandClass {
Remove some unnecessary PredicateMethod overrides. Add RenderMethod overrides to remove forwarding in the X86AsmParser code itself. No functional change. llvm-svn: 189205
2013-08-26 08:13:09 +08:00
let Name = "MemVY64"; let RenderMethod = "addMemOperands";
Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. llvm-svn: 160420
2012-07-18 12:11:12 +08:00
}
Added encoding prefixes for KNL instructions (EVEX). Added 512-bit operands printing. Added instruction formats for KNL instructions. llvm-svn: 187324
2013-07-28 16:28:38 +08:00
def X86MemVZ64Operand : AsmOperandClass {
Remove some unnecessary PredicateMethod overrides. Add RenderMethod overrides to remove forwarding in the X86AsmParser code itself. No functional change. llvm-svn: 189205
2013-08-26 08:13:09 +08:00
let Name = "MemVZ64"; let RenderMethod = "addMemOperands";
Added encoding prefixes for KNL instructions (EVEX). Added 512-bit operands printing. Added instruction formats for KNL instructions. llvm-svn: 187324
2013-07-28 16:28:38 +08:00
}
MC/X86: X86AbsMemAsmOperand is subclass of X86NoSegMemAsmOperand. - This fixes "leal 0, %eax", for example. llvm-svn: 103205
2010-05-07 06:39:14 +08:00
def X86AbsMemAsmOperand : AsmOperandClass {
let Name = "AbsMem";
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 07:46:44 +08:00
let SuperClasses = [X86MemAsmOperand];
MC/X86: X86AbsMemAsmOperand is subclass of X86NoSegMemAsmOperand. - This fixes "leal 0, %eax", for example. llvm-svn: 103205
2010-05-07 06:39:14 +08:00
}
Use generic iPTR instead i32 to represent pointer type. llvm-svn: 28371
2006-05-18 05:21:41 +08:00
class X86MemOperand<string printMethod> : Operand<iPTR> {
No longer track value types for asm printer operands, and remove them as an argument to every operand printing function. Requires some slight tweaks to x86, the only user. llvm-svn: 24541
2005-12-01 02:54:35 +08:00
let PrintMethod = printMethod;
Add a new register class to describe operands that can't be SP, due to x86 encoding restrictions. This is currently off by default because it may cause code quality regressions. This is for PR4572. llvm-svn: 77565
2009-07-30 09:56:29 +08:00
let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
llvm-mc/AsmMatcher: Change assembler parser match classes to their own record structure. llvm-svn: 78581
2009-08-11 02:41:10 +08:00
let ParserMatchClass = X86MemAsmOperand;
Convert asmprinter to new style of instruction printer Start asmprintergen'ifying machine instrs with memory operands. llvm-svn: 15646
2004-08-11 10:25:00 +08:00
}
No longer track value types for asm printer operands, and remove them as an argument to every operand printing function. Requires some slight tweaks to x86, the only user. llvm-svn: 24541
2005-12-01 02:54:35 +08:00
Port operand types for ARM and X86 over from EDIS to the .td files. llvm-svn: 135198
2011-07-15 05:47:22 +08:00
let OperandType = "OPERAND_MEMORY" in {
Added opaque 32-, 48-, and 80-bit memory operand types to the X86 instruction tables to support segmented addressing (and other objects of obscure type). Modified the X86 assembly printers to handle these new operand types. Added JMP and CALL instructions that use segmented addresses. llvm-svn: 80857
2009-09-03 08:04:47 +08:00
def opaque32mem : X86MemOperand<"printopaquemem">;
def opaque48mem : X86MemOperand<"printopaquemem">;
def opaque80mem : X86MemOperand<"printopaquemem">;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def opaque512mem : X86MemOperand<"printopaquemem">;
Remove trailing whitespace. llvm-svn: 189178
2013-08-25 03:50:11 +08:00
def i8mem : X86MemOperand<"printi8mem"> {
Add predicate method check match memory operand size, if available. In att style asm syntax memory operand size is derived from suffix attached with mnemonic. In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction. llvm-svn: 148006
2012-01-12 09:51:42 +08:00
let ParserMatchClass = X86Mem8AsmOperand; }
Remove trailing whitespace. llvm-svn: 189178
2013-08-25 03:50:11 +08:00
def i16mem : X86MemOperand<"printi16mem"> {
Add predicate method check match memory operand size, if available. In att style asm syntax memory operand size is derived from suffix attached with mnemonic. In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction. llvm-svn: 148006
2012-01-12 09:51:42 +08:00
let ParserMatchClass = X86Mem16AsmOperand; }
Remove trailing whitespace. llvm-svn: 189178
2013-08-25 03:50:11 +08:00
def i32mem : X86MemOperand<"printi32mem"> {
Add predicate method check match memory operand size, if available. In att style asm syntax memory operand size is derived from suffix attached with mnemonic. In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction. llvm-svn: 148006
2012-01-12 09:51:42 +08:00
let ParserMatchClass = X86Mem32AsmOperand; }
Remove trailing whitespace. llvm-svn: 189178
2013-08-25 03:50:11 +08:00
def i64mem : X86MemOperand<"printi64mem"> {
Add predicate method check match memory operand size, if available. In att style asm syntax memory operand size is derived from suffix attached with mnemonic. In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction. llvm-svn: 148006
2012-01-12 09:51:42 +08:00
let ParserMatchClass = X86Mem64AsmOperand; }
Remove trailing whitespace. llvm-svn: 189178
2013-08-25 03:50:11 +08:00
def i128mem : X86MemOperand<"printi128mem"> {
Add predicate method check match memory operand size, if available. In att style asm syntax memory operand size is derived from suffix attached with mnemonic. In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction. llvm-svn: 148006
2012-01-12 09:51:42 +08:00
let ParserMatchClass = X86Mem128AsmOperand; }
Remove trailing whitespace. llvm-svn: 189178
2013-08-25 03:50:11 +08:00
def i256mem : X86MemOperand<"printi256mem"> {
Add predicate method check match memory operand size, if available. In att style asm syntax memory operand size is derived from suffix attached with mnemonic. In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction. llvm-svn: 148006
2012-01-12 09:51:42 +08:00
let ParserMatchClass = X86Mem256AsmOperand; }
Remove trailing whitespace. llvm-svn: 189178
2013-08-25 03:50:11 +08:00
def i512mem : X86MemOperand<"printi512mem"> {
Added encoding prefixes for KNL instructions (EVEX). Added 512-bit operands printing. Added instruction formats for KNL instructions. llvm-svn: 187324
2013-07-28 16:28:38 +08:00
let ParserMatchClass = X86Mem512AsmOperand; }
Remove trailing whitespace. llvm-svn: 189178
2013-08-25 03:50:11 +08:00
def f32mem : X86MemOperand<"printf32mem"> {
Add predicate method check match memory operand size, if available. In att style asm syntax memory operand size is derived from suffix attached with mnemonic. In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction. llvm-svn: 148006
2012-01-12 09:51:42 +08:00
let ParserMatchClass = X86Mem32AsmOperand; }
Remove trailing whitespace. llvm-svn: 189178
2013-08-25 03:50:11 +08:00
def f64mem : X86MemOperand<"printf64mem"> {
Add predicate method check match memory operand size, if available. In att style asm syntax memory operand size is derived from suffix attached with mnemonic. In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction. llvm-svn: 148006
2012-01-12 09:51:42 +08:00
let ParserMatchClass = X86Mem64AsmOperand; }
Remove trailing whitespace. llvm-svn: 189178
2013-08-25 03:50:11 +08:00
def f80mem : X86MemOperand<"printf80mem"> {
Add predicate method check match memory operand size, if available. In att style asm syntax memory operand size is derived from suffix attached with mnemonic. In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction. llvm-svn: 148006
2012-01-12 09:51:42 +08:00
let ParserMatchClass = X86Mem80AsmOperand; }
Remove trailing whitespace. llvm-svn: 189178
2013-08-25 03:50:11 +08:00
def f128mem : X86MemOperand<"printf128mem"> {
Add predicate method check match memory operand size, if available. In att style asm syntax memory operand size is derived from suffix attached with mnemonic. In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction. llvm-svn: 148006
2012-01-12 09:51:42 +08:00
let ParserMatchClass = X86Mem128AsmOperand; }
Remove trailing whitespace. llvm-svn: 189178
2013-08-25 03:50:11 +08:00
def f256mem : X86MemOperand<"printf256mem">{
Add predicate method check match memory operand size, if available. In att style asm syntax memory operand size is derived from suffix attached with mnemonic. In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction. llvm-svn: 148006
2012-01-12 09:51:42 +08:00
let ParserMatchClass = X86Mem256AsmOperand; }
Added encoding prefixes for KNL instructions (EVEX). Added 512-bit operands printing. Added instruction formats for KNL instructions. llvm-svn: 187324
2013-07-28 16:28:38 +08:00
def f512mem : X86MemOperand<"printf512mem">{
let ParserMatchClass = X86Mem512AsmOperand; }
def v512mem : Operand<iPTR> {
let PrintMethod = "printf512mem";
let MIOperandInfo = (ops ptr_rc, i8imm, VR512, i32imm, i8imm);
let ParserMatchClass = X86Mem512AsmOperand; }
Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. llvm-svn: 160420
2012-07-18 12:11:12 +08:00
// Gather mem operands
def vx32mem : X86MemOperand<"printi32mem">{
X86: add GATHER intrinsics (AVX2) in LLVM Support the following intrinsics: llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256 llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256 Modified Disassembler to handle VSIB addressing mode. llvm-svn: 159221
2012-06-27 03:47:59 +08:00
let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. llvm-svn: 160420
2012-07-18 12:11:12 +08:00
let ParserMatchClass = X86MemVX32Operand; }
def vy32mem : X86MemOperand<"printi32mem">{
X86: add GATHER intrinsics (AVX2) in LLVM Support the following intrinsics: llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256 llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256 Modified Disassembler to handle VSIB addressing mode. llvm-svn: 159221
2012-06-27 03:47:59 +08:00
let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. llvm-svn: 160420
2012-07-18 12:11:12 +08:00
let ParserMatchClass = X86MemVY32Operand; }
def vx64mem : X86MemOperand<"printi64mem">{
let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
let ParserMatchClass = X86MemVX64Operand; }
def vy64mem : X86MemOperand<"printi64mem">{
let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
let ParserMatchClass = X86MemVY64Operand; }
Added encoding prefixes for KNL instructions (EVEX). Added 512-bit operands printing. Added instruction formats for KNL instructions. llvm-svn: 187324
2013-07-28 16:28:38 +08:00
def vy64xmem : X86MemOperand<"printi64mem">{
let MIOperandInfo = (ops ptr_rc, i8imm, VR256X, i32imm, i8imm);
let ParserMatchClass = X86MemVY64Operand; }
def vz32mem : X86MemOperand<"printi32mem">{
let MIOperandInfo = (ops ptr_rc, i16imm, VR512, i32imm, i8imm);
let ParserMatchClass = X86MemVZ32Operand; }
def vz64mem : X86MemOperand<"printi64mem">{
let MIOperandInfo = (ops ptr_rc, i8imm, VR512, i32imm, i8imm);
let ParserMatchClass = X86MemVZ64Operand; }
Port operand types for ARM and X86 over from EDIS to the .td files. llvm-svn: 135198
2011-07-15 05:47:22 +08:00
}
No longer track value types for asm printer operands, and remove them as an argument to every operand printing function. Requires some slight tweaks to x86, the only user. llvm-svn: 24541
2005-12-01 02:54:35 +08:00
Implement x86 h-register extract support. - Add patterns for h-register extract, which avoids a shift and mask, and in some cases a temporary register. - Add address-mode matching for turning (X>>(8-n))&(255<<n), where n is a valid address-mode scale value, into an h-register extract and a scaled-offset address. - Replace X86's MOV32to32_ and related instructions with the new target-independent COPY_TO_SUBREG instruction. On x86-64 there are complicated constraints on h registers, and CodeGen doesn't currently provide a high-level way to express all of them, so they are handled with a bunch of special code. This code currently only supports extracts where the result is used by a zero-extend or a store, though these are fairly common. These transformations are not always beneficial; since there are only 4 h registers, they sometimes require extra move instructions, and this sometimes increases register pressure because it can force out values that would otherwise be in one of those registers. However, this appears to be relatively uncommon. llvm-svn: 68962
2009-04-14 00:09:41 +08:00
// A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
// plain GR64, so that it doesn't potentially require a REX prefix.
def i8mem_NOREX : Operand<i64> {
let PrintMethod = "printi8mem";
Add a new register class to describe operands that can't be SP, due to x86 encoding restrictions. This is currently off by default because it may cause code quality regressions. This is for PR4572. llvm-svn: 77565
2009-07-30 09:56:29 +08:00
let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
Intel syntax: Fix parser match class to check memory operand size. llvm-svn: 148338
2012-01-18 05:48:03 +08:00
let ParserMatchClass = X86Mem8AsmOperand;
Port operand types for ARM and X86 over from EDIS to the .td files. llvm-svn: 135198
2011-07-15 05:47:22 +08:00
let OperandType = "OPERAND_MEMORY";
Implement x86 h-register extract support. - Add patterns for h-register extract, which avoids a shift and mask, and in some cases a temporary register. - Add address-mode matching for turning (X>>(8-n))&(255<<n), where n is a valid address-mode scale value, into an h-register extract and a scaled-offset address. - Replace X86's MOV32to32_ and related instructions with the new target-independent COPY_TO_SUBREG instruction. On x86-64 there are complicated constraints on h registers, and CodeGen doesn't currently provide a high-level way to express all of them, so they are handled with a bunch of special code. This code currently only supports extracts where the result is used by a zero-extend or a store, though these are fairly common. These transformations are not always beneficial; since there are only 4 h registers, they sometimes require extra move instructions, and this sometimes increases register pressure because it can force out values that would otherwise be in one of those registers. However, this appears to be relatively uncommon. llvm-svn: 68962
2009-04-14 00:09:41 +08:00
}
Target/X86: Tweak win64's tailcall. llvm-svn: 124272
2011-01-26 10:04:09 +08:00
// GPRs available for tailcall.
Use ptr_rc_tailcall instead of GR32_TC. The getPointerRegClass() hook will return GR32_TC, or whatever is appropriate for the current function. Patch by Yiannis Tsiouris! llvm-svn: 156459
2012-05-09 09:50:09 +08:00
// It represents GR32_TC, GR64_TC or GR64_TCW64.
Target/X86: Tweak win64's tailcall. llvm-svn: 124272
2011-01-26 10:04:09 +08:00
def ptr_rc_tailcall : PointerLikeRegClass<2>;
Do not force indirect tailcall through fixed registers: eax, r11. Add support to allow loads to be folded to tail call instructions. llvm-svn: 98465
2010-03-14 11:48:46 +08:00
// Special i32mem for addresses of load folding tail calls. These are not
// allowed to use callee-saved registers since they must be scheduled
// after callee-saved register are popped.
def i32mem_TC : Operand<i32> {
let PrintMethod = "printi32mem";
Use ptr_rc_tailcall instead of GR32_TC. The getPointerRegClass() hook will return GR32_TC, or whatever is appropriate for the current function. Patch by Yiannis Tsiouris! llvm-svn: 156459
2012-05-09 09:50:09 +08:00
let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
i32imm, i8imm);
Intel syntax: Fix parser match class to check memory operand size. llvm-svn: 148338
2012-01-18 05:48:03 +08:00
let ParserMatchClass = X86Mem32AsmOperand;
Port operand types for ARM and X86 over from EDIS to the .td files. llvm-svn: 135198
2011-07-15 05:47:22 +08:00
let OperandType = "OPERAND_MEMORY";
Do not force indirect tailcall through fixed registers: eax, r11. Add support to allow loads to be folded to tail call instructions. llvm-svn: 98465
2010-03-14 11:48:46 +08:00
}
move various pattern matching support goop out of X86Instr64Bit, to live with the 32-bit stuff. llvm-svn: 115602
2010-10-05 14:37:31 +08:00
// Special i64mem for addresses of load folding tail calls. These are not
// allowed to use callee-saved registers since they must be scheduled
// after callee-saved register are popped.
def i64mem_TC : Operand<i64> {
let PrintMethod = "printi64mem";
Target/X86: Tweak win64's tailcall. llvm-svn: 124272
2011-01-26 10:04:09 +08:00
let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
ptr_rc_tailcall, i32imm, i8imm);
Intel syntax: Fix parser match class to check memory operand size. llvm-svn: 148338
2012-01-18 05:48:03 +08:00
let ParserMatchClass = X86Mem64AsmOperand;
Port operand types for ARM and X86 over from EDIS to the .td files. llvm-svn: 135198
2011-07-15 05:47:22 +08:00
let OperandType = "OPERAND_MEMORY";
move various pattern matching support goop out of X86Instr64Bit, to live with the 32-bit stuff. llvm-svn: 115602
2010-10-05 14:37:31 +08:00
}
Committing X86-64 support. llvm-svn: 30177
2006-09-08 14:48:29 +08:00
Port operand types for ARM and X86 over from EDIS to the .td files. llvm-svn: 135198
2011-07-15 05:47:22 +08:00
let OperandType = "OPERAND_PCREL",
ParserMatchClass = X86AbsMemAsmOperand,
Update function names to conform to guidelines. No functional change intended. llvm-svn: 163561
2012-09-11 06:50:57 +08:00
PrintMethod = "printPCRelImm" in {
X86.td: Refactor to bring operands that use print_pcrel_imm together. llvm-svn: 94861
2010-01-30 08:24:12 +08:00
def i32imm_pcrel : Operand<i32>;
Implement the major chunk of PR7195: support for 'callw' in the integrated assembler. Still some discussion to be done. llvm-svn: 107825
2010-07-08 06:27:31 +08:00
def i16imm_pcrel : Operand<i16>;
X86.td: Refactor to bring operands that use print_pcrel_imm together. llvm-svn: 94861
2010-01-30 08:24:12 +08:00
// Branch targets have OtherVT type and print as pc-relative values.
def brtarget : Operand<OtherVT>;
def brtarget8 : Operand<OtherVT>;
}
[x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385) llvm-svn: 199803
2014-01-22 23:08:08 +08:00
def X86SrcIdx8Operand : AsmOperandClass {
let Name = "SrcIdx8";
let RenderMethod = "addSrcIdxOperands";
let SuperClasses = [X86Mem8AsmOperand];
}
def X86SrcIdx16Operand : AsmOperandClass {
let Name = "SrcIdx16";
let RenderMethod = "addSrcIdxOperands";
let SuperClasses = [X86Mem16AsmOperand];
}
def X86SrcIdx32Operand : AsmOperandClass {
let Name = "SrcIdx32";
let RenderMethod = "addSrcIdxOperands";
let SuperClasses = [X86Mem32AsmOperand];
}
def X86SrcIdx64Operand : AsmOperandClass {
let Name = "SrcIdx64";
let RenderMethod = "addSrcIdxOperands";
let SuperClasses = [X86Mem64AsmOperand];
}
[x86] Allow address-size overrides for STOS[BWLQ] (PR9385) llvm-svn: 199804
2014-01-22 23:08:21 +08:00
def X86DstIdx8Operand : AsmOperandClass {
let Name = "DstIdx8";
let RenderMethod = "addDstIdxOperands";
let SuperClasses = [X86Mem8AsmOperand];
}
def X86DstIdx16Operand : AsmOperandClass {
let Name = "DstIdx16";
let RenderMethod = "addDstIdxOperands";
let SuperClasses = [X86Mem16AsmOperand];
}
def X86DstIdx32Operand : AsmOperandClass {
let Name = "DstIdx32";
let RenderMethod = "addDstIdxOperands";
let SuperClasses = [X86Mem32AsmOperand];
}
def X86DstIdx64Operand : AsmOperandClass {
let Name = "DstIdx64";
let RenderMethod = "addDstIdxOperands";
let SuperClasses = [X86Mem64AsmOperand];
}
First round of fixes for the x86 fixes for the x86 move accumulator from/to memory offset instructions. -Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted. -x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size. -Intel syntax printing prints the ptr size and places brackets around the address immediate. Known remaining issues with these instructions: -Segment override prefix is not supported. PR16962 and PR16961. -Immediate size should be changed by address size prefix. llvm-svn: 189201
2013-08-26 06:23:38 +08:00
def X86MemOffs8AsmOperand : AsmOperandClass {
let Name = "MemOffs8";
Remove some unnecessary PredicateMethod overrides. Add RenderMethod overrides to remove forwarding in the X86AsmParser code itself. No functional change. llvm-svn: 189205
2013-08-26 08:13:09 +08:00
let RenderMethod = "addMemOffsOperands";
First round of fixes for the x86 fixes for the x86 move accumulator from/to memory offset instructions. -Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted. -x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size. -Intel syntax printing prints the ptr size and places brackets around the address immediate. Known remaining issues with these instructions: -Segment override prefix is not supported. PR16962 and PR16961. -Immediate size should be changed by address size prefix. llvm-svn: 189201
2013-08-26 06:23:38 +08:00
let SuperClasses = [X86Mem8AsmOperand];
}
def X86MemOffs16AsmOperand : AsmOperandClass {
let Name = "MemOffs16";
Remove some unnecessary PredicateMethod overrides. Add RenderMethod overrides to remove forwarding in the X86AsmParser code itself. No functional change. llvm-svn: 189205
2013-08-26 08:13:09 +08:00
let RenderMethod = "addMemOffsOperands";
First round of fixes for the x86 fixes for the x86 move accumulator from/to memory offset instructions. -Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted. -x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size. -Intel syntax printing prints the ptr size and places brackets around the address immediate. Known remaining issues with these instructions: -Segment override prefix is not supported. PR16962 and PR16961. -Immediate size should be changed by address size prefix. llvm-svn: 189201
2013-08-26 06:23:38 +08:00
let SuperClasses = [X86Mem16AsmOperand];
}
def X86MemOffs32AsmOperand : AsmOperandClass {
let Name = "MemOffs32";
Remove some unnecessary PredicateMethod overrides. Add RenderMethod overrides to remove forwarding in the X86AsmParser code itself. No functional change. llvm-svn: 189205
2013-08-26 08:13:09 +08:00
let RenderMethod = "addMemOffsOperands";
First round of fixes for the x86 fixes for the x86 move accumulator from/to memory offset instructions. -Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted. -x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size. -Intel syntax printing prints the ptr size and places brackets around the address immediate. Known remaining issues with these instructions: -Segment override prefix is not supported. PR16962 and PR16961. -Immediate size should be changed by address size prefix. llvm-svn: 189201
2013-08-26 06:23:38 +08:00
let SuperClasses = [X86Mem32AsmOperand];
}
def X86MemOffs64AsmOperand : AsmOperandClass {
let Name = "MemOffs64";
Remove some unnecessary PredicateMethod overrides. Add RenderMethod overrides to remove forwarding in the X86AsmParser code itself. No functional change. llvm-svn: 189205
2013-08-26 08:13:09 +08:00
let RenderMethod = "addMemOffsOperands";
First round of fixes for the x86 fixes for the x86 move accumulator from/to memory offset instructions. -Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted. -x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size. -Intel syntax printing prints the ptr size and places brackets around the address immediate. Known remaining issues with these instructions: -Segment override prefix is not supported. PR16962 and PR16961. -Immediate size should be changed by address size prefix. llvm-svn: 189201
2013-08-26 06:23:38 +08:00
let SuperClasses = [X86Mem64AsmOperand];
}
let OperandType = "OPERAND_MEMORY" in {
[x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385) llvm-svn: 199803
2014-01-22 23:08:08 +08:00
def srcidx8 : Operand<iPTR> {
let ParserMatchClass = X86SrcIdx8Operand;
let MIOperandInfo = (ops ptr_rc, i8imm);
let PrintMethod = "printSrcIdx8"; }
def srcidx16 : Operand<iPTR> {
let ParserMatchClass = X86SrcIdx16Operand;
let MIOperandInfo = (ops ptr_rc, i8imm);
let PrintMethod = "printSrcIdx16"; }
def srcidx32 : Operand<iPTR> {
let ParserMatchClass = X86SrcIdx32Operand;
let MIOperandInfo = (ops ptr_rc, i8imm);
let PrintMethod = "printSrcIdx32"; }
def srcidx64 : Operand<iPTR> {
let ParserMatchClass = X86SrcIdx64Operand;
let MIOperandInfo = (ops ptr_rc, i8imm);
let PrintMethod = "printSrcIdx64"; }
[x86] Allow address-size overrides for STOS[BWLQ] (PR9385) llvm-svn: 199804
2014-01-22 23:08:21 +08:00
def dstidx8 : Operand<iPTR> {
let ParserMatchClass = X86DstIdx8Operand;
let MIOperandInfo = (ops ptr_rc);
let PrintMethod = "printDstIdx8"; }
def dstidx16 : Operand<iPTR> {
let ParserMatchClass = X86DstIdx16Operand;
let MIOperandInfo = (ops ptr_rc);
let PrintMethod = "printDstIdx16"; }
def dstidx32 : Operand<iPTR> {
let ParserMatchClass = X86DstIdx32Operand;
let MIOperandInfo = (ops ptr_rc);
let PrintMethod = "printDstIdx32"; }
def dstidx64 : Operand<iPTR> {
let ParserMatchClass = X86DstIdx64Operand;
let MIOperandInfo = (ops ptr_rc);
let PrintMethod = "printDstIdx64"; }
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
2014-01-16 15:36:58 +08:00
def offset8 : Operand<iPTR> {
First round of fixes for the x86 fixes for the x86 move accumulator from/to memory offset instructions. -Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted. -x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size. -Intel syntax printing prints the ptr size and places brackets around the address immediate. Known remaining issues with these instructions: -Segment override prefix is not supported. PR16962 and PR16961. -Immediate size should be changed by address size prefix. llvm-svn: 189201
2013-08-26 06:23:38 +08:00
let ParserMatchClass = X86MemOffs8AsmOperand;
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
2014-01-16 15:36:58 +08:00
let MIOperandInfo = (ops i64imm, i8imm);
First round of fixes for the x86 fixes for the x86 move accumulator from/to memory offset instructions. -Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted. -x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size. -Intel syntax printing prints the ptr size and places brackets around the address immediate. Known remaining issues with these instructions: -Segment override prefix is not supported. PR16962 and PR16961. -Immediate size should be changed by address size prefix. llvm-svn: 189201
2013-08-26 06:23:38 +08:00
let PrintMethod = "printMemOffs8"; }
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
2014-01-16 15:36:58 +08:00
def offset16 : Operand<iPTR> {
First round of fixes for the x86 fixes for the x86 move accumulator from/to memory offset instructions. -Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted. -x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size. -Intel syntax printing prints the ptr size and places brackets around the address immediate. Known remaining issues with these instructions: -Segment override prefix is not supported. PR16962 and PR16961. -Immediate size should be changed by address size prefix. llvm-svn: 189201
2013-08-26 06:23:38 +08:00
let ParserMatchClass = X86MemOffs16AsmOperand;
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
2014-01-16 15:36:58 +08:00
let MIOperandInfo = (ops i64imm, i8imm);
First round of fixes for the x86 fixes for the x86 move accumulator from/to memory offset instructions. -Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted. -x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size. -Intel syntax printing prints the ptr size and places brackets around the address immediate. Known remaining issues with these instructions: -Segment override prefix is not supported. PR16962 and PR16961. -Immediate size should be changed by address size prefix. llvm-svn: 189201
2013-08-26 06:23:38 +08:00
let PrintMethod = "printMemOffs16"; }
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
2014-01-16 15:36:58 +08:00
def offset32 : Operand<iPTR> {
First round of fixes for the x86 fixes for the x86 move accumulator from/to memory offset instructions. -Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted. -x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size. -Intel syntax printing prints the ptr size and places brackets around the address immediate. Known remaining issues with these instructions: -Segment override prefix is not supported. PR16962 and PR16961. -Immediate size should be changed by address size prefix. llvm-svn: 189201
2013-08-26 06:23:38 +08:00
let ParserMatchClass = X86MemOffs32AsmOperand;
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
2014-01-16 15:36:58 +08:00
let MIOperandInfo = (ops i64imm, i8imm);
First round of fixes for the x86 fixes for the x86 move accumulator from/to memory offset instructions. -Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted. -x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size. -Intel syntax printing prints the ptr size and places brackets around the address immediate. Known remaining issues with these instructions: -Segment override prefix is not supported. PR16962 and PR16961. -Immediate size should be changed by address size prefix. llvm-svn: 189201
2013-08-26 06:23:38 +08:00
let PrintMethod = "printMemOffs32"; }
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
2014-01-16 15:36:58 +08:00
def offset64 : Operand<iPTR> {
First round of fixes for the x86 fixes for the x86 move accumulator from/to memory offset instructions. -Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted. -x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size. -Intel syntax printing prints the ptr size and places brackets around the address immediate. Known remaining issues with these instructions: -Segment override prefix is not supported. PR16962 and PR16961. -Immediate size should be changed by address size prefix. llvm-svn: 189201
2013-08-26 06:23:38 +08:00
let ParserMatchClass = X86MemOffs64AsmOperand;
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
2014-01-16 15:36:58 +08:00
let MIOperandInfo = (ops i64imm, i8imm);
First round of fixes for the x86 fixes for the x86 move accumulator from/to memory offset instructions. -Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted. -x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size. -Intel syntax printing prints the ptr size and places brackets around the address immediate. Known remaining issues with these instructions: -Segment override prefix is not supported. PR16962 and PR16961. -Immediate size should be changed by address size prefix. llvm-svn: 189201
2013-08-26 06:23:38 +08:00
let PrintMethod = "printMemOffs64"; }
}
Get closer to fully working scalar FP in SSE regs. This gets singlesource working, and Olden/power. llvm-svn: 22441
2005-07-15 08:38:55 +08:00
def SSECC : Operand<i8> {
let PrintMethod = "printSSECC";
Port operand types for ARM and X86 over from EDIS to the .td files. llvm-svn: 135198
2011-07-15 05:47:22 +08:00
let OperandType = "OPERAND_IMMEDIATE";
Get closer to fully working scalar FP in SSE regs. This gets singlesource working, and Olden/power. llvm-svn: 22441
2005-07-15 08:38:55 +08:00
}
Convert asmprinter to new style of instruction printer Start asmprintergen'ifying machine instrs with memory operands. llvm-svn: 15646
2004-08-11 10:25:00 +08:00
Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo. llvm-svn: 153935
2012-04-03 13:20:24 +08:00
def AVXCC : Operand<i8> {
Separate AVXCC and SSECC printing for cmpps/pd/ss/sd and add masking before the switch statement. This keeps the unreachable default case from being hit if the instruction was created with an intrinsic with too large of an immediate. llvm-svn: 165483
2012-10-09 13:26:13 +08:00
let PrintMethod = "printAVXCC";
Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo. llvm-svn: 153935
2012-04-03 13:20:24 +08:00
let OperandType = "OPERAND_IMMEDIATE";
}
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example: addw $0xFFFF, %ax should match the same as addw $-1, %ax but we used to match it to the longer encoding. llvm-svn: 104453
2010-05-23 05:02:33 +08:00
class ImmSExtAsmOperandClass : AsmOperandClass {
tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one. llvm-svn: 104452
2010-05-23 05:02:29 +08:00
let SuperClasses = [ImmAsmOperand];
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example: addw $0xFFFF, %ax should match the same as addw $-1, %ax but we used to match it to the longer encoding. llvm-svn: 104453
2010-05-23 05:02:33 +08:00
let RenderMethod = "addImmOperands";
X86: Model i64i32imm properly, as a subclass of all immediates. llvm-svn: 104272
2010-05-21 04:20:39 +08:00
}
Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions. llvm-svn: 192567
2013-10-14 12:55:01 +08:00
def X86GR32orGR64AsmOperand : AsmOperandClass {
let Name = "GR32orGR64";
}
def GR32orGR64 : RegisterOperand<GR32> {
let ParserMatchClass = X86GR32orGR64AsmOperand;
}
AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp Printing rounding control. Enncoding for EVEX_RC (rounding control). llvm-svn: 198277
2014-01-01 23:12:34 +08:00
def AVX512RC : Operand<i32> {
let PrintMethod = "printRoundingControl";
let OperandType = "OPERAND_IMMEDIATE";
}
[x86] Fix a pretty horrible bug and inconsistency in the x86 asm parsing (and latent bug in the instruction definitions). This is effectively a revert of r136287 which tried to address a specific and narrow case of immediate operands failing to be accepted by x86 instructions with a pretty heavy hammer: it introduced a new kind of operand that behaved differently. All of that is removed with this commit, but the test cases are both preserved and enhanced. The core problem that r136287 and this commit are trying to handle is that gas accepts both of the following instructions: insertps $192, %xmm0, %xmm1 insertps $-64, %xmm0, %xmm1 These will encode to the same byte sequence, with the immediate occupying an 8-bit entry. The first form was fixed by r136287 but that broke the prior handling of the second form! =[ Ironically, we would still emit the second form in some cases and then be unable to re-assemble the output. The reason why the first instruction failed to be handled is because prior to r136287 the operands ere marked 'i32i8imm' which forces them to be sign-extenable. Clearly, that won't work for 192 in a single byte. However, making thim zero-extended or "unsigned" doesn't really address the core issue either because it breaks negative immediates. The correct fix is to make these operands 'i8imm' reflecting that they can be either signed or unsigned but must be 8-bit immediates. This patch backs out r136287 and then changes those places as well as some others to use 'i8imm' rather than one of the extended variants. Naturally, this broke something else. The custom DAG nodes had to be updated to have a much more accurate type constraint of an i8 node, and a bunch of Pat immediates needed to be specified as i8 values. The fallout didn't end there though. We also then ceased to be able to match the instruction-specific intrinsics to the instructions so modified. Digging, this is because they too used i32 rather than i8 in their signature. So I've also switched those intrinsics to i8 arguments in line with the instructions. In order to make the intrinsic adjustments of course, I also had to add auto upgrading for the intrinsics. I suspect that the intrinsic argument types may have led everything down this rabbit hole. Pretty happy with the result. llvm-svn: 217310
2014-09-06 18:00:01 +08:00
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example: addw $0xFFFF, %ax should match the same as addw $-1, %ax but we used to match it to the longer encoding. llvm-svn: 104453
2010-05-23 05:02:33 +08:00
// Sign-extended immediate classes. We don't need to define the full lattice
// here because there is no instruction with an ambiguity between ImmSExti64i32
// and ImmSExti32i8.
//
// The strange ranges come from the fact that the assembler always works with
// 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
// (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 07:46:44 +08:00
// [0, 0x7FFFFFFF] |
// [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example: addw $0xFFFF, %ax should match the same as addw $-1, %ax but we used to match it to the longer encoding. llvm-svn: 104453
2010-05-23 05:02:33 +08:00
def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
let Name = "ImmSExti64i32";
}
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 07:46:44 +08:00
// [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example: addw $0xFFFF, %ax should match the same as addw $-1, %ax but we used to match it to the longer encoding. llvm-svn: 104453
2010-05-23 05:02:33 +08:00
def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
let Name = "ImmSExti16i8";
let SuperClasses = [ImmSExti64i32AsmOperand];
}
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 07:46:44 +08:00
// [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example: addw $0xFFFF, %ax should match the same as addw $-1, %ax but we used to match it to the longer encoding. llvm-svn: 104453
2010-05-23 05:02:33 +08:00
def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
let Name = "ImmSExti32i8";
}
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 07:46:44 +08:00
// [0, 0x0000007F] |
// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example: addw $0xFFFF, %ax should match the same as addw $-1, %ax but we used to match it to the longer encoding. llvm-svn: 104453
2010-05-23 05:02:33 +08:00
def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
let Name = "ImmSExti64i8";
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 07:46:44 +08:00
let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
ImmSExti64i32AsmOperand];
llvm-mc/AsmMatcher: Change assembler parser match classes to their own record structure. llvm-svn: 78581
2009-08-11 02:41:10 +08:00
}
add more patterns, patch by Evan Cheng. llvm-svn: 24406
2005-11-18 09:04:42 +08:00
// A couple of more descriptive operand definitions.
// 16-bits but only 8 bits are significant.
llvm-mc/AsmParser: Implement user defined super classes. - We can now discriminate SUB32ri8 from SUB32ri, for example. llvm-svn: 78530
2009-08-09 15:20:21 +08:00
def i16i8imm : Operand<i16> {
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example: addw $0xFFFF, %ax should match the same as addw $-1, %ax but we used to match it to the longer encoding. llvm-svn: 104453
2010-05-23 05:02:33 +08:00
let ParserMatchClass = ImmSExti16i8AsmOperand;
Port operand types for ARM and X86 over from EDIS to the .td files. llvm-svn: 135198
2011-07-15 05:47:22 +08:00
let OperandType = "OPERAND_IMMEDIATE";
llvm-mc/AsmParser: Implement user defined super classes. - We can now discriminate SUB32ri8 from SUB32ri, for example. llvm-svn: 78530
2009-08-09 15:20:21 +08:00
}
add more patterns, patch by Evan Cheng. llvm-svn: 24406
2005-11-18 09:04:42 +08:00
// 32-bits but only 8 bits are significant.
llvm-mc/AsmParser: Implement user defined super classes. - We can now discriminate SUB32ri8 from SUB32ri, for example. llvm-svn: 78530
2009-08-09 15:20:21 +08:00
def i32i8imm : Operand<i32> {
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example: addw $0xFFFF, %ax should match the same as addw $-1, %ax but we used to match it to the longer encoding. llvm-svn: 104453
2010-05-23 05:02:33 +08:00
let ParserMatchClass = ImmSExti32i8AsmOperand;
Port operand types for ARM and X86 over from EDIS to the .td files. llvm-svn: 135198
2011-07-15 05:47:22 +08:00
let OperandType = "OPERAND_IMMEDIATE";
llvm-mc/AsmParser: Implement user defined super classes. - We can now discriminate SUB32ri8 from SUB32ri, for example. llvm-svn: 78530
2009-08-09 15:20:21 +08:00
}
add more patterns, patch by Evan Cheng. llvm-svn: 24406
2005-11-18 09:04:42 +08:00
move various pattern matching support goop out of X86Instr64Bit, to live with the 32-bit stuff. llvm-svn: 115602
2010-10-05 14:37:31 +08:00
// 64-bits but only 32 bits are significant.
def i64i32imm : Operand<i64> {
let ParserMatchClass = ImmSExti64i32AsmOperand;
Port operand types for ARM and X86 over from EDIS to the .td files. llvm-svn: 135198
2011-07-15 05:47:22 +08:00
let OperandType = "OPERAND_IMMEDIATE";
move various pattern matching support goop out of X86Instr64Bit, to live with the 32-bit stuff. llvm-svn: 115602
2010-10-05 14:37:31 +08:00
}
// 64-bits but only 32 bits are significant, and those bits are treated as being
// pc relative.
def i64i32imm_pcrel : Operand<i64> {
Update function names to conform to guidelines. No functional change intended. llvm-svn: 163561
2012-09-11 06:50:57 +08:00
let PrintMethod = "printPCRelImm";
move various pattern matching support goop out of X86Instr64Bit, to live with the 32-bit stuff. llvm-svn: 115602
2010-10-05 14:37:31 +08:00
let ParserMatchClass = X86AbsMemAsmOperand;
X86: Add some operand types required to identify calls. llvm-svn: 138285
2011-08-23 06:55:32 +08:00
let OperandType = "OPERAND_PCREL";
move various pattern matching support goop out of X86Instr64Bit, to live with the 32-bit stuff. llvm-svn: 115602
2010-10-05 14:37:31 +08:00
}
// 64-bits but only 8 bits are significant.
def i64i8imm : Operand<i64> {
let ParserMatchClass = ImmSExti64i8AsmOperand;
X86: Add some operand types required to identify calls. llvm-svn: 138285
2011-08-23 06:55:32 +08:00
let OperandType = "OPERAND_IMMEDIATE";
move various pattern matching support goop out of X86Instr64Bit, to live with the 32-bit stuff. llvm-svn: 115602
2010-10-05 14:37:31 +08:00
}
def lea64_32mem : Operand<i32> {
let PrintMethod = "printi32mem";
X86: Stop LEA64_32r doing unspeakable things to its arguments. Previously LEA64_32r went through virtually the entire backend thinking it was using 32-bit registers until its blissful illusions were cruelly snatched away by MCInstLower and 64-bit equivalents were substituted at the last minute. This patch makes it behave normally, and take 64-bit registers as sources all the way through. Previous uses (for 32-bit arithmetic) are accommodated via SUBREG_TO_REG instructions which make the types and classes agree properly. llvm-svn: 183693
2013-06-11 04:43:49 +08:00
let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
move various pattern matching support goop out of X86Instr64Bit, to live with the 32-bit stuff. llvm-svn: 115602
2010-10-05 14:37:31 +08:00
let ParserMatchClass = X86MemAsmOperand;
}
Two changes relevant to LEA and x32: 1) allows the use of RIP-relative addressing in 32-bit LEA instructions under x86-64 (ILP32 and LP64) 2) separates the size of address registers in 64-bit LEA instructions from control by ILP32/LP64. llvm-svn: 174208
2013-02-02 03:28:09 +08:00
// Memory operands that use 64-bit pointers in both ILP32 and LP64.
def lea64mem : Operand<i64> {
let PrintMethod = "printi64mem";
let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
let ParserMatchClass = X86MemAsmOperand;
}
move various pattern matching support goop out of X86Instr64Bit, to live with the 32-bit stuff. llvm-svn: 115602
2010-10-05 14:37:31 +08:00
Added support for cmp, test, and conditional move instructions. llvm-svn: 24756
2005-12-17 09:24:02 +08:00
//===----------------------------------------------------------------------===//
// X86 Complex Pattern Definitions.
//
* Added intelligence to X86 LEA addressing mode matching routine so it returns false if the match is not profitable. e.g. leal 1(%eax), %eax. * Added patterns for X86 integer loads and LEA32. llvm-svn: 24635
2005-12-08 10:01:35 +08:00
// Define X86 specific addressing mode.
reimplement support for GS and FS relative address space matching by having X86DAGToDAGISel::SelectAddr get passed in the parent node of the operand match (the load/store/atomic op) and having it get the address space from that, instead of having special FS/GS addr mode operations that require duplicating the entire instruction set to support. This makes FS and GS relative accesses *far* more predictable and work much better. It also simplifies the X86 backend a bit, more to come. There is still a pending issue with nodes like ISD::PREFETCH and X86ISD::FLD, which really should be MemSDNode's but aren't. llvm-svn: 114491
2010-09-22 06:07:31 +08:00
def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 07:46:44 +08:00
def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
Resync lea32addr and lea64addr. llvm-svn: 77893
2009-08-03 00:09:17 +08:00
[add, sub, mul, X86mul_imm, shl, or, frameindex],
[]>;
Two changes relevant to LEA and x32: 1) allows the use of RIP-relative addressing in 32-bit LEA instructions under x86-64 (ILP32 and LP64) 2) separates the size of address registers in 64-bit LEA instructions from control by ILP32/LP64. llvm-svn: 174208
2013-02-02 03:28:09 +08:00
// In 64-bit mode 32-bit LEAs can use RIP-relative addressing.
X86: Stop LEA64_32r doing unspeakable things to its arguments. Previously LEA64_32r went through virtually the entire backend thinking it was using 32-bit registers until its blissful illusions were cruelly snatched away by MCInstLower and 64-bit equivalents were substituted at the last minute. This patch makes it behave normally, and take 64-bit registers as sources all the way through. Previous uses (for 32-bit arithmetic) are accommodated via SUBREG_TO_REG instructions which make the types and classes agree properly. llvm-svn: 183693
2013-06-11 04:43:49 +08:00
def lea64_32addr : ComplexPattern<i32, 5, "SelectLEA64_32Addr",
Two changes relevant to LEA and x32: 1) allows the use of RIP-relative addressing in 32-bit LEA instructions under x86-64 (ILP32 and LP64) 2) separates the size of address registers in 64-bit LEA instructions from control by ILP32/LP64. llvm-svn: 174208
2013-02-02 03:28:09 +08:00
[add, sub, mul, X86mul_imm, shl, or,
frameindex, X86WrapperRIP],
[]>;
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 07:46:44 +08:00
def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
change TLS_ADDR lowering to lower to a real mem operand, instead of matching as a global with that gets printed with the :mem modifier. All operands to lea's should be handled with the lea32mem operand kind, and this allows the TLS stuff to do this. There are several better ways to do this, but I went for the minimal change since I can't really test this (beyond make check). This also makes the use of EBX explicit in the operand list in the 32-bit, instead of implicit in the instruction. llvm-svn: 73834
2009-06-21 04:38:48 +08:00
[tglobaltlsaddr], []>;
* Added intelligence to X86 LEA addressing mode matching routine so it returns false if the match is not profitable. e.g. leal 1(%eax), %eax. * Added patterns for X86 integer loads and LEA32. llvm-svn: 24635
2005-12-08 10:01:35 +08:00
Implement the local-dynamic TLS model for x86 (PR3985) This implements codegen support for accesses to thread-local variables using the local-dynamic model, and adds a clean-up pass so that the base address for the TLS block can be re-used between local-dynamic access on an execution path. llvm-svn: 157818
2012-06-02 00:27:21 +08:00
def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
[tglobaltlsaddr], []>;
move various pattern matching support goop out of X86Instr64Bit, to live with the 32-bit stuff. llvm-svn: 115602
2010-10-05 14:37:31 +08:00
def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
[add, sub, mul, X86mul_imm, shl, or, frameindex,
X86WrapperRIP], []>;
def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
[tglobaltlsaddr], []>;
Implement the local-dynamic TLS model for x86 (PR3985) This implements codegen support for accesses to thread-local variables using the local-dynamic model, and adds a clean-up pass so that the base address for the TLS block can be re-used between local-dynamic access on an execution path. llvm-svn: 157818
2012-06-02 00:27:21 +08:00
def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
[tglobaltlsaddr], []>;
SSE2 floating point load / store patterns. SSE2 fp to int conversion patterns. llvm-svn: 24886
2005-12-21 06:59:51 +08:00
//===----------------------------------------------------------------------===//
// X86 Instruction Predicate Definitions.
add support for pentium class CPUs which do not have cmov, PR4841. Patch by Craig Smith! llvm-svn: 98496
2010-03-15 02:31:44 +08:00
def HasCMov : Predicate<"Subtarget->hasCMov()">;
def NoCMov : Predicate<"!Subtarget->hasCMov()">;
Revert this change since it breaks a couple of the AVX tests. I'm unclear if the tests are actually correct or not, but reverting for now. llvm-svn: 120847
2010-12-04 06:29:15 +08:00
Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable. llvm-svn: 121439
2010-12-10 08:26:57 +08:00
def HasMMX : Predicate<"Subtarget->hasMMX()">;
Implement support for the bizarre 3DNow! encoding (which is unlike anything else in X86), and add support for pavgusb. This is apparently the only instruction (other than movsx) that is preventing ffmpeg from building with clang. If someone else is interested in banging out the rest of the 3DNow! instructions, it should be quite easy now. llvm-svn: 115466
2010-10-04 02:08:05 +08:00
def Has3DNow : Predicate<"Subtarget->has3DNow()">;
def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable. llvm-svn: 121439
2010-12-10 08:26:57 +08:00
def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
Remove hasNoAVX method. Can just invert hasAVX instead. llvm-svn: 164664
2012-09-26 14:29:37 +08:00
def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable. llvm-svn: 121439
2010-12-10 08:26:57 +08:00
def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
Remove hasNoAVX method. Can just invert hasAVX instead. llvm-svn: 164664
2012-09-26 14:29:37 +08:00
def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable. llvm-svn: 121439
2010-12-10 08:26:57 +08:00
def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
Remove hasNoAVX method. Can just invert hasAVX instead. llvm-svn: 164664
2012-09-26 14:29:37 +08:00
def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable. llvm-svn: 121439
2010-12-10 08:26:57 +08:00
def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
Remove hasNoAVX method. Can just invert hasAVX instead. llvm-svn: 164664
2012-09-26 14:29:37 +08:00
def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable. llvm-svn: 121439
2010-12-10 08:26:57 +08:00
def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
[x86] Adjust the patterns for lowering X86vzmovl nodes which don't perform a load to use blendps rather than movss when it is available. For non-loads, blendps is *much* faster. It can execute on two ports in Sandy Bridge and Ivy Bridge, and *three* ports on Haswell. This fixes one of the "regressions" from aggressively taking the "insertion" path in the new vector shuffle lowering. This does highlight one problem with blendps -- it isn't commuted as heavily as it should be. That's future work though. llvm-svn: 219022
2014-10-04 05:38:49 +08:00
def NoSSE41 : Predicate<"!Subtarget->hasSSE41()">;
Remove hasNoAVX method. Can just invert hasAVX instead. llvm-svn: 164664
2012-09-26 14:29:37 +08:00
def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable. llvm-svn: 121439
2010-12-10 08:26:57 +08:00
def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
Remove hasNoAVX method. Can just invert hasAVX instead. llvm-svn: 164664
2012-09-26 14:29:37 +08:00
def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable. llvm-svn: 121439
2010-12-10 08:26:57 +08:00
def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
Add feature flags for AVX and FMA and fix some SSE4A feature flag initialization problems. llvm-svn: 74350
2009-06-27 06:46:54 +08:00
def HasAVX : Predicate<"Subtarget->hasAVX()">;
Add intrinsics and feature flag for read/write FS/GS base instructions. Also add AVX2 feature flag. llvm-svn: 143319
2011-10-31 03:57:21 +08:00
def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
Add HasAVX1Only predicate and use it for patterns that have an AVX1 instruction and an AVX2 instruction rather than relying on AddedComplexity. llvm-svn: 162654
2012-08-27 14:08:57 +08:00
def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
AVX-512: Removed "z" suffix from AVX-512 instructions, since it is incompatible with GCC. I moved a test from avx512-vbroadcast-crash.ll to avx512-vbroadcast.ll I defined HasAVX512 predicate as AssemblerPredicate. It means that you should invoke llvm-mc with "-mcpu=knl" to get encoding for AVX-512 instructions. I need this to let AsmMatcher to set different encoding for AVX and AVX-512 instructions that have the same mnemonic and operands (all scalar instructions). llvm-svn: 197041
2013-12-11 22:31:04 +08:00
def HasAVX512 : Predicate<"Subtarget->hasAVX512()">,
AssemblerPredicate<"FeatureAVX512", "AVX-512 ISA">;
Added encoding prefixes for KNL instructions (EVEX). Added 512-bit operands printing. Added instruction formats for KNL instructions. llvm-svn: 187324
2013-07-28 16:28:38 +08:00
def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
[SKX] Enabling SKX target and AVX512BW, AVX512DQ, AVX512VL features. Enabling HasAVX512{DQ,BW,VL} predicates. Adding VK2, VK4, VK32, VK64 masked register classes. Adding new types (v64i8, v32i16) to VR512. Extending calling conventions for new types (v64i8, v32i16) Patch by Zinovy Nis <zinovy.y.nis@intel.com> Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com> llvm-svn: 213545
2014-07-21 22:54:21 +08:00
def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;
Added encoding prefixes for KNL instructions (EVEX). Added 512-bit operands printing. Added instruction formats for KNL instructions. llvm-svn: 187324
2013-07-28 16:28:38 +08:00
def HasCDI : Predicate<"Subtarget->hasCDI()">;
def HasPFI : Predicate<"Subtarget->hasPFI()">;
AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics. llvm-svn: 192283
2013-10-09 16:16:14 +08:00
def HasERI : Predicate<"Subtarget->hasERI()">;
[SKX] Enabling SKX target and AVX512BW, AVX512DQ, AVX512VL features. Enabling HasAVX512{DQ,BW,VL} predicates. Adding VK2, VK4, VK32, VK64 masked register classes. Adding new types (v64i8, v32i16) to VR512. Extending calling conventions for new types (v64i8, v32i16) Patch by Zinovy Nis <zinovy.y.nis@intel.com> Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com> llvm-svn: 213545
2014-07-21 22:54:21 +08:00
def HasDQI : Predicate<"Subtarget->hasDQI()">;
[AVX512] Add DQ subvector inserts In AVX512f we support 64x2 and 32x8 inserts via matching them to 32x4 and 64x4 respectively. These are matched by "Alt" Pat<>'s (Alt stands for alternative VTs). Since DQ has native support for these intructions, I peeled off the non-"Alt" part of the baseclass into vinsert_for_size_no_alt. The DQ instructions are derived from this multiclass. The "Alt" Pat<>'s are disabled with DQ. Fixes <rdar://problem/18426089> llvm-svn: 219874
2014-10-16 07:42:17 +08:00
def NoDQI : Predicate<"!Subtarget->hasDQI()">;
[SKX] Enabling SKX target and AVX512BW, AVX512DQ, AVX512VL features. Enabling HasAVX512{DQ,BW,VL} predicates. Adding VK2, VK4, VK32, VK64 masked register classes. Adding new types (v64i8, v32i16) to VR512. Extending calling conventions for new types (v64i8, v32i16) Patch by Zinovy Nis <zinovy.y.nis@intel.com> Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com> llvm-svn: 213545
2014-07-21 22:54:21 +08:00
def HasBWI : Predicate<"Subtarget->hasBWI()">;
def HasVLX : Predicate<"Subtarget->hasVLX()">,
AssemblerPredicate<"FeatureVLX", "AVX-512 VLX ISA">;
[SKX] Extended non-temporal load/store instructions for AVX512VL subsets. Added avx512_movnt_vl multiclass for handling 256/128-bit forms of instruction. Added encoding and lowering tests. Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com> llvm-svn: 215536
2014-08-13 18:46:00 +08:00
def NoVLX : Predicate<"!Subtarget->hasVLX()">;
Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable. llvm-svn: 121439
2010-12-10 08:26:57 +08:00
Add HasPOPCNT predicate to the POPCNT instructions. Also mark POPCNT as modifying EFLAGS. llvm-svn: 141656
2011-10-11 15:13:09 +08:00
def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable. llvm-svn: 121439
2010-12-10 08:26:57 +08:00
def HasAES : Predicate<"Subtarget->hasAES()">;
X86: Rename the CLMUL target feature to PCLMUL. It was renamed in gcc/gas a while ago and causes all kinds of confusion because it was named differently in llvm and clang. llvm-svn: 157745
2012-05-31 22:34:17 +08:00
def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
Rename FMA3 feature flag to just FMA to match gcc so it can be added to clang. llvm-svn: 157903
2012-06-04 02:58:46 +08:00
def HasFMA : Predicate<"Subtarget->hasFMA()">;
Added encoding prefixes for KNL instructions (EVEX). Added 512-bit operands printing. Added instruction formats for KNL instructions. llvm-svn: 187324
2013-07-28 16:28:38 +08:00
def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">;
Add feature flags for AVX and FMA and fix some SSE4A feature flag initialization problems. llvm-svn: 74350
2009-06-27 06:46:54 +08:00
def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
XOP instructions and encoding tests. llvm-svn: 146407
2011-12-13 03:37:49 +08:00
def HasXOP : Predicate<"Subtarget->hasXOP()">;
Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539
2013-09-28 02:38:42 +08:00
def HasTBM : Predicate<"Subtarget->hasTBM()">;
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. llvm-svn: 141007
2011-10-04 01:28:23 +08:00
def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler. llvm-svn: 141505
2011-10-09 15:31:39 +08:00
def HasF16C : Predicate<"Subtarget->hasF16C()">;
Add intrinsics and feature flag for read/write FS/GS base instructions. Also add AVX2 feature flag. llvm-svn: 143319
2011-10-31 03:57:21 +08:00
def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
Add X86 LZCNT instruction. Including instruction selection support. llvm-svn: 141651
2011-10-11 14:44:02 +08:00
def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. llvm-svn: 141939
2011-10-14 11:21:46 +08:00
def HasBMI : Predicate<"Subtarget->hasBMI()">;
Add X86 BZHI instruction as well as BMI2 feature detection. llvm-svn: 142122
2011-10-16 15:55:05 +08:00
def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
Add support of RTM from TSX extension - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region llvm-svn: 167573
2012-11-08 15:28:54 +08:00
def HasRTM : Predicate<"Subtarget->hasRTM()">;
Add HLE target feature llvm-svn: 178082
2013-03-27 06:46:02 +08:00
def HasHLE : Predicate<"Subtarget->hasHLE()">;
Add XTEST codegen support llvm-svn: 178083
2013-03-27 06:47:01 +08:00
def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
added basic support for Intel ADX instructions -feature flag, instructions definitions, test cases llvm-svn: 175196
2013-02-15 03:08:21 +08:00
def HasADX : Predicate<"Subtarget->hasADX()">;
Partial support for Intel SHA Extensions (sha1rnds4) Add basic assembly/disassembly support for the first Intel SHA instruction 'sha1rnds4'. Also includes feature flag, and test cases. Support for the remaining instructions will follow in a separate patch. llvm-svn: 190611
2013-09-12 23:51:31 +08:00
def HasSHA : Predicate<"Subtarget->hasSHA()">;
Add support for the X86 secure guard extensions instructions in assembler (SGX). This allows assembling the two new instructions, encls and enclu for the SKX processor model. Note the diffs are a bigger than what might think, but to fit the new MRM_CF and MRM_D7 in things in the right places things had to be renumbered and shuffled down causing a bit more diffs. rdar://16228228 llvm-svn: 214460
2014-08-01 07:57:38 +08:00
def HasSGX : Predicate<"Subtarget->hasSGX()">;
Add PREFETCHW codegen support - Add 'PRFCHW' feature defined in AVX2 ISA extension llvm-svn: 178040
2013-03-27 01:47:11 +08:00
def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
Add support of RDSEED defined in AVX2 extension llvm-svn: 178314
2013-03-29 07:41:26 +08:00
def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
[x86] Enable Broadwell target. Added FeatureSMAP. Broadwell ISA includes Haswell ISA + ADX + RDSEED + SMAP llvm-svn: 216161
2014-08-21 17:16:12 +08:00
def HasSMAP : Predicate<"Subtarget->hasSMAP()">;
Enabling 3DNow! prefetch instruction for a few AMD processors: bobcat, jaguar, bulldozer and piledriver. Support for the instruction itself seems to have already been added in r178040. Differential Revision: http://llvm-reviews.chandlerc.com/D1933 llvm-svn: 192828
2013-10-17 03:04:11 +08:00
def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
Instruction selection priority fixes to remove the XMM/XMMInt/orAVX predicates. Another commit will remove orAVX functions from X86SubTarget. llvm-svn: 147841
2012-01-10 14:30:56 +08:00
def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction. llvm-svn: 138660
2011-08-27 05:21:21 +08:00
def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
[x86] Rename In32BitMode predicate to Not64BitMode That's what it actually means, and with 16-bit support it's going to be a little more relevant since in a few corner cases we may actually want to distinguish between 16-bit and 32-bit mode (for example the bare 'push' aliases to pushw/pushl etc.) Patch by David Woodhouse llvm-svn: 197768
2013-12-20 10:04:49 +08:00
def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">;
Eliminate asm parser's dependency on TargetMachine: - Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". llvm-svn: 134678
2011-07-08 09:53:10 +08:00
def In64BitMode : Predicate<"Subtarget->is64Bit()">,
X86: Better diagnostics for 32-bit vs. 64-bit mode mismatches. When an instruction as written requires 32-bit mode and we're assembling in 64-bit mode, or vice-versa, issue a more specific diagnostic about what's wrong. rdar://12700702 llvm-svn: 167937
2012-11-15 02:04:47 +08:00
AssemblerPredicate<"Mode64Bit", "64-bit mode">;
[x32] Fix segmented stacks support Summary: Update segmented-stacks*.ll tests with x32 target case and make corresponding changes to make them pass. Test Plan: tests updated with x32 target Reviewers: nadav, rafael, dschuff Subscribers: llvm-commits, zinovy.nis Differential Revision: http://reviews.llvm.org/D5245 llvm-svn: 218247
2014-09-22 21:11:35 +08:00
def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">;
def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">;
[x86] Add basic support for .code16 This is not really expected to work right yet. Mostly because we will still emit the OpSize (0x66) prefix in all the wrong places, along with a number of other corner cases. Those will all be fixed in the subsequent commits. Patch from David Woodhouse. llvm-svn: 198584
2014-01-06 12:55:54 +08:00
def In16BitMode : Predicate<"Subtarget->is16Bit()">,
AssemblerPredicate<"Mode16Bit", "16-bit mode">;
def Not16BitMode : Predicate<"!Subtarget->is16Bit()">,
AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">;
def In32BitMode : Predicate<"Subtarget->is32Bit()">,
AssemblerPredicate<"Mode32Bit", "32-bit mode">;
Unbreak Win64 CC. Step one: honour register save area, fix some alignment and provide a different set of call-clobberred registers. llvm-svn: 77962
2009-08-03 16:12:53 +08:00
def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
Remove NaClMode llvm-svn: 142338
2011-10-18 13:29:23 +08:00
def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
We need to sext global addresses in kernel code model, not zext llvm-svn: 78299
2009-08-06 19:23:24 +08:00
def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
Missed part of recent kernel codemodel tweaks llvm-svn: 78293
2009-08-06 17:11:19 +08:00
"TM.getCodeModel() != CodeModel::Kernel">;
We need to sext global addresses in kernel code model, not zext llvm-svn: 78299
2009-08-06 19:23:24 +08:00
def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
"TM.getCodeModel() == CodeModel::Kernel">;
- Switch X86-64 JIT to large code size model. - Re-enable some codegen niceties for X86-64 static relocation model codegen. - Clean ups, etc. llvm-svn: 32238
2006-12-06 03:50:18 +08:00
def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
Disable folding loads into tail call in 32-bit PIC mode. It can introduce illegal code like this: addl $12, %esp popl %esi popl %edi popl %ebx popl %ebp jmpl *__Block_deallocator-L1$pb(%esi) # TAILCALL The problem is the global base register is assigned GR32 register class. TCRETURNmi needs the registers making up the address mode to have the GR32_TC register class. The *proper* fix is for X86DAGToDAGISel::getGlobalBaseReg() to return a copy from the global base register of the machine function rather than returning the register itself. But that has the potential of causing it to be coalesced to a more restrictive register class: GR32_TC. It can introduce additional copies and spills. For something as important the PIC base, it's not worth it especially since this is not an issue on 64-bit. llvm-svn: 99455
2010-03-25 08:10:31 +08:00
def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size. llvm-svn: 91910
2009-12-23 01:47:23 +08:00
def OptForSize : Predicate<"OptForSize">;
Implement "punpckldq %xmm0, $xmm0" as "pshufd $0x50, %xmm0, %xmm" unless optimizing for code size. llvm-svn: 56711
2008-09-27 07:41:32 +08:00
def OptForSpeed : Predicate<"!OptForSize">;
Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register. llvm-svn: 61557
2009-01-02 13:35:45 +08:00
def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
Try again. Allow call to immediate address for ELF or when in static relocation mode. llvm-svn: 72160
2009-05-20 12:53:57 +08:00
def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
Skip moving call address loading into callseq when targets prefer register indirect call. To enable a load of a call address to be folded with that call, this load is moved from outside of callseq into callseq. Such a moving adds a non-glued node (that load) into a glued sequence. This non-glue load is only removed when DAG selection folds them into a memory form call instruction. When such instruction selection is disabled, it breaks DAG schedule. To prevent that, such moving is disabled when target favors register indirect call. Previous workaround disabling CALL32m/CALL64m insn selection is removed. llvm-svn: 178308
2013-03-29 07:13:21 +08:00
def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">;
[X86] Use ADD/SUB instead of INC/DEC for Silvermont According to Intel Software Optimization Manual on Silvermont INC or DEC instructions require an additional uop to merge the flags. As a result, a branch instruction depending on an INC or a DEC instruction incurs a 1 cycle penalty. Differential Revision: http://reviews.llvm.org/D3990 llvm-svn: 210466
2014-06-09 19:40:41 +08:00
def NotSlowIncDec : Predicate<"!Subtarget->slowIncDec()">;
combine consecutive subvector 16-byte loads into one 32-byte load This is a fix for PR21709 ( http://llvm.org/bugs/show_bug.cgi?id=21709 ). When we have 2 consecutive 16-byte loads that are merged into one 32-byte vector, we can use a single 32-byte load instead. But we don't do this for SandyBridge / IvyBridge because they have slower 32-byte memops. We also don't bother using 32-byte *integer* loads on a machine that only has AVX1 (btver2) because those operands would have to be split in half anyway since there is no support for 32-byte integer math ops. Differential Revision: http://reviews.llvm.org/D6492 llvm-svn: 224344
2014-12-17 00:30:01 +08:00
def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">;
SSE2 floating point load / store patterns. SSE2 fp to int conversion patterns. llvm-svn: 24886
2005-12-21 06:59:51 +08:00
Added support for cmp, test, and conditional move instructions. llvm-svn: 24756
2005-12-17 09:24:02 +08:00
//===----------------------------------------------------------------------===//
Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load ) llvm-svn: 40628
2007-07-31 16:04:03 +08:00
// X86 Instruction Format Definitions.
Added support for cmp, test, and conditional move instructions. llvm-svn: 24756
2005-12-17 09:24:02 +08:00
//
Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load ) llvm-svn: 40628
2007-07-31 16:04:03 +08:00
include "X86InstrFormats.td"
Add new TableGen instruction definitions llvm-svn: 7537
2003-08-04 05:54:21 +08:00
add more patterns, patch by Evan Cheng. llvm-svn: 24406
2005-11-18 09:04:42 +08:00
//===----------------------------------------------------------------------===//
Rework our internal representation of node predicates to expose more structure and fix some fixmes. We now have a TreePredicateFn class that handles all of the decoding of these things. This is an internal cleanup that has no impact on the code generated by tblgen. llvm-svn: 129670
2011-04-18 05:38:24 +08:00
// Pattern fragments.
add more patterns, patch by Evan Cheng. llvm-svn: 24406
2005-11-18 09:04:42 +08:00
//
* Fast call support. * FP cmp, setcc, etc. llvm-svn: 25117
2006-01-06 08:43:03 +08:00
// X86 specific condition code. These correspond to CondCode in
Reference correct header llvm-svn: 36834
2007-05-06 12:00:55 +08:00
// X86InstrInfo.h. They must be kept in synch.
X86_COND_C and X86_COND_NC are alternate mnemonics for X86_COND_B and X86_COND_AE, respectively. llvm-svn: 61835
2009-01-07 08:15:08 +08:00
def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
* Fast call support. * FP cmp, setcc, etc. llvm-svn: 25117
2006-01-06 08:43:03 +08:00
def X86_COND_NO : PatLeaf<(i8 10)>;
X86_COND_C and X86_COND_NC are alternate mnemonics for X86_COND_B and X86_COND_AE, respectively. llvm-svn: 61835
2009-01-07 08:15:08 +08:00
def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
* Fast call support. * FP cmp, setcc, etc. llvm-svn: 25117
2006-01-06 08:43:03 +08:00
def X86_COND_NS : PatLeaf<(i8 12)>;
X86_COND_C and X86_COND_NC are alternate mnemonics for X86_COND_B and X86_COND_AE, respectively. llvm-svn: 61835
2009-01-07 08:15:08 +08:00
def X86_COND_O : PatLeaf<(i8 13)>;
def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
def X86_COND_S : PatLeaf<(i8 15)>;
* Fast call support. * FP cmp, setcc, etc. llvm-svn: 25117
2006-01-06 08:43:03 +08:00
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
// Predicate used to help when pattern matching LZCNT/TZCNT.
def X86_COND_E_OR_NE : ImmLeaf<i8, [{
return (Imm == X86::COND_E) || (Imm == X86::COND_NE);
}]>;
Add a new bit that ImmLeaf's can opt into, which allows them to duck out of the generated FastISel. X86 doesn't need to generate code to match ADD16ri8 since ADD16ri will do just fine. This is a small codesize win in the generated instruction selector. llvm-svn: 129692
2011-04-18 14:36:55 +08:00
let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
This should always be signed chars, so use int8_t. This fixes a miscompile when llvm is built with unsigned chars where an immediate such as 0xff would be zero extended to 64-bits, turning "cmp $0xff,%eax" into "cmp $0xffffffffffffffff,%eax". llvm-svn: 129845
2011-04-20 11:19:42 +08:00
def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
Add a new bit that ImmLeaf's can opt into, which allows them to duck out of the generated FastISel. X86 doesn't need to generate code to match ADD16ri8 since ADD16ri will do just fine. This is a small codesize win in the generated instruction selector. llvm-svn: 129692
2011-04-18 14:36:55 +08:00
}
switch the rest of the x86 immediate patterns over to ImmLeaf, simplifying them and exposing more information to tblgen. It would be nice if other target authors adopted this as well, particularly arm since it has fastisel. llvm-svn: 129676
2011-04-18 06:12:55 +08:00
def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
add more patterns, patch by Evan Cheng. llvm-svn: 24406
2005-11-18 09:04:42 +08:00
now that predicates have a decent abstraction layer on them, introduce a new kind of predicate: one that is specific to imm nodes. The predicate function specified here just checks an int64_t directly instead of messing around with SDNode's. The virtue of this is that it means that fastisel and other things can reason about these predicates. llvm-svn: 129675
2011-04-18 06:05:17 +08:00
switch the rest of the x86 immediate patterns over to ImmLeaf, simplifying them and exposing more information to tblgen. It would be nice if other target authors adopted this as well, particularly arm since it has fastisel. llvm-svn: 129676
2011-04-18 06:12:55 +08:00
// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
// unsigned field.
def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
now that predicates have a decent abstraction layer on them, introduce a new kind of predicate: one that is specific to imm nodes. The predicate function specified here just checks an int64_t directly instead of messing around with SDNode's. The virtue of this is that it means that fastisel and other things can reason about these predicates. llvm-svn: 129675
2011-04-18 06:05:17 +08:00
switch the rest of the x86 immediate patterns over to ImmLeaf, simplifying them and exposing more information to tblgen. It would be nice if other target authors adopted this as well, particularly arm since it has fastisel. llvm-svn: 129676
2011-04-18 06:12:55 +08:00
def i64immZExt32SExt8 : ImmLeaf<i64, [{
return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
Fix PR8365 by adding a more specialized Pat that checks if an 'and' with 8 bit constants can be used. llvm-svn: 116403
2010-10-13 21:31:20 +08:00
}]>;
A few helper fragments for loads. e.g. (i8 (load addr:$src)) -> (loadi8 addr:$src). Only to improve readibility. llvm-svn: 24688
2005-12-13 09:57:51 +08:00
// Helper fragments for loads.
- Fix the pasto in the fix for a previous pasto. - Incorporate Chris' comment suggestion. llvm-svn: 51061
2008-05-14 02:59:59 +08:00
// It's always safe to treat a anyext i16 load as a i32 load if the i16 is
// known to be 32-bit aligned or better. Ditto for i8 to i16.
Now that predicates can be composed, simplify several of the predicates by extending simple predicates to create more complex predicates instead of duplicating the logic for the simple predicates. This doesn't reduce much redundancy in DAGISelEmitter.cpp's generated source yet; that will require improvements to DAGISelEmitter.cpp's instruction sorting, to make it more effectively group nodes with similar predicates together. llvm-svn: 57565
2008-10-15 14:50:19 +08:00
def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
Tablegen generated code already tests the opcode value, so it's not necessary to use dyn_cast in these predicates. llvm-svn: 55055
2008-08-20 23:24:22 +08:00
LoadSDNode *LD = cast<LoadSDNode>(N);
ISD::LoadExtType ExtType = LD->getExtensionType();
if (ExtType == ISD::NON_EXTLOAD)
return true;
if (ExtType == ISD::EXTLOAD)
return LD->getAlignment() >= 2 && !LD->isVolatile();
On x86, it's safe to treat i32 load anyext as a normal i32 load. Ditto for i8 anyext load to i16. llvm-svn: 51019
2008-05-13 08:54:02 +08:00
return false;
}]>;
factor the 'in the default address space' check out to a single 'dsload' pattern. tblgen doesn't check patterns to see if they're textually identical. This allows better factoring. llvm-svn: 97630
2010-03-03 09:52:59 +08:00
def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
Fix patterns for SSE4.1 move and sign extend instructions. Also add instructions which fold VZEXT_MOVL and VZEXT_LOAD. llvm-svn: 56594
2008-09-25 07:27:55 +08:00
LoadSDNode *LD = cast<LoadSDNode>(N);
ISD::LoadExtType ExtType = LD->getExtensionType();
if (ExtType == ISD::EXTLOAD)
return LD->getAlignment() >= 2 && !LD->isVolatile();
return false;
}]>;
Now that predicates can be composed, simplify several of the predicates by extending simple predicates to create more complex predicates instead of duplicating the logic for the simple predicates. This doesn't reduce much redundancy in DAGISelEmitter.cpp's generated source yet; that will require improvements to DAGISelEmitter.cpp's instruction sorting, to make it more effectively group nodes with similar predicates together. llvm-svn: 57565
2008-10-15 14:50:19 +08:00
def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
Tablegen generated code already tests the opcode value, so it's not necessary to use dyn_cast in these predicates. llvm-svn: 55055
2008-08-20 23:24:22 +08:00
LoadSDNode *LD = cast<LoadSDNode>(N);
ISD::LoadExtType ExtType = LD->getExtensionType();
if (ExtType == ISD::NON_EXTLOAD)
return true;
if (ExtType == ISD::EXTLOAD)
return LD->getAlignment() >= 4 && !LD->isVolatile();
On x86, it's safe to treat i32 load anyext as a normal i32 load. Ditto for i8 anyext load to i16. llvm-svn: 51019
2008-05-13 08:54:02 +08:00
return false;
}]>;
reimplement support for GS and FS relative address space matching by having X86DAGToDAGISel::SelectAddr get passed in the parent node of the operand match (the load/store/atomic op) and having it get the address space from that, instead of having special FS/GS addr mode operations that require duplicating the entire instruction set to support. This makes FS and GS relative accesses *far* more predictable and work much better. It also simplifies the X86 backend a bit, more to come. There is still a pending issue with nodes like ISD::PREFETCH and X86ISD::FLD, which really should be MemSDNode's but aren't. llvm-svn: 114491
2010-09-22 06:07:31 +08:00
def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
Added sext and zext patterns. llvm-svn: 24705
2005-12-14 10:22:27 +08:00
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes. llvm-svn: 30844
2006-10-10 04:57:25 +08:00
def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
move various pattern matching support goop out of X86Instr64Bit, to live with the 32-bit stuff. llvm-svn: 115602
2010-10-05 14:37:31 +08:00
def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes. llvm-svn: 30844
2006-10-10 04:57:25 +08:00
def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
move various pattern matching support goop out of X86Instr64Bit, to live with the 32-bit stuff. llvm-svn: 115602
2010-10-05 14:37:31 +08:00
def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes. llvm-svn: 30844
2006-10-10 04:57:25 +08:00
def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
move various pattern matching support goop out of X86Instr64Bit, to live with the 32-bit stuff. llvm-svn: 115602
2010-10-05 14:37:31 +08:00
def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
Added separate alias instructions for SSE logical ops that operate on non-packed types. llvm-svn: 26297
2006-02-21 10:24:38 +08:00
Don't fold and's into test instructions if they have multiple uses. This compiles test-nofold.ll into: _test: movl $15, %ecx andl 4(%esp), %ecx testl %ecx, %ecx movl $42, %eax cmove %ecx, %eax ret instead of: _test: movl 4(%esp), %eax movl %eax, %ecx andl $15, %ecx testl $15, %eax movl $42, %eax cmove %ecx, %eax ret llvm-svn: 47330
2008-02-20 01:37:35 +08:00
// An 'and' node with a single use.
def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
Remove -always-fold-and-in-test. llvm-svn: 47871
2008-03-04 08:40:35 +08:00
return N->hasOneUse();
Don't fold and's into test instructions if they have multiple uses. This compiles test-nofold.ll into: _test: movl $15, %ecx andl 4(%esp), %ecx testl %ecx, %ecx movl $42, %eax cmove %ecx, %eax ret instead of: _test: movl 4(%esp), %eax movl %eax, %ecx andl $15, %ecx testl $15, %eax movl $42, %eax cmove %ecx, %eax ret llvm-svn: 47330
2008-02-20 01:37:35 +08:00
}]>;
Implement x86 h-register extract support. - Add patterns for h-register extract, which avoids a shift and mask, and in some cases a temporary register. - Add address-mode matching for turning (X>>(8-n))&(255<<n), where n is a valid address-mode scale value, into an h-register extract and a scaled-offset address. - Replace X86's MOV32to32_ and related instructions with the new target-independent COPY_TO_SUBREG instruction. On x86-64 there are complicated constraints on h registers, and CodeGen doesn't currently provide a high-level way to express all of them, so they are handled with a bunch of special code. This code currently only supports extracts where the result is used by a zero-extend or a store, though these are fairly common. These transformations are not always beneficial; since there are only 4 h registers, they sometimes require extra move instructions, and this sometimes increases register pressure because it can force out values that would otherwise be in one of those registers. However, this appears to be relatively uncommon. llvm-svn: 68962
2009-04-14 00:09:41 +08:00
// An 'srl' node with a single use.
def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
return N->hasOneUse();
}]>;
// An 'trunc' node with a single use.
def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
return N->hasOneUse();
}]>;
Don't fold and's into test instructions if they have multiple uses. This compiles test-nofold.ll into: _test: movl $15, %ecx andl 4(%esp), %ecx testl %ecx, %ecx movl $42, %eax cmove %ecx, %eax ret instead of: _test: movl 4(%esp), %eax movl %eax, %ecx andl $15, %ecx testl $15, %eax movl $42, %eax cmove %ecx, %eax ret llvm-svn: 47330
2008-02-20 01:37:35 +08:00
Add new TableGen instruction definitions llvm-svn: 7537
2003-08-04 05:54:21 +08:00
//===----------------------------------------------------------------------===//
refactor .td files a bit, moving system instructions out to X86InstrSystem.td llvm-svn: 115591
2010-10-05 13:32:15 +08:00
// Instruction list.
Add new TableGen instruction definitions llvm-svn: 7537
2003-08-04 05:54:21 +08:00
//
SSE cmov support. llvm-svn: 25190
2006-01-11 08:33:36 +08:00
// Nop
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 08:46:26 +08:00
let hasSideEffects = 0, SchedRW = [WriteZero] in {
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
Recommit r201059 and r201060 with hopefully a fix for its original failure. Original commits messages: Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code. Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information. llvm-svn: 201065
2014-02-10 14:55:41 +08:00
def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;
Recommit r201059 and r201060 with hopefully a fix for its original failure. Original commits messages: Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code. Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information. llvm-svn: 201065
2014-02-10 14:55:41 +08:00
def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32;
Added a 2+-byte NOP instruction to the Intel tables, for the assembler/disassembler to use. llvm-svn: 76914
2009-07-24 07:39:34 +08:00
}
SSE cmov support. llvm-svn: 25190
2006-01-11 08:33:36 +08:00
Add new TableGen instruction definitions llvm-svn: 7537
2003-08-04 05:54:21 +08:00
Added the ENTER instruction, which sets up a stack frame, to the Intel instruction tables. llvm-svn: 81995
2009-09-16 10:57:13 +08:00
// Constructing a stack frame.
fix rdar://8444631 - encoder crash on 'enter' What a weird instruction. llvm-svn: 114190
2010-09-18 02:02:29 +08:00
def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
Annotate the rest of X86InstrInfo.td with SchedRW lists. llvm-svn: 178048
2013-03-27 02:24:15 +08:00
"enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>;
Added the ENTER instruction, which sets up a stack frame, to the Intel instruction tables. llvm-svn: 81995
2009-09-16 10:57:13 +08:00
Annotate the rest of X86InstrInfo.td with SchedRW lists. llvm-svn: 178048
2013-03-27 02:24:15 +08:00
let SchedRW = [WriteALU] in {
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 08:46:26 +08:00
let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in
This purely mechanical patch gives the "I" tblgen class operand list and asm string operands, and adjusts all users to pass them in instead of using II. llvm-svn: 15624
2004-08-11 04:17:41 +08:00
def LEAVE : I<0xC9, RawFrm,
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
(outs), (ins), "leave", [], IIC_LEAVE>,
[x86] Rename In32BitMode predicate to Not64BitMode That's what it actually means, and with 16-bit support it's going to be a little more relevant since in a few corner cases we may actually want to distinguish between 16-bit and 32-bit mode (for example the bare 'push' aliases to pushw/pushl etc.) Patch by David Woodhouse llvm-svn: 197768
2013-12-20 10:04:49 +08:00
Requires<[Not64BitMode]>;
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-12 03:55:27 +08:00
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 08:46:26 +08:00
let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in
move CMOV_FR32 and friends to InstrCompiler, since they are pseudo instructions. Move POPCNT to InstrSSE since they are SSE4 instructions. llvm-svn: 115603
2010-10-05 14:41:40 +08:00
def LEAVE64 : I<0xC9, RawFrm,
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
(outs), (ins), "leave", [], IIC_LEAVE>,
Requires<[In64BitMode]>;
Annotate the rest of X86InstrInfo.td with SchedRW lists. llvm-svn: 178048
2013-03-27 02:24:15 +08:00
} // SchedRW
move CMOV_FR32 and friends to InstrCompiler, since they are pseudo instructions. Move POPCNT to InstrSSE since they are SSE4 instructions. llvm-svn: 115603
2010-10-05 14:41:40 +08:00
continue moving stuff out to X86InstrSystem.td. Move control flow stuff out to X86InstrControl.td. Move some compiler pseudo instructions and Pat<> patterns out to X86InstrCompiler.td llvm-svn: 115596
2010-10-05 14:04:14 +08:00
//===----------------------------------------------------------------------===//
move CMOV_FR32 and friends to InstrCompiler, since they are pseudo instructions. Move POPCNT to InstrSSE since they are SSE4 instructions. llvm-svn: 115603
2010-10-05 14:41:40 +08:00
// Miscellaneous Instructions.
continue moving stuff out to X86InstrSystem.td. Move control flow stuff out to X86InstrControl.td. Move some compiler pseudo instructions and Pat<> patterns out to X86InstrCompiler.td llvm-svn: 115596
2010-10-05 14:04:14 +08:00
//
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 08:46:26 +08:00
let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in {
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
let mayLoad = 1, SchedRW = [WriteLoad] in {
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
IIC_POP_REG16>, OpSize16;
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
IIC_POP_REG>, OpSize16;
X86: POP*rmm: move address operand to (ins) from (outs). llvm-svn: 185292
2013-07-01 04:44:50 +08:00
def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [],
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
IIC_POP_MEM>, OpSize16;
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
X86: POP*rmm: move address operand to (ins) from (outs). llvm-svn: 185292
2013-07-01 04:44:50 +08:00
def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [],
Add a bunch of OpSize32 tags to 64-bit mode only instructions to match their 32-bit mode counterparts for cases where there is also a OpSize16 instruction. llvm-svn: 201550
2014-02-18 16:18:29 +08:00
IIC_POP_MEM>, OpSize32, Requires<[Not64BitMode]>;
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
} // mayLoad, SchedRW
Add new TableGen instruction definitions llvm-svn: 7537
2003-08-04 05:54:21 +08:00
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
let mayStore = 1, SchedRW = [WriteStore] in {
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
IIC_PUSH_REG>, OpSize16;
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
IIC_PUSH_REG>, OpSize16;
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
IIC_PUSH_MEM>, OpSize16;
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>;
Implemented correct stack probing on mingw/cygwin for dynamic alloca's. Also, fixed static case in presence of eax livin. This fixes PR331 PS: Why don't we still have push/pop instructions? :) llvm-svn: 36195
2007-04-17 17:20:00 +08:00
[x86] Do not relax PUSHi16 to PUSHi32 (PR18414) They do *different* things to %esp, so they are not equivalent. Rename PUSHi8 to PUSH32i8 and add the missing PUSH16i8. llvm-svn: 198761
2014-01-08 20:58:32 +08:00
def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
[x86] Do not relax PUSHi16 to PUSHi32 (PR18414) They do *different* things to %esp, so they are not equivalent. Rename PUSHi8 to PUSH32i8 and add the missing PUSH16i8. llvm-svn: 198761
2014-01-08 20:58:32 +08:00
Requires<[Not64BitMode]>;
def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
[x86] Add OpSize16 to instructions that need it This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. llvm-svn: 198752
2014-01-08 20:57:40 +08:00
Requires<[Not64BitMode]>;
Fix Whitespace. llvm-svn: 116972
2010-10-21 07:40:27 +08:00
def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack. llvm-svn: 198547
2014-01-05 13:46:38 +08:00
Requires<[Not64BitMode]>;
Fix Whitespace. llvm-svn: 116972
2010-10-21 07:40:27 +08:00
def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
[x86] Add OpSize16 to instructions that need it This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. llvm-svn: 198752
2014-01-08 20:57:40 +08:00
Requires<[Not64BitMode]>;
x86-32: PUSHF/POPF use/def EFLAGS Summary: As a side-quest for D6629 jvoung pointed out that I should use -verify-machineinstrs and this found a bug in x86-32's handling of EFLAGS for PUSHF/POPF. This patch fixes the use/def, and adds -verify-machineinstrs to all x86 tests which contain 'EFLAGS'. One exception: this patch leaves inline-asm-fpstack.ll as-is because it fails -verify-machineinstrs in a way unrelated to EFLAGS. This patch also modifies cmpxchg-clobber-flags.ll along the lines of what D6629 already does by also testing i386. Test Plan: ninja check Reviewers: t.p.northover, jvoung Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6687 llvm-svn: 224359
2014-12-17 04:15:45 +08:00
} // mayStore, SchedRW
}
Fix Whitespace. llvm-svn: 116972
2010-10-21 07:40:27 +08:00
x86-32: PUSHF/POPF use/def EFLAGS Summary: As a side-quest for D6629 jvoung pointed out that I should use -verify-machineinstrs and this found a bug in x86-32's handling of EFLAGS for PUSHF/POPF. This patch fixes the use/def, and adds -verify-machineinstrs to all x86 tests which contain 'EFLAGS'. One exception: this patch leaves inline-asm-fpstack.ll as-is because it fails -verify-machineinstrs in a way unrelated to EFLAGS. This patch also modifies cmpxchg-clobber-flags.ll along the lines of what D6629 already does by also testing i386. Test Plan: ninja check Reviewers: t.p.northover, jvoung Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6687 llvm-svn: 224359
2014-12-17 04:15:45 +08:00
let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
SchedRW = [WriteLoad] in {
def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>,
OpSize16;
def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
OpSize32, Requires<[Not64BitMode]>;
}
let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, hasSideEffects=0,
SchedRW = [WriteStore] in {
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize16;
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize32, Requires<[Not64BitMode]>;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
}
Add pushf{d|q}, popf{d|q} to push and pop EFLAGS register. llvm-svn: 42335
2007-09-26 09:29:06 +08:00
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 08:46:26 +08:00
let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in {
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
let mayLoad = 1, SchedRW = [WriteLoad] in {
Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test. llvm-svn: 198530
2014-01-05 09:35:51 +08:00
def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
Add a bunch of OpSize32 tags to 64-bit mode only instructions to match their 32-bit mode counterparts for cases where there is also a OpSize16 instruction. llvm-svn: 201550
2014-02-18 16:18:29 +08:00
IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
Add a bunch of OpSize32 tags to 64-bit mode only instructions to match their 32-bit mode counterparts for cases where there is also a OpSize16 instruction. llvm-svn: 201550
2014-02-18 16:18:29 +08:00
IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
X86: POP*rmm: move address operand to (ins) from (outs). llvm-svn: 185292
2013-07-01 04:44:50 +08:00
def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [],
Add a bunch of OpSize32 tags to 64-bit mode only instructions to match their 32-bit mode counterparts for cases where there is also a OpSize16 instruction. llvm-svn: 201550
2014-02-18 16:18:29 +08:00
IIC_POP_MEM>, OpSize32, Requires<[In64BitMode]>;
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
} // mayLoad, SchedRW
let mayStore = 1, SchedRW = [WriteStore] in {
Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test. llvm-svn: 198530
2014-01-05 09:35:51 +08:00
def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
Add a bunch of OpSize32 tags to 64-bit mode only instructions to match their 32-bit mode counterparts for cases where there is also a OpSize16 instruction. llvm-svn: 201550
2014-02-18 16:18:29 +08:00
IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
Add a bunch of OpSize32 tags to 64-bit mode only instructions to match their 32-bit mode counterparts for cases where there is also a OpSize16 instruction. llvm-svn: 201550
2014-02-18 16:18:29 +08:00
IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
Add a bunch of OpSize32 tags to 64-bit mode only instructions to match their 32-bit mode counterparts for cases where there is also a OpSize16 instruction. llvm-svn: 201550
2014-02-18 16:18:29 +08:00
IIC_PUSH_MEM>, OpSize32, Requires<[In64BitMode]>;
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
} // mayStore, SchedRW
move some instructions from Instr64Bit -> InstrInfo. bswap32 doesn't read eflags. llvm-svn: 115604
2010-10-05 14:47:35 +08:00
}
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 08:46:26 +08:00
let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1,
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
SchedRW = [WriteStore] in {
Changed the X86 PUSH64i8 record to use the i64i8imm ParserMatchClass so that a push with a small constant produces a 2-byte push. llvm-svn: 134501
2011-07-07 01:23:46 +08:00
def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test. llvm-svn: 198530
2014-01-05 09:35:51 +08:00
"push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
Fix Whitespace. llvm-svn: 116972
2010-10-21 07:40:27 +08:00
def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack. llvm-svn: 198547
2014-01-05 13:46:38 +08:00
Requires<[In64BitMode]>;
[x86] Fix signed relocations for i64i32imm operands These should end up (in ELF) as R_X86_64_32S relocs, not R_X86_64_32. Kill the horrid and incomplete special case and FIXME in EncodeInstruction() and set things up so it can infer the signedness from the ImmType just like it can the size and whether it's PC-relative. llvm-svn: 200495
2014-01-31 06:20:41 +08:00
def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
Add a bunch of OpSize32 tags to 64-bit mode only instructions to match their 32-bit mode counterparts for cases where there is also a OpSize16 instruction. llvm-svn: 201550
2014-02-18 16:18:29 +08:00
"push{q}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
Requires<[In64BitMode]>;
move some instructions from Instr64Bit -> InstrInfo. bswap32 doesn't read eflags. llvm-svn: 115604
2010-10-05 14:47:35 +08:00
}
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 08:46:26 +08:00
let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
Add a bunch of OpSize32 tags to 64-bit mode only instructions to match their 32-bit mode counterparts for cases where there is also a OpSize16 instruction. llvm-svn: 201550
2014-02-18 16:18:29 +08:00
OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>;
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 08:46:26 +08:00
let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, hasSideEffects=0 in
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
Add a bunch of OpSize32 tags to 64-bit mode only instructions to match their 32-bit mode counterparts for cases where there is also a OpSize16 instruction. llvm-svn: 201550
2014-02-18 16:18:29 +08:00
OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>;
move some instructions from Instr64Bit -> InstrInfo. bswap32 doesn't read eflags. llvm-svn: 115604
2010-10-05 14:47:35 +08:00
Add support for the x86 instructions "pusha" and "popa". llvm-svn: 106671
2010-06-24 04:00:58 +08:00
let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 08:46:26 +08:00
mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in {
[x86] Add PUSHA16,POPA16 instructions, and fix aliases for 16-bit mode llvm-svn: 198753
2014-01-08 20:57:45 +08:00
def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize32, Requires<[Not64BitMode]>;
[x86] Add PUSHA16,POPA16 instructions, and fix aliases for 16-bit mode llvm-svn: 198753
2014-01-08 20:57:45 +08:00
def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize16, Requires<[Not64BitMode]>;
Add support for the x86 instructions "pusha" and "popa". llvm-svn: 106671
2010-06-24 04:00:58 +08:00
}
let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 08:46:26 +08:00
mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
[x86] Add PUSHA16,POPA16 instructions, and fix aliases for 16-bit mode llvm-svn: 198753
2014-01-08 20:57:45 +08:00
def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize32, Requires<[Not64BitMode]>;
[x86] Add PUSHA16,POPA16 instructions, and fix aliases for 16-bit mode llvm-svn: 198753
2014-01-08 20:57:45 +08:00
def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize16, Requires<[Not64BitMode]>;
Add support for the x86 instructions "pusha" and "popa". llvm-svn: 106671
2010-06-24 04:00:58 +08:00
}
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
// GR32 = bswap GR32
move sign and zero extensions out to their own file. llvm-svn: 115605
2010-10-05 14:52:26 +08:00
def BSWAP32r : I<0xC8, AddRegFrm,
(outs GR32:$dst), (ins GR32:$src),
Fix Whitespace. llvm-svn: 116972
2010-10-21 07:40:27 +08:00
"bswap{l}\t$dst",
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
[(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize32, TB;
Fix Whitespace. llvm-svn: 116972
2010-10-21 07:40:27 +08:00
move some instructions from Instr64Bit -> InstrInfo. bswap32 doesn't read eflags. llvm-svn: 115604
2010-10-05 14:47:35 +08:00
def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
Fix Whitespace. llvm-svn: 116972
2010-10-21 07:40:27 +08:00
"bswap{q}\t$dst",
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
[(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
} // Constraints = "$src = $dst", SchedRW
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-04 04:35:00 +08:00
Implement ctlz and cttz with bsr and bsf. llvm-svn: 45024
2007-12-14 10:13:44 +08:00
// Bit scan instructions.
let Defs = [EFLAGS] in {
Fix bsf / bsr jit encoding. llvm-svn: 45037
2007-12-15 02:49:43 +08:00
def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
Fix Intel asm syntax for the bsr and bsf instructions. llvm-svn: 45030
2007-12-14 23:10:00 +08:00
"bsf{w}\t{$src, $dst|$dst, $src}",
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
[(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
2014-02-18 08:21:49 +08:00
IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
Implement ctlz and cttz with bsr and bsf. llvm-svn: 45024
2007-12-14 10:13:44 +08:00
def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
Fix Intel asm syntax for the bsr and bsf instructions. llvm-svn: 45030
2007-12-14 23:10:00 +08:00
"bsf{w}\t{$src, $dst|$dst, $src}",
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
[(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
2014-02-18 08:21:49 +08:00
IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
Fix bsf / bsr jit encoding. llvm-svn: 45037
2007-12-15 02:49:43 +08:00
def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
Fix Intel asm syntax for the bsr and bsf instructions. llvm-svn: 45030
2007-12-14 23:10:00 +08:00
"bsf{l}\t{$src, $dst|$dst, $src}",
Adds support for Atom Silvermont (SLM) - -march=slm Implements Instruction scheduler latencies for Silvermont, using latencies from the Intel Silvermont Optimization Guide. Auto detects SLM. Turns on post RA scheduler when generating code for SLM. llvm-svn: 190717
2013-09-14 03:23:28 +08:00
[(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))],
Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
2014-02-18 08:21:49 +08:00
IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
Implement ctlz and cttz with bsr and bsf. llvm-svn: 45024
2007-12-14 10:13:44 +08:00
def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
Fix Intel asm syntax for the bsr and bsf instructions. llvm-svn: 45030
2007-12-14 23:10:00 +08:00
"bsf{l}\t{$src, $dst|$dst, $src}",
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
[(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
2014-02-18 08:21:49 +08:00
IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
move some instructions from Instr64Bit -> InstrInfo. bswap32 doesn't read eflags. llvm-svn: 115604
2010-10-05 14:47:35 +08:00
def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
"bsf{q}\t{$src, $dst|$dst, $src}",
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
[(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
2014-02-18 08:21:49 +08:00
IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
move some instructions from Instr64Bit -> InstrInfo. bswap32 doesn't read eflags. llvm-svn: 115604
2010-10-05 14:47:35 +08:00
def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
"bsf{q}\t{$src, $dst|$dst, $src}",
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
[(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
2014-02-18 08:21:49 +08:00
IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
Implement ctlz and cttz with bsr and bsf. llvm-svn: 45024
2007-12-14 10:13:44 +08:00
Fix bsf / bsr jit encoding. llvm-svn: 45037
2007-12-15 02:49:43 +08:00
def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
Fix Intel asm syntax for the bsr and bsf instructions. llvm-svn: 45030
2007-12-14 23:10:00 +08:00
"bsr{w}\t{$src, $dst|$dst, $src}",
Adds support for Atom Silvermont (SLM) - -march=slm Implements Instruction scheduler latencies for Silvermont, using latencies from the Intel Silvermont Optimization Guide. Auto detects SLM. Turns on post RA scheduler when generating code for SLM. llvm-svn: 190717
2013-09-14 03:23:28 +08:00
[(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))],
Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
2014-02-18 08:21:49 +08:00
IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
Implement ctlz and cttz with bsr and bsf. llvm-svn: 45024
2007-12-14 10:13:44 +08:00
def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
Fix Intel asm syntax for the bsr and bsf instructions. llvm-svn: 45030
2007-12-14 23:10:00 +08:00
"bsr{w}\t{$src, $dst|$dst, $src}",
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
[(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
2014-02-18 08:21:49 +08:00
IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
Fix bsf / bsr jit encoding. llvm-svn: 45037
2007-12-15 02:49:43 +08:00
def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
Fix Intel asm syntax for the bsr and bsf instructions. llvm-svn: 45030
2007-12-14 23:10:00 +08:00
"bsr{l}\t{$src, $dst|$dst, $src}",
Adds support for Atom Silvermont (SLM) - -march=slm Implements Instruction scheduler latencies for Silvermont, using latencies from the Intel Silvermont Optimization Guide. Auto detects SLM. Turns on post RA scheduler when generating code for SLM. llvm-svn: 190717
2013-09-14 03:23:28 +08:00
[(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))],
Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
2014-02-18 08:21:49 +08:00
IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
Implement ctlz and cttz with bsr and bsf. llvm-svn: 45024
2007-12-14 10:13:44 +08:00
def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
Fix Intel asm syntax for the bsr and bsf instructions. llvm-svn: 45030
2007-12-14 23:10:00 +08:00
"bsr{l}\t{$src, $dst|$dst, $src}",
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
[(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
2014-02-18 08:21:49 +08:00
IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
move some instructions from Instr64Bit -> InstrInfo. bswap32 doesn't read eflags. llvm-svn: 115604
2010-10-05 14:47:35 +08:00
def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
"bsr{q}\t{$src, $dst|$dst, $src}",
Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
2014-02-18 08:21:49 +08:00
[(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))],
IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
move some instructions from Instr64Bit -> InstrInfo. bswap32 doesn't read eflags. llvm-svn: 115604
2010-10-05 14:47:35 +08:00
def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
"bsr{q}\t{$src, $dst|$dst, $src}",
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
[(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
2014-02-18 08:21:49 +08:00
IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
Implement ctlz and cttz with bsr and bsf. llvm-svn: 45024
2007-12-14 10:13:44 +08:00
} // Defs = [EFLAGS]
Annotate the rest of X86InstrInfo.td with SchedRW lists. llvm-svn: 178048
2013-03-27 02:24:15 +08:00
let SchedRW = [WriteMicrocoded] in {
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. llvm-svn: 95252
2010-02-04 05:04:42 +08:00
// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
[x86] Allow segment and address-size overrides for MOVS[BWLQ] (PR9385) llvm-svn: 199807
2014-01-22 23:08:42 +08:00
def MOVSB : I<0xA4, RawFrmDstSrc, (outs dstidx8:$dst), (ins srcidx8:$src),
"movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
def MOVSW : I<0xA5, RawFrmDstSrc, (outs dstidx16:$dst), (ins srcidx16:$src),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"movsw\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize16;
[x86] Allow segment and address-size overrides for MOVS[BWLQ] (PR9385) llvm-svn: 199807
2014-01-22 23:08:42 +08:00
def MOVSL : I<0xA5, RawFrmDstSrc, (outs dstidx32:$dst), (ins srcidx32:$src),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"movs{l|d}\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize32;
[x86] Allow segment and address-size overrides for MOVS[BWLQ] (PR9385) llvm-svn: 199807
2014-01-22 23:08:42 +08:00
def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs dstidx64:$dst), (ins srcidx64:$src),
"movsq\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. llvm-svn: 95252
2010-02-04 05:04:42 +08:00
}
// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
[x86] Allow address-size overrides for STOS[BWLQ] (PR9385) llvm-svn: 199804
2014-01-22 23:08:21 +08:00
def STOSB : I<0xAA, RawFrmDst, (outs dstidx8:$dst), (ins),
"stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>;
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. llvm-svn: 95252
2010-02-04 05:04:42 +08:00
let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
[x86] Allow address-size overrides for STOS[BWLQ] (PR9385) llvm-svn: 199804
2014-01-22 23:08:21 +08:00
def STOSW : I<0xAB, RawFrmDst, (outs dstidx16:$dst), (ins),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize16;
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. llvm-svn: 95252
2010-02-04 05:04:42 +08:00
let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
[x86] Allow address-size overrides for STOS[BWLQ] (PR9385) llvm-svn: 199804
2014-01-22 23:08:21 +08:00
def STOSL : I<0xAB, RawFrmDst, (outs dstidx32:$dst), (ins),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize32;
move string pseudo instructions to InstrCompiler consolidate 64-bit and 32-bit together. llvm-svn: 115600
2010-10-05 14:27:48 +08:00
let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
[x86] Allow address-size overrides for STOS[BWLQ] (PR9385) llvm-svn: 199804
2014-01-22 23:08:21 +08:00
def STOSQ : RI<0xAB, RawFrmDst, (outs dstidx64:$dst), (ins),
"stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>;
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. llvm-svn: 95252
2010-02-04 05:04:42 +08:00
[X86] Fix Uses/Defs lists for INS, OUTS, SCAS, CMPS, LODS llvm-svn: 202348
2014-02-27 13:08:25 +08:00
// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
let Defs = [EDI,EFLAGS], Uses = [AL,EDI,EFLAGS] in
def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst),
[x86] Allow address-size overrides for SCAS{8,16,32,64} (PR9385) llvm-svn: 199805
2014-01-22 23:08:27 +08:00
"scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>;
[X86] Fix Uses/Defs lists for INS, OUTS, SCAS, CMPS, LODS llvm-svn: 202348
2014-02-27 13:08:25 +08:00
let Defs = [EDI,EFLAGS], Uses = [AX,EDI,EFLAGS] in
def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst),
"scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize16;
let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,EFLAGS] in
def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst),
"scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize32;
let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,EFLAGS] in
def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst),
"scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>;
// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,EFLAGS] in {
def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src),
]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385) llvm-svn: 199806
2014-01-22 23:08:36 +08:00
"cmpsb\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
[X86] Fix Uses/Defs lists for INS, OUTS, SCAS, CMPS, LODS llvm-svn: 202348
2014-02-27 13:08:25 +08:00
def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src),
"cmpsw\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize16;
def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src),
"cmps{l|d}\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize32;
def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src),
"cmpsq\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
}
Annotate the rest of X86InstrInfo.td with SchedRW lists. llvm-svn: 178048
2013-03-27 02:24:15 +08:00
} // SchedRW
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
Add new TableGen instruction definitions llvm-svn: 7537
2003-08-04 05:54:21 +08:00
//===----------------------------------------------------------------------===//
refactor .td files a bit, moving system instructions out to X86InstrSystem.td llvm-svn: 115591
2010-10-05 13:32:15 +08:00
// Move Instructions.
Add new TableGen instruction definitions llvm-svn: 7537
2003-08-04 05:54:21 +08:00
//
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
let SchedRW = [WriteMove] in {
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 08:46:26 +08:00
let hasSideEffects = 0 in {
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 09:14:50 +08:00
def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 09:14:50 +08:00
def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 09:14:50 +08:00
def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
distribute the rest of the contents of X86Instr64bit.td out to the right places. X86Instr64bit.td now dies, long live x86-64! llvm-svn: 115669
2010-10-06 04:49:15 +08:00
def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
Start inferring side effect information more aggressively, and fix many bugs in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. llvm-svn: 45829
2008-01-10 15:59:24 +08:00
}
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
XOR32rr, etc. are not AsCheapAsMove, but MOV32ri, etc. are. llvm-svn: 52454
2008-06-18 16:13:07 +08:00
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 09:14:50 +08:00
def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-08-01 04:11:57 +08:00
"mov{b}\t{$src, $dst|$dst, $src}",
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
[(set GR8:$dst, imm:$src)], IIC_MOV>;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 09:14:50 +08:00
def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-08-01 04:11:57 +08:00
"mov{w}\t{$src, $dst|$dst, $src}",
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
[(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize16;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 09:14:50 +08:00
def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-08-01 04:11:57 +08:00
"mov{l}\t{$src, $dst|$dst, $src}",
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
[(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize32;
[x86] Fix signed relocations for i64i32imm operands These should end up (in ELF) as R_X86_64_32S relocs, not R_X86_64_32. Kill the horrid and incomplete special case and FIXME in EncodeInstruction() and set things up so it can infer the signedness from the ImmType just like it can the size and whether it's PC-relative. llvm-svn: 200495
2014-01-31 06:20:41 +08:00
def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
"mov{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
Revert the earlier change that removed the M_REMATERIALIZABLE machine instruction flag, and use the flag along with a virtual member function hook for targets to override if there are instructions that are only trivially rematerializable with specific operands (i.e. constant pool loads). llvm-svn: 37728
2007-06-26 08:48:07 +08:00
}
[X86] Don't mark movabsq as cheap-as-move - it isn't that cheap. A simple register copy on X86 is just 3 bytes, whereas movabsq is a 10 byte instruction. Marking movabsq as not beeing cheap will allow LICM to move it out of the loop and it also prevents unnecessary rematerializations if the value is needed in more than one register. llvm-svn: 201377
2014-02-14 08:51:13 +08:00
let isReMaterializable = 1 in {
def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
"movabs{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, imm:$src)], IIC_MOV>;
}
Add opcode extension forms of MOV8ri/MOV16ri/MOV32ri. llvm-svn: 201463
2014-02-15 15:29:18 +08:00
// Longer forms that use a ModR/M byte. Needed for disassembler
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src),
"mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src),
"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src),
"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
}
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
} // SchedRW
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. llvm-svn: 95252
2010-02-04 05:04:42 +08:00
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
let SchedRW = [WriteStore] in {
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 09:14:50 +08:00
def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-08-01 04:11:57 +08:00
"mov{b}\t{$src, $dst|$dst, $src}",
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
[(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 09:14:50 +08:00
def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-08-01 04:11:57 +08:00
"mov{w}\t{$src, $dst|$dst, $src}",
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
[(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 09:14:50 +08:00
def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-08-01 04:11:57 +08:00
"mov{l}\t{$src, $dst|$dst, $src}",
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
[(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize32;
[x86] Fix signed relocations for i64i32imm operands These should end up (in ELF) as R_X86_64_32S relocs, not R_X86_64_32. Kill the horrid and incomplete special case and FIXME in EncodeInstruction() and set things up so it can infer the signedness from the ImmType just like it can the size and whether it's PC-relative. llvm-svn: 200495
2014-01-31 06:20:41 +08:00
def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
"mov{q}\t{$src, $dst|$dst, $src}",
[(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
} // SchedRW
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-04 04:35:00 +08:00
Add hasSideEffects/mayLoad/mayStore flags to the X86 moffs8/moffs16/moffs32/moffs64 versions of move. llvm-svn: 189182
2013-08-25 04:31:14 +08:00
let hasSideEffects = 0 in {
reapply r103668 with a fix. Never make "minor syntax changes" after testing before committing. llvm-svn: 103681
2010-05-13 08:02:47 +08:00
/// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
[x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand It seems there is no separate instruction class for having AdSize *and* OpSize bits set, which is required in order to disambiguate between all these instructions. So add that to the disassembler. Hm, perhaps we do need an AdSize16 bit after all? llvm-svn: 198759
2014-01-08 20:58:24 +08:00
/// 32-bit offset from the segment base. These are only valid in x86-32 mode.
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
let SchedRW = [WriteALU] in {
Add hasSideEffects/mayLoad/mayStore flags to the X86 moffs8/moffs16/moffs32/moffs64 versions of move. llvm-svn: 189182
2013-08-25 04:31:14 +08:00
let mayLoad = 1 in {
[X86] Add RAX/EAX/AX/AL Uses/Defs to the absolute memory location move instructions. Patch by Florian Lukas with some additional instructions fixed by me. Fixes PR18975. llvm-svn: 202345
2014-02-27 12:07:57 +08:00
let Defs = [AL] in
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
2014-01-16 15:36:58 +08:00
def MOV8o8a : Ii32 <0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax. Patch by Richard Mitton. llvm-svn: 187476
2013-07-31 10:47:52 +08:00
"mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
[x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand It seems there is no separate instruction class for having AdSize *and* OpSize bits set, which is required in order to disambiguate between all these instructions. So add that to the disassembler. Hm, perhaps we do need an AdSize16 bit after all? llvm-svn: 198759
2014-01-08 20:58:24 +08:00
Requires<[In32BitMode]>;
[X86] Add RAX/EAX/AX/AL Uses/Defs to the absolute memory location move instructions. Patch by Florian Lukas with some additional instructions fixed by me. Fixes PR18975. llvm-svn: 202345
2014-02-27 12:07:57 +08:00
let Defs = [AX] in
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
2014-01-16 15:36:58 +08:00
def MOV16o16a : Ii32 <0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
OpSize16, Requires<[In32BitMode]>;
[X86] Add RAX/EAX/AX/AL Uses/Defs to the absolute memory location move instructions. Patch by Florian Lukas with some additional instructions fixed by me. Fixes PR18975. llvm-svn: 202345
2014-02-27 12:07:57 +08:00
let Defs = [EAX] in
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
2014-01-16 15:36:58 +08:00
def MOV32o32a : Ii32 <0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax. Patch by Richard Mitton. llvm-svn: 187476
2013-07-31 10:47:52 +08:00
"mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize32, Requires<[In32BitMode]>;
[x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand It seems there is no separate instruction class for having AdSize *and* OpSize bits set, which is required in order to disambiguate between all these instructions. So add that to the disassembler. Hm, perhaps we do need an AdSize16 bit after all? llvm-svn: 198759
2014-01-08 20:58:24 +08:00
[X86] Add RAX/EAX/AX/AL Uses/Defs to the absolute memory location move instructions. Patch by Florian Lukas with some additional instructions fixed by me. Fixes PR18975. llvm-svn: 202345
2014-02-27 12:07:57 +08:00
let Defs = [AL] in
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
2014-01-16 15:36:58 +08:00
def MOV8o8a_16 : Ii16 <0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
[x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand It seems there is no separate instruction class for having AdSize *and* OpSize bits set, which is required in order to disambiguate between all these instructions. So add that to the disassembler. Hm, perhaps we do need an AdSize16 bit after all? llvm-svn: 198759
2014-01-08 20:58:24 +08:00
"mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
AdSize, Requires<[In16BitMode]>;
[X86] Add RAX/EAX/AX/AL Uses/Defs to the absolute memory location move instructions. Patch by Florian Lukas with some additional instructions fixed by me. Fixes PR18975. llvm-svn: 202345
2014-02-27 12:07:57 +08:00
let Defs = [AX] in
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
2014-01-16 15:36:58 +08:00
def MOV16o16a_16 : Ii16 <0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
OpSize16, AdSize, Requires<[In16BitMode]>;
[X86] Add RAX/EAX/AX/AL Uses/Defs to the absolute memory location move instructions. Patch by Florian Lukas with some additional instructions fixed by me. Fixes PR18975. llvm-svn: 202345
2014-02-27 12:07:57 +08:00
let Defs = [EAX] in
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
2014-01-16 15:36:58 +08:00
def MOV32o32a_16 : Ii16 <0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
[x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand It seems there is no separate instruction class for having AdSize *and* OpSize bits set, which is required in order to disambiguate between all these instructions. So add that to the disassembler. Hm, perhaps we do need an AdSize16 bit after all? llvm-svn: 198759
2014-01-08 20:58:24 +08:00
"mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
AdSize, OpSize32, Requires<[In16BitMode]>;
Add hasSideEffects/mayLoad/mayStore flags to the X86 moffs8/moffs16/moffs32/moffs64 versions of move. llvm-svn: 189182
2013-08-25 04:31:14 +08:00
}
let mayStore = 1 in {
[X86] Add RAX/EAX/AX/AL Uses/Defs to the absolute memory location move instructions. Patch by Florian Lukas with some additional instructions fixed by me. Fixes PR18975. llvm-svn: 202345
2014-02-27 12:07:57 +08:00
let Uses = [AL] in
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
2014-01-16 15:36:58 +08:00
def MOV8ao8 : Ii32 <0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax. Patch by Richard Mitton. llvm-svn: 187476
2013-07-31 10:47:52 +08:00
"mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>,
[x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand It seems there is no separate instruction class for having AdSize *and* OpSize bits set, which is required in order to disambiguate between all these instructions. So add that to the disassembler. Hm, perhaps we do need an AdSize16 bit after all? llvm-svn: 198759
2014-01-08 20:58:24 +08:00
Requires<[In32BitMode]>;
[X86] Add RAX/EAX/AX/AL Uses/Defs to the absolute memory location move instructions. Patch by Florian Lukas with some additional instructions fixed by me. Fixes PR18975. llvm-svn: 202345
2014-02-27 12:07:57 +08:00
let Uses = [AX] in
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
2014-01-16 15:36:58 +08:00
def MOV16ao16 : Ii32 <0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
OpSize16, Requires<[In32BitMode]>;
[X86] Add RAX/EAX/AX/AL Uses/Defs to the absolute memory location move instructions. Patch by Florian Lukas with some additional instructions fixed by me. Fixes PR18975. llvm-svn: 202345
2014-02-27 12:07:57 +08:00
let Uses = [EAX] in
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
2014-01-16 15:36:58 +08:00
def MOV32ao32 : Ii32 <0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax. Patch by Richard Mitton. llvm-svn: 187476
2013-07-31 10:47:52 +08:00
"mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize32, Requires<[In32BitMode]>;
[x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand It seems there is no separate instruction class for having AdSize *and* OpSize bits set, which is required in order to disambiguate between all these instructions. So add that to the disassembler. Hm, perhaps we do need an AdSize16 bit after all? llvm-svn: 198759
2014-01-08 20:58:24 +08:00
[X86] Add RAX/EAX/AX/AL Uses/Defs to the absolute memory location move instructions. Patch by Florian Lukas with some additional instructions fixed by me. Fixes PR18975. llvm-svn: 202345
2014-02-27 12:07:57 +08:00
let Uses = [AL] in
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
2014-01-16 15:36:58 +08:00
def MOV8ao8_16 : Ii16 <0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
[x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand It seems there is no separate instruction class for having AdSize *and* OpSize bits set, which is required in order to disambiguate between all these instructions. So add that to the disassembler. Hm, perhaps we do need an AdSize16 bit after all? llvm-svn: 198759
2014-01-08 20:58:24 +08:00
"mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>,
AdSize, Requires<[In16BitMode]>;
[X86] Add RAX/EAX/AX/AL Uses/Defs to the absolute memory location move instructions. Patch by Florian Lukas with some additional instructions fixed by me. Fixes PR18975. llvm-svn: 202345
2014-02-27 12:07:57 +08:00
let Uses = [AX] in
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
2014-01-16 15:36:58 +08:00
def MOV16ao16_16 : Ii16 <0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
OpSize16, AdSize, Requires<[In16BitMode]>;
[X86] Add RAX/EAX/AX/AL Uses/Defs to the absolute memory location move instructions. Patch by Florian Lukas with some additional instructions fixed by me. Fixes PR18975. llvm-svn: 202345
2014-02-27 12:07:57 +08:00
let Uses = [EAX] in
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
2014-01-16 15:36:58 +08:00
def MOV32ao32_16 : Ii16 <0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
[x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand It seems there is no separate instruction class for having AdSize *and* OpSize bits set, which is required in order to disambiguate between all these instructions. So add that to the disassembler. Hm, perhaps we do need an AdSize16 bit after all? llvm-svn: 198759
2014-01-08 20:58:24 +08:00
"mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize32, AdSize, Requires<[In16BitMode]>;
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
}
Add hasSideEffects/mayLoad/mayStore flags to the X86 moffs8/moffs16/moffs32/moffs64 versions of move. llvm-svn: 189182
2013-08-25 04:31:14 +08:00
}
Fix Whitespace. llvm-svn: 116972
2010-10-21 07:40:27 +08:00
Fix the move to/from accumulator register instructions that use a full 64-bit absolute address encoded in the instruction. rdar://8612627 and rdar://14299221 llvm-svn: 186878
2013-07-23 05:25:31 +08:00
// These forms all have full 64-bit absolute addresses in their instructions
// and use the movabs mnemonic to indicate this specific form.
Add hasSideEffects/mayLoad/mayStore flags to the X86 moffs8/moffs16/moffs32/moffs64 versions of move. llvm-svn: 189182
2013-08-25 04:31:14 +08:00
let mayLoad = 1 in {
[X86] Add RAX/EAX/AX/AL Uses/Defs to the absolute memory location move instructions. Patch by Florian Lukas with some additional instructions fixed by me. Fixes PR18975. llvm-svn: 202345
2014-02-27 12:07:57 +08:00
let Defs = [AL] in
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
2014-01-16 15:36:58 +08:00
def MOV64o8a : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax. Patch by Richard Mitton. llvm-svn: 187476
2013-07-31 10:47:52 +08:00
"movabs{b}\t{$src, %al|al, $src}", []>,
Fix the move to/from accumulator register instructions that use a full 64-bit absolute address encoded in the instruction. rdar://8612627 and rdar://14299221 llvm-svn: 186878
2013-07-23 05:25:31 +08:00
Requires<[In64BitMode]>;
[X86] Add RAX/EAX/AX/AL Uses/Defs to the absolute memory location move instructions. Patch by Florian Lukas with some additional instructions fixed by me. Fixes PR18975. llvm-svn: 202345
2014-02-27 12:07:57 +08:00
let Defs = [AX] in
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
2014-01-16 15:36:58 +08:00
def MOV64o16a : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16,
Fix the move to/from accumulator register instructions that use a full 64-bit absolute address encoded in the instruction. rdar://8612627 and rdar://14299221 llvm-svn: 186878
2013-07-23 05:25:31 +08:00
Requires<[In64BitMode]>;
[X86] Add RAX/EAX/AX/AL Uses/Defs to the absolute memory location move instructions. Patch by Florian Lukas with some additional instructions fixed by me. Fixes PR18975. llvm-svn: 202345
2014-02-27 12:07:57 +08:00
let Defs = [EAX] in
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
2014-01-16 15:36:58 +08:00
def MOV64o32a : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32,
Fix the move to/from accumulator register instructions that use a full 64-bit absolute address encoded in the instruction. rdar://8612627 and rdar://14299221 llvm-svn: 186878
2013-07-23 05:25:31 +08:00
Requires<[In64BitMode]>;
[X86] Add RAX/EAX/AX/AL Uses/Defs to the absolute memory location move instructions. Patch by Florian Lukas with some additional instructions fixed by me. Fixes PR18975. llvm-svn: 202345
2014-02-27 12:07:57 +08:00
let Defs = [RAX] in
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
2014-01-16 15:36:58 +08:00
def MOV64o64a : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64:$src),
Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax. Patch by Richard Mitton. llvm-svn: 187476
2013-07-31 10:47:52 +08:00
"movabs{q}\t{$src, %rax|rax, $src}", []>,
Fix the move to/from accumulator register instructions that use a full 64-bit absolute address encoded in the instruction. rdar://8612627 and rdar://14299221 llvm-svn: 186878
2013-07-23 05:25:31 +08:00
Requires<[In64BitMode]>;
Add hasSideEffects/mayLoad/mayStore flags to the X86 moffs8/moffs16/moffs32/moffs64 versions of move. llvm-svn: 189182
2013-08-25 04:31:14 +08:00
}
Fix the move to/from accumulator register instructions that use a full 64-bit absolute address encoded in the instruction. rdar://8612627 and rdar://14299221 llvm-svn: 186878
2013-07-23 05:25:31 +08:00
Add hasSideEffects/mayLoad/mayStore flags to the X86 moffs8/moffs16/moffs32/moffs64 versions of move. llvm-svn: 189182
2013-08-25 04:31:14 +08:00
let mayStore = 1 in {
[X86] Add RAX/EAX/AX/AL Uses/Defs to the absolute memory location move instructions. Patch by Florian Lukas with some additional instructions fixed by me. Fixes PR18975. llvm-svn: 202345
2014-02-27 12:07:57 +08:00
let Uses = [AL] in
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
2014-01-16 15:36:58 +08:00
def MOV64ao8 : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax. Patch by Richard Mitton. llvm-svn: 187476
2013-07-31 10:47:52 +08:00
"movabs{b}\t{%al, $dst|$dst, al}", []>,
Fix the move to/from accumulator register instructions that use a full 64-bit absolute address encoded in the instruction. rdar://8612627 and rdar://14299221 llvm-svn: 186878
2013-07-23 05:25:31 +08:00
Requires<[In64BitMode]>;
[X86] Add RAX/EAX/AX/AL Uses/Defs to the absolute memory location move instructions. Patch by Florian Lukas with some additional instructions fixed by me. Fixes PR18975. llvm-svn: 202345
2014-02-27 12:07:57 +08:00
let Uses = [AX] in
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
2014-01-16 15:36:58 +08:00
def MOV64ao16 : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16,
Fix the move to/from accumulator register instructions that use a full 64-bit absolute address encoded in the instruction. rdar://8612627 and rdar://14299221 llvm-svn: 186878
2013-07-23 05:25:31 +08:00
Requires<[In64BitMode]>;
[X86] Add RAX/EAX/AX/AL Uses/Defs to the absolute memory location move instructions. Patch by Florian Lukas with some additional instructions fixed by me. Fixes PR18975. llvm-svn: 202345
2014-02-27 12:07:57 +08:00
let Uses = [EAX] in
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
2014-01-16 15:36:58 +08:00
def MOV64ao32 : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32,
Fix the move to/from accumulator register instructions that use a full 64-bit absolute address encoded in the instruction. rdar://8612627 and rdar://14299221 llvm-svn: 186878
2013-07-23 05:25:31 +08:00
Requires<[In64BitMode]>;
[X86] Add RAX/EAX/AX/AL Uses/Defs to the absolute memory location move instructions. Patch by Florian Lukas with some additional instructions fixed by me. Fixes PR18975. llvm-svn: 202345
2014-02-27 12:07:57 +08:00
let Uses = [RAX] in
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
2014-01-16 15:36:58 +08:00
def MOV64ao64 : RIi64<0xA3, RawFrmMemOffs, (outs offset64:$dst), (ins),
Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax. Patch by Richard Mitton. llvm-svn: 187476
2013-07-31 10:47:52 +08:00
"movabs{q}\t{%rax, $dst|$dst, rax}", []>,
Fix the move to/from accumulator register instructions that use a full 64-bit absolute address encoded in the instruction. rdar://8612627 and rdar://14299221 llvm-svn: 186878
2013-07-23 05:25:31 +08:00
Requires<[In64BitMode]>;
Add hasSideEffects/mayLoad/mayStore flags to the X86 moffs8/moffs16/moffs32/moffs64 versions of move. llvm-svn: 189182
2013-08-25 04:31:14 +08:00
}
} // hasSideEffects = 0
Added a new register class for segment registers to the Intel register table. Added 16- and 64-bit MOVs to and from the segment registers to the Intel instruction tables. llvm-svn: 81895
2009-09-16 02:47:29 +08:00
Add a new x86 specific instruction flag to force some isCodeGenOnly instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions. llvm-svn: 198543
2014-01-05 12:17:28 +08:00
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
SchedRW = [WriteMove] in {
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
distribute the rest of the contents of X86Instr64bit.td out to the right places. X86Instr64bit.td now dies, long live x86-64! llvm-svn: 115669
2010-10-06 04:49:15 +08:00
def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
AsmMatcher/X86: Mark _REV instructions as "code gen only", they aren't expected to be matched. llvm-svn: 104757
2010-05-27 06:21:28 +08:00
}
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 09:14:50 +08:00
def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-08-01 04:11:57 +08:00
"mov{b}\t{$src, $dst|$dst, $src}",
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
[(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 09:14:50 +08:00
def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-08-01 04:11:57 +08:00
"mov{w}\t{$src, $dst|$dst, $src}",
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
[(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize16;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 09:14:50 +08:00
def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-08-01 04:11:57 +08:00
"mov{l}\t{$src, $dst|$dst, $src}",
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
[(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32;
distribute the rest of the contents of X86Instr64bit.td out to the right places. X86Instr64bit.td now dies, long live x86-64! llvm-svn: 115669
2010-10-06 04:49:15 +08:00
def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
"mov{q}\t{$src, $dst|$dst, $src}",
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
[(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
Mark load instructions with isLoad = 1. llvm-svn: 41595
2007-08-30 13:49:43 +08:00
}
Add support to the instruction patterns for AT&T style output, which will hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
2004-10-04 04:35:00 +08:00
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
let SchedRW = [WriteStore] in {
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 09:14:50 +08:00
def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-08-01 04:11:57 +08:00
"mov{b}\t{$src, $dst|$dst, $src}",
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
[(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 09:14:50 +08:00
def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-08-01 04:11:57 +08:00
"mov{w}\t{$src, $dst|$dst, $src}",
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
[(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16;
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 09:14:50 +08:00
def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. llvm-svn: 40648
2007-08-01 04:11:57 +08:00
"mov{l}\t{$src, $dst|$dst, $src}",
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
[(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize32;
distribute the rest of the contents of X86Instr64bit.td out to the right places. X86Instr64bit.td now dies, long live x86-64! llvm-svn: 115669
2010-10-06 04:49:15 +08:00
def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
"mov{q}\t{$src, $dst|$dst, $src}",
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
[(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
} // SchedRW
Implement x86 h-register extract support. - Add patterns for h-register extract, which avoids a shift and mask, and in some cases a temporary register. - Add address-mode matching for turning (X>>(8-n))&(255<<n), where n is a valid address-mode scale value, into an h-register extract and a scaled-offset address. - Replace X86's MOV32to32_ and related instructions with the new target-independent COPY_TO_SUBREG instruction. On x86-64 there are complicated constraints on h registers, and CodeGen doesn't currently provide a high-level way to express all of them, so they are handled with a bunch of special code. This code currently only supports extracts where the result is used by a zero-extend or a store, though these are fairly common. These transformations are not always beneficial; since there are only 4 h registers, they sometimes require extra move instructions, and this sometimes increases register pressure because it can force out values that would otherwise be in one of those registers. However, this appears to be relatively uncommon. llvm-svn: 68962
2009-04-14 00:09:41 +08:00
Rename GR8_ABCD to GR8_ABCD_L and create GR8_ABCD_H, and use these to precisely describe the h-register subreg register classes. Thanks to Jakob Stoklund Olesen for spotting this and for the initial patch! Also, make getStoreRegOpcode and getLoadRegOpcode aware of the needs of h registers. llvm-svn: 70211
2009-04-28 00:41:36 +08:00
// Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
// that they can be used for copying and storing h registers, which can't be
// encoded when a REX prefix is present.
X86: Mark MOV.*_{TC,NOREX} instruction as code gen only, they aren't real. llvm-svn: 108680
2010-07-19 14:14:49 +08:00
let isCodeGenOnly = 1 in {
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 08:46:26 +08:00
let hasSideEffects = 0 in
Fix 80-column violations. llvm-svn: 69204
2009-04-16 03:48:57 +08:00
def MOV8rr_NOREX : I<0x88, MRMDestReg,
(outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
"mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>,
Sched<[WriteMove]>;
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 08:46:26 +08:00
let mayStore = 1, hasSideEffects = 0 in
Add a new MOV8rr_NOREX, and make X86's copyRegToReg use it when either the source or destination is a physical h register. This fixes sqlite3 with the post-RA scheduler enabled. llvm-svn: 69111
2009-04-15 08:04:23 +08:00
def MOV8mr_NOREX : I<0x88, MRMDestMem,
(outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
IIC_MOV_MEM>, Sched<[WriteStore]>;
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 08:46:26 +08:00
let mayLoad = 1, hasSideEffects = 0,
The mayHaveSideEffects flag is no longer used. llvm-svn: 97348
2010-02-28 07:47:46 +08:00
canFoldAsLoad = 1, isReMaterializable = 1 in
Rename GR8_ABCD to GR8_ABCD_L and create GR8_ABCD_H, and use these to precisely describe the h-register subreg register classes. Thanks to Jakob Stoklund Olesen for spotting this and for the initial patch! Also, make getStoreRegOpcode and getLoadRegOpcode aware of the needs of h registers. llvm-svn: 70211
2009-04-28 00:41:36 +08:00
def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
(outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
IIC_MOV_MEM>, Sched<[WriteLoad]>;
X86: Mark MOV.*_{TC,NOREX} instruction as code gen only, they aren't real. llvm-svn: 108680
2010-07-19 14:14:49 +08:00
}
Implement x86 h-register extract support. - Add patterns for h-register extract, which avoids a shift and mask, and in some cases a temporary register. - Add address-mode matching for turning (X>>(8-n))&(255<<n), where n is a valid address-mode scale value, into an h-register extract and a scaled-offset address. - Replace X86's MOV32to32_ and related instructions with the new target-independent COPY_TO_SUBREG instruction. On x86-64 there are complicated constraints on h registers, and CodeGen doesn't currently provide a high-level way to express all of them, so they are handled with a bunch of special code. This code currently only supports extracts where the result is used by a zero-extend or a store, though these are fairly common. These transformations are not always beneficial; since there are only 4 h registers, they sometimes require extra move instructions, and this sometimes increases register pressure because it can force out values that would otherwise be in one of those registers. However, this appears to be relatively uncommon. llvm-svn: 68962
2009-04-14 00:09:41 +08:00
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 09:57:46 +08:00
Each instruction now has both an ImmType and a MemType. This describes the size of the immediate and the memory operand on instructions that use them. This resolves problems with instructions that take both a memory and an immediate operand but their sizes differ (i.e. ADDmi32b). llvm-svn: 11967
2004-02-29 06:02:05 +08:00
// Condition code ops, incl. set if equal/not equal/...
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
let SchedRW = [WriteALU] in {
X86: Don't emit conditional floating point moves on when targeting pre-pentiumpro architectures. * Model FPSW (the FPU status word) as a register. * Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions. * During Legalize/Lowering, build a node sequence to transfer the comparison result from FPSW into EFLAGS. If you're wondering about the right-shift: That's an implicit sub-register extraction (%ax -> %ah) which is handled later on by the instruction selector. Fixes PR6679. Patch by Christoph Erhardt! llvm-svn: 155704
2012-04-27 20:07:43 +08:00
let Defs = [EFLAGS], Uses = [AH] in
def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
[(set EFLAGS, (X86sahf AH))], IIC_AHF>;
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 08:46:26 +08:00
let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
IIC_AHF>; // AH = flags
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
} // SchedRW
MC/X86: Rename alternate spellings of CMP{8,16,32} and mark as "code gen only" so they don't get selected by the asm matcher. llvm-svn: 98097
2010-03-10 06:50:40 +08:00
distribute the rest of the contents of X86Instr64bit.td out to the right places. X86Instr64bit.td now dies, long live x86-64! llvm-svn: 115669
2010-10-06 04:49:15 +08:00
//===----------------------------------------------------------------------===//
// Bit tests instructions: BT, BTS, BTR, BTC.
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 09:57:46 +08:00
Add instruction patterns and encodings for the x86 bt instructions. llvm-svn: 61400
2008-12-24 06:45:23 +08:00
let Defs = [EFLAGS] in {
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
let SchedRW = [WriteALU] in {
Fix a few more JIT encoding issues in the BT instructions. llvm-svn: 62179
2009-01-14 04:32:45 +08:00
def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
Add instruction patterns and encodings for the x86 bt instructions. llvm-svn: 61400
2008-12-24 06:45:23 +08:00
"bt{w}\t{$src2, $src1|$src1, $src2}",
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
[(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize16, TB;
Fix a few more JIT encoding issues in the BT instructions. llvm-svn: 62179
2009-01-14 04:32:45 +08:00
def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
Add instruction patterns and encodings for the x86 bt instructions. llvm-svn: 61400
2008-12-24 06:45:23 +08:00
"bt{l}\t{$src2, $src1|$src1, $src2}",
[x86] Add OpSize16 to instructions that need it This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. llvm-svn: 198752
2014-01-08 20:57:40 +08:00
[(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize32, TB;
distribute the rest of the contents of X86Instr64bit.td out to the right places. X86Instr64bit.td now dies, long live x86-64! llvm-svn: 115669
2010-10-06 04:49:15 +08:00
def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
"bt{q}\t{$src2, $src1|$src1, $src2}",
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
[(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
} // SchedRW
Disable the register+memory forms of the bt instructions for now. Thanks to Eli for pointing out that these forms don't ignore the high bits of their index operands, and as such are not immediately suitable for use by isel. llvm-svn: 62194
2009-01-14 07:23:30 +08:00
// Unlike with the register+register form, the memory+register form of the
// bt instruction does not ignore the high bits of the index. From ISel's
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
// perspective, this is pretty bizarre. Make these instructions disassembly
// only for now.
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in {
Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them. llvm-svn: 171128
2012-12-27 10:01:33 +08:00
def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
"bt{w}\t{$src2, $src1|$src1, $src2}",
// [(X86bt (loadi16 addr:$src1), GR16:$src2),
// (implicit EFLAGS)]
[], IIC_BT_MR
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
>, OpSize16, TB, Requires<[FastBTMem]>;
Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them. llvm-svn: 171128
2012-12-27 10:01:33 +08:00
def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
"bt{l}\t{$src2, $src1|$src1, $src2}",
// [(X86bt (loadi32 addr:$src1), GR32:$src2),
// (implicit EFLAGS)]
[], IIC_BT_MR
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
>, OpSize32, TB, Requires<[FastBTMem]>;
Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them. llvm-svn: 171128
2012-12-27 10:01:33 +08:00
def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
"bt{q}\t{$src2, $src1|$src1, $src2}",
// [(X86bt (loadi64 addr:$src1), GR64:$src2),
// (implicit EFLAGS)]
[], IIC_BT_MR
>, TB;
}
Add bt instructions that take immediate operands. llvm-svn: 62180
2009-01-14 04:33:23 +08:00
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
let SchedRW = [WriteALU] in {
Add bt instructions that take immediate operands. llvm-svn: 62180
2009-01-14 04:33:23 +08:00
def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
"bt{w}\t{$src2, $src1|$src1, $src2}",
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
[(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
IIC_BT_RI>, OpSize16, TB;
Add bt instructions that take immediate operands. llvm-svn: 62180
2009-01-14 04:33:23 +08:00
def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
"bt{l}\t{$src2, $src1|$src1, $src2}",
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
[(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
IIC_BT_RI>, OpSize32, TB;
distribute the rest of the contents of X86Instr64bit.td out to the right places. X86Instr64bit.td now dies, long live x86-64! llvm-svn: 115669
2010-10-06 04:49:15 +08:00
def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
"bt{q}\t{$src2, $src1|$src1, $src2}",
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
[(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
IIC_BT_RI>, TB;
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
} // SchedRW
distribute the rest of the contents of X86Instr64bit.td out to the right places. X86Instr64bit.td now dies, long live x86-64! llvm-svn: 115669
2010-10-06 04:49:15 +08:00
Add bt instructions that take immediate operands. llvm-svn: 62180
2009-01-14 04:33:23 +08:00
// Note that these instructions don't need FastBTMem because that
// only applies when the other operand is in a register. When it's
// an immediate, bt is still fast.
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
let SchedRW = [WriteALU] in {
Add bt instructions that take immediate operands. llvm-svn: 62180
2009-01-14 04:33:23 +08:00
def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
"bt{w}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 08:01:11 +08:00
[(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
], IIC_BT_MI>, OpSize16, TB;
Add bt instructions that take immediate operands. llvm-svn: 62180
2009-01-14 04:33:23 +08:00
def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
"bt{l}\t{$src2, $src1|$src1, $src2}",
Now that tblgen can handle matching implicit defs of instructions to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
2010-03-19 08:01:11 +08:00
[(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
], IIC_BT_MI>, OpSize32, TB;
distribute the rest of the contents of X86Instr64bit.td out to the right places. X86Instr64bit.td now dies, long live x86-64! llvm-svn: 115669
2010-10-06 04:49:15 +08:00
def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
"bt{q}\t{$src2, $src1|$src1, $src2}",
[(set EFLAGS, (X86bt (loadi64 addr:$src1),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
i64immSExt8:$src2))], IIC_BT_MI>, TB;
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
} // SchedRW
distribute the rest of the contents of X86Instr64bit.td out to the right places. X86Instr64bit.td now dies, long live x86-64! llvm-svn: 115669
2010-10-06 04:49:15 +08:00
Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them. llvm-svn: 171128
2012-12-27 10:01:33 +08:00
let hasSideEffects = 0 in {
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
let SchedRW = [WriteALU] in {
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize16, TB;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
[x86] Add OpSize16 to instructions that need it This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. llvm-svn: 198752
2014-01-08 20:57:40 +08:00
"btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize32, TB;
distribute the rest of the contents of X86Instr64bit.td out to the right places. X86Instr64bit.td now dies, long live x86-64! llvm-svn: 115669
2010-10-06 04:49:15 +08:00
def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
} // SchedRW
Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them. llvm-svn: 171128
2012-12-27 10:01:33 +08:00
Annotate the rest of X86InstrInfo.td with SchedRW lists. llvm-svn: 178048
2013-03-27 02:24:15 +08:00
let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize16, TB;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
[x86] Add OpSize16 to instructions that need it This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. llvm-svn: 198752
2014-01-08 20:57:40 +08:00
"btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize32, TB;
distribute the rest of the contents of X86Instr64bit.td out to the right places. X86Instr64bit.td now dies, long live x86-64! llvm-svn: 115669
2010-10-06 04:49:15 +08:00
def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them. llvm-svn: 171128
2012-12-27 10:01:33 +08:00
}
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
let SchedRW = [WriteALU] in {
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize16, TB;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
[x86] Add OpSize16 to instructions that need it This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. llvm-svn: 198752
2014-01-08 20:57:40 +08:00
"btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize32, TB;
distribute the rest of the contents of X86Instr64bit.td out to the right places. X86Instr64bit.td now dies, long live x86-64! llvm-svn: 115669
2010-10-06 04:49:15 +08:00
def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
} // SchedRW
Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them. llvm-svn: 171128
2012-12-27 10:01:33 +08:00
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize16, TB;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
[x86] Add OpSize16 to instructions that need it This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. llvm-svn: 198752
2014-01-08 20:57:40 +08:00
"btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize32, TB;
distribute the rest of the contents of X86Instr64bit.td out to the right places. X86Instr64bit.td now dies, long live x86-64! llvm-svn: 115669
2010-10-06 04:49:15 +08:00
def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them. llvm-svn: 171128
2012-12-27 10:01:33 +08:00
}
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
let SchedRW = [WriteALU] in {
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize16, TB;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
[x86] Add OpSize16 to instructions that need it This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. llvm-svn: 198752
2014-01-08 20:57:40 +08:00
"btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize32, TB;
distribute the rest of the contents of X86Instr64bit.td out to the right places. X86Instr64bit.td now dies, long live x86-64! llvm-svn: 115669
2010-10-06 04:49:15 +08:00
def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
"btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
} // SchedRW
Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them. llvm-svn: 171128
2012-12-27 10:01:33 +08:00
Annotate the rest of X86InstrInfo.td with SchedRW lists. llvm-svn: 178048
2013-03-27 02:24:15 +08:00
let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize16, TB;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
[x86] Add OpSize16 to instructions that need it This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. llvm-svn: 198752
2014-01-08 20:57:40 +08:00
"btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize32, TB;
distribute the rest of the contents of X86Instr64bit.td out to the right places. X86Instr64bit.td now dies, long live x86-64! llvm-svn: 115669
2010-10-06 04:49:15 +08:00
def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them. llvm-svn: 171128
2012-12-27 10:01:33 +08:00
}
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
let SchedRW = [WriteALU] in {
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize16, TB;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
[x86] Add OpSize16 to instructions that need it This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. llvm-svn: 198752
2014-01-08 20:57:40 +08:00
"btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize32, TB;
distribute the rest of the contents of X86Instr64bit.td out to the right places. X86Instr64bit.td now dies, long live x86-64! llvm-svn: 115669
2010-10-06 04:49:15 +08:00
def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
} // SchedRW
Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them. llvm-svn: 171128
2012-12-27 10:01:33 +08:00
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize16, TB;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
[x86] Add OpSize16 to instructions that need it This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. llvm-svn: 198752
2014-01-08 20:57:40 +08:00
"btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize32, TB;
distribute the rest of the contents of X86Instr64bit.td out to the right places. X86Instr64bit.td now dies, long live x86-64! llvm-svn: 115669
2010-10-06 04:49:15 +08:00
def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them. llvm-svn: 171128
2012-12-27 10:01:33 +08:00
}
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
let SchedRW = [WriteALU] in {
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize16, TB;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
[x86] Add OpSize16 to instructions that need it This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. llvm-svn: 198752
2014-01-08 20:57:40 +08:00
"bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize32, TB;
distribute the rest of the contents of X86Instr64bit.td out to the right places. X86Instr64bit.td now dies, long live x86-64! llvm-svn: 115669
2010-10-06 04:49:15 +08:00
def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
} // SchedRW
Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them. llvm-svn: 171128
2012-12-27 10:01:33 +08:00
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
OpSize16, TB;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
OpSize32, TB;
distribute the rest of the contents of X86Instr64bit.td out to the right places. X86Instr64bit.td now dies, long live x86-64! llvm-svn: 115669
2010-10-06 04:49:15 +08:00
def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them. llvm-svn: 171128
2012-12-27 10:01:33 +08:00
}
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
let SchedRW = [WriteALU] in {
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize16, TB;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
[x86] Add OpSize16 to instructions that need it This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. llvm-svn: 198752
2014-01-08 20:57:40 +08:00
"bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize32, TB;
distribute the rest of the contents of X86Instr64bit.td out to the right places. X86Instr64bit.td now dies, long live x86-64! llvm-svn: 115669
2010-10-06 04:49:15 +08:00
def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
} // SchedRW
Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them. llvm-svn: 171128
2012-12-27 10:01:33 +08:00
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize16, TB;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
[x86] Add OpSize16 to instructions that need it This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. llvm-svn: 198752
2014-01-08 20:57:40 +08:00
"bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize32, TB;
distribute the rest of the contents of X86Instr64bit.td out to the right places. X86Instr64bit.td now dies, long live x86-64! llvm-svn: 115669
2010-10-06 04:49:15 +08:00
def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them. llvm-svn: 171128
2012-12-27 10:01:33 +08:00
}
} // hasSideEffects = 0
Add instruction patterns and encodings for the x86 bt instructions. llvm-svn: 61400
2008-12-24 06:45:23 +08:00
} // Defs = [EFLAGS]
Long live the exception handling! This patch fills the last necessary bits to enable exceptions handling in LLVM. Currently only on x86-32/linux. In fact, this patch adds necessary intrinsics (and their lowering) which represent really weird target-specific gcc builtins used inside unwinder. After corresponding llvm-gcc patch will land (easy) exceptions should be more or less workable. However, exceptions handling support should not be thought as 'finished': I expect many small and not so small glitches everywhere. llvm-svn: 39855
2007-07-14 22:06:15 +08:00
Atomic op support. If any gcc test uses __sync builtins, it might start failing on archs that haven't implemented them yet llvm-svn: 47430
2008-02-21 14:45:13 +08:00
//===----------------------------------------------------------------------===//
// Atomic support
//
Add lock prefix support to x86. Also add the instructions necessary for the atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode. llvm-svn: 47795
2008-03-01 21:37:02 +08:00
xchg which references a memory operand does not need to lock prefix. Atomicity is guaranteed. llvm-svn: 49946
2008-04-19 09:20:30 +08:00
// Atomic swap. These are just normal xchg instructions. But since a memory
// operand is referenced, the atomicity is ensured.
Revise td of X86 atomic instructions - Rewirte most atomic instructions in templates for both better maintenance and future extensions, such as HLE in TSX. llvm-svn: 164357
2012-09-21 11:00:17 +08:00
multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
InstrItinClass itin> {
Annotate the rest of X86InstrInfo.td with SchedRW lists. llvm-svn: 178048
2013-03-27 02:24:15 +08:00
let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in {
Remove # from the beginning and end of def names. llvm-svn: 171696
2013-01-07 13:26:58 +08:00
def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst),
(ins GR8:$val, i8mem:$ptr),
!strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
[(set
GR8:$dst,
(!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
itin>;
def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst),
(ins GR16:$val, i16mem:$ptr),
!strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
[(set
GR16:$dst,
(!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
itin>, OpSize16;
Remove # from the beginning and end of def names. llvm-svn: 171696
2013-01-07 13:26:58 +08:00
def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),
(ins GR32:$val, i32mem:$ptr),
!strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
[(set
GR32:$dst,
(!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
itin>, OpSize32;
Remove # from the beginning and end of def names. llvm-svn: 171696
2013-01-07 13:26:58 +08:00
def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
(ins GR64:$val, i64mem:$ptr),
!strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
Revise td of X86 atomic instructions - Rewirte most atomic instructions in templates for both better maintenance and future extensions, such as HLE in TSX. llvm-svn: 164357
2012-09-21 11:00:17 +08:00
[(set
Remove # from the beginning and end of def names. llvm-svn: 171696
2013-01-07 13:26:58 +08:00
GR64:$dst,
(!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
Revise td of X86 atomic instructions - Rewirte most atomic instructions in templates for both better maintenance and future extensions, such as HLE in TSX. llvm-svn: 164357
2012-09-21 11:00:17 +08:00
itin>;
}
}
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
Revise td of X86 atomic instructions - Rewirte most atomic instructions in templates for both better maintenance and future extensions, such as HLE in TSX. llvm-svn: 164357
2012-09-21 11:00:17 +08:00
defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
// Swap between registers.
Annotate the rest of X86InstrInfo.td with SchedRW lists. llvm-svn: 178048
2013-03-27 02:24:15 +08:00
let SchedRW = [WriteALU] in {
Revise td of X86 atomic instructions - Rewirte most atomic instructions in templates for both better maintenance and future extensions, such as HLE in TSX. llvm-svn: 164357
2012-09-21 11:00:17 +08:00
let Constraints = "$val = $dst" in {
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
move the atomic pseudo instructions out to X86InstrCompiler.td llvm-svn: 115599
2010-10-05 14:22:35 +08:00
def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
OpSize16;
move the atomic pseudo instructions out to X86InstrCompiler.td llvm-svn: 115599
2010-10-05 14:22:35 +08:00
def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
[x86] Add OpSize16 to instructions that need it This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. llvm-svn: 198752
2014-01-08 20:57:40 +08:00
"xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize32;
move the atomic pseudo instructions out to X86InstrCompiler.td llvm-svn: 115599
2010-10-05 14:22:35 +08:00
def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
xchg which references a memory operand does not need to lock prefix. Atomicity is guaranteed. llvm-svn: 49946
2008-04-19 09:20:30 +08:00
}
Revise td of X86 atomic instructions - Rewirte most atomic instructions in templates for both better maintenance and future extensions, such as HLE in TSX. llvm-svn: 164357
2012-09-21 11:00:17 +08:00
// Swap between EAX and other registers.
[X86] Add RAX/EAX/AX Uses/Defs to XCHG RAX/EAX/AX instructions. llvm-svn: 202347
2014-02-27 12:27:00 +08:00
let Uses = [AX], Defs = [AX] in
Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. llvm-svn: 141353
2011-10-07 13:35:38 +08:00
def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize16;
[X86] Add RAX/EAX/AX Uses/Defs to XCHG RAX/EAX/AX instructions. llvm-svn: 202347
2014-02-27 12:27:00 +08:00
let Uses = [EAX], Defs = [EAX] in
Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. llvm-svn: 141353
2011-10-07 13:35:38 +08:00
def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax. Patch by Richard Mitton. llvm-svn: 187476
2013-07-31 10:47:52 +08:00
"xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize32, Requires<[Not64BitMode]>;
[X86] Add RAX/EAX/AX Uses/Defs to XCHG RAX/EAX/AX instructions. llvm-svn: 202347
2014-02-27 12:27:00 +08:00
let Uses = [EAX], Defs = [EAX] in
Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. llvm-svn: 141353
2011-10-07 13:35:38 +08:00
// Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
// xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax. Patch by Richard Mitton. llvm-svn: 187476
2013-07-31 10:47:52 +08:00
"xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
Add a bunch of OpSize32 tags to 64-bit mode only instructions to match their 32-bit mode counterparts for cases where there is also a OpSize16 instruction. llvm-svn: 201550
2014-02-18 16:18:29 +08:00
OpSize32, Requires<[In64BitMode]>;
[X86] Add RAX/EAX/AX Uses/Defs to XCHG RAX/EAX/AX instructions. llvm-svn: 202347
2014-02-27 12:27:00 +08:00
let Uses = [RAX], Defs = [RAX] in
Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. llvm-svn: 141353
2011-10-07 13:35:38 +08:00
def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax. Patch by Richard Mitton. llvm-svn: 187476
2013-07-31 10:47:52 +08:00
"xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>;
Annotate the rest of X86InstrInfo.td with SchedRW lists. llvm-svn: 178048
2013-03-27 02:24:15 +08:00
} // SchedRW
move the atomic pseudo instructions out to X86InstrCompiler.td llvm-svn: 115599
2010-10-05 14:22:35 +08:00
Annotate the rest of X86InstrInfo.td with SchedRW lists. llvm-svn: 178048
2013-03-27 02:24:15 +08:00
let SchedRW = [WriteALU] in {
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize16;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
[x86] Add OpSize16 to instructions that need it This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. llvm-svn: 198752
2014-01-08 20:57:40 +08:00
"xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize32;
move the atomic pseudo instructions out to X86InstrCompiler.td llvm-svn: 115599
2010-10-05 14:22:35 +08:00
def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
Annotate the rest of X86InstrInfo.td with SchedRW lists. llvm-svn: 178048
2013-03-27 02:24:15 +08:00
} // SchedRW
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
Annotate the rest of X86InstrInfo.td with SchedRW lists. llvm-svn: 178048
2013-03-27 02:24:15 +08:00
let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize16;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
[x86] Add OpSize16 to instructions that need it This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. llvm-svn: 198752
2014-01-08 20:57:40 +08:00
"xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize32;
move the atomic pseudo instructions out to X86InstrCompiler.td llvm-svn: 115599
2010-10-05 14:22:35 +08:00
def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
move the atomic pseudo instructions out to X86InstrCompiler.td llvm-svn: 115599
2010-10-05 14:22:35 +08:00
Add mayLoad and mayStore flags to instructions which missed them. llvm-svn: 103776
2010-05-15 00:34:55 +08:00
}
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
Annotate the rest of X86InstrInfo.td with SchedRW lists. llvm-svn: 178048
2013-03-27 02:24:15 +08:00
let SchedRW = [WriteALU] in {
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
IIC_CMPXCHG_REG8>, TB;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
IIC_CMPXCHG_REG>, TB, OpSize16;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
IIC_CMPXCHG_REG>, TB, OpSize32;
move the atomic pseudo instructions out to X86InstrCompiler.td llvm-svn: 115599
2010-10-05 14:22:35 +08:00
def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
IIC_CMPXCHG_REG>, TB;
Annotate the rest of X86InstrInfo.td with SchedRW lists. llvm-svn: 178048
2013-03-27 02:24:15 +08:00
} // SchedRW
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
Annotate the rest of X86InstrInfo.td with SchedRW lists. llvm-svn: 178048
2013-03-27 02:24:15 +08:00
let SchedRW = [WriteALULd, WriteRMW] in {
Add mayLoad and mayStore flags to instructions which missed them. llvm-svn: 103776
2010-05-15 00:34:55 +08:00
let mayLoad = 1, mayStore = 1 in {
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
IIC_CMPXCHG_MEM8>, TB;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
IIC_CMPXCHG_MEM>, TB, OpSize16;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
IIC_CMPXCHG_MEM>, TB, OpSize32;
move the atomic pseudo instructions out to X86InstrCompiler.td llvm-svn: 115599
2010-10-05 14:22:35 +08:00
def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
IIC_CMPXCHG_MEM>, TB;
Add mayLoad and mayStore flags to instructions which missed them. llvm-svn: 103776
2010-05-15 00:34:55 +08:00
}
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
Fix what looks to me obvious instruction definition bugs. 1. CMPXCHG8B and CMPXCHG16B did not specify implicit physical register defs and uses. 2. LCMPXCHG8B is loading 64 bit memory, not 32 bit. llvm-svn: 92985
2010-01-08 09:29:19 +08:00
let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
move the atomic pseudo instructions out to X86InstrCompiler.td llvm-svn: 115599
2010-10-05 14:22:35 +08:00
let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
TB, Requires<[HasCmpxchg16b]>;
Annotate the rest of X86InstrInfo.td with SchedRW lists. llvm-svn: 178048
2013-03-27 02:24:15 +08:00
} // SchedRW
move the atomic pseudo instructions out to X86InstrCompiler.td llvm-svn: 115599
2010-10-05 14:22:35 +08:00
Handle some 64-bit atomics on x86-32, some of the time. llvm-svn: 56963
2008-10-03 02:53:47 +08:00
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. llvm-svn: 95252
2010-02-04 05:04:42 +08:00
// Lock instruction prefix
def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
Implement the rex64 prefix. llvm-svn: 120017
2010-11-23 19:23:24 +08:00
// Rex64 instruction prefix
Mark REX64_PREFIX as In64BitMode, remove hack from X86RecognizableInstr. llvm-svn: 198336
2014-01-03 03:12:10 +08:00
def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>,
Requires<[In64BitMode]>;
Implement the rex64 prefix. llvm-svn: 120017
2010-11-23 19:23:24 +08:00
Implement the data16 prefix. llvm-svn: 120224
2010-11-28 04:29:45 +08:00
// Data16 instruction prefix
def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. llvm-svn: 95252
2010-02-04 05:04:42 +08:00
// Repeat string operation instruction prefixes
// These uses the DF flag in the EFLAGS register to inc or dec ECX
let Defs = [ECX], Uses = [ECX,EFLAGS] in {
// Repeat (used with INS, OUTS, MOVS, LODS and STOS)
def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
// Repeat while not equal (used with CMPS and SCAS)
def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
}
Added the LODS (load byte into register, usually as part string parsing) instructions to the Intel instruction tables. llvm-svn: 82089
2009-09-17 06:59:28 +08:00
// String manipulation instructions
Annotate the rest of X86InstrInfo.td with SchedRW lists. llvm-svn: 178048
2013-03-27 02:24:15 +08:00
let SchedRW = [WriteMicrocoded] in {
[X86] Fix Uses/Defs lists for INS, OUTS, SCAS, CMPS, LODS llvm-svn: 202348
2014-02-27 13:08:25 +08:00
// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
let Defs = [AL,ESI], Uses = [ESI,EFLAGS] in
[x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385) llvm-svn: 199803
2014-01-22 23:08:08 +08:00
def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src),
"lodsb\t{$src, %al|al, $src}", [], IIC_LODS>;
[X86] Fix Uses/Defs lists for INS, OUTS, SCAS, CMPS, LODS llvm-svn: 202348
2014-02-27 13:08:25 +08:00
let Defs = [AX,ESI], Uses = [ESI,EFLAGS] in
[x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385) llvm-svn: 199803
2014-01-22 23:08:08 +08:00
def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize16;
[X86] Fix Uses/Defs lists for INS, OUTS, SCAS, CMPS, LODS llvm-svn: 202348
2014-02-27 13:08:25 +08:00
let Defs = [EAX,ESI], Uses = [ESI,EFLAGS] in
[x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385) llvm-svn: 199803
2014-01-22 23:08:08 +08:00
def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize32;
[X86] Fix Uses/Defs lists for INS, OUTS, SCAS, CMPS, LODS llvm-svn: 202348
2014-02-27 13:08:25 +08:00
let Defs = [RAX,ESI], Uses = [ESI,EFLAGS] in
[x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385) llvm-svn: 199803
2014-01-22 23:08:08 +08:00
def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src),
"lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>;
Annotate the rest of X86InstrInfo.td with SchedRW lists. llvm-svn: 178048
2013-03-27 02:24:15 +08:00
}
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
Annotate the rest of X86InstrInfo.td with SchedRW lists. llvm-svn: 178048
2013-03-27 02:24:15 +08:00
let SchedRW = [WriteSystem] in {
[X86] Fix Uses/Defs lists for INS, OUTS, SCAS, CMPS, LODS llvm-svn: 202348
2014-02-27 13:08:25 +08:00
// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
let Defs = [ESI], Uses = [DX,ESI,EFLAGS] in {
[x86] Allow segment and address-size overrides for OUTS[BWLQ] (PR9385) llvm-svn: 199808
2014-01-22 23:08:49 +08:00
def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src),
"outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>;
def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"outsw\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize16;
[x86] Allow segment and address-size overrides for OUTS[BWLQ] (PR9385) llvm-svn: 199808
2014-01-22 23:08:49 +08:00
def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize32;
Annotate the rest of X86InstrInfo.td with SchedRW lists. llvm-svn: 178048
2013-03-27 02:24:15 +08:00
}
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
[X86] Fix Uses/Defs lists for INS, OUTS, SCAS, CMPS, LODS llvm-svn: 202348
2014-02-27 13:08:25 +08:00
// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
let Defs = [EDI], Uses = [DX,EDI,EFLAGS] in {
def INSB : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins),
"insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>;
def INSW : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins),
"insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16;
def INSL : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins),
"ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize32;
}
}
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
// Flag instructions
Annotate the rest of X86InstrInfo.td with SchedRW lists. llvm-svn: 178048
2013-03-27 02:24:15 +08:00
let SchedRW = [WriteALU] in {
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
Annotate the rest of X86InstrInfo.td with SchedRW lists. llvm-svn: 178048
2013-03-27 02:24:15 +08:00
}
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
// Table lookup instructions
Annotate the rest of X86InstrInfo.td with SchedRW lists. llvm-svn: 178048
2013-03-27 02:24:15 +08:00
def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>,
Sched<[WriteLoad]>;
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
2009-12-18 08:01:26 +08:00
Add a WriteMicrocoded for ancient microcoded instructions. llvm-svn: 177611
2013-03-21 08:07:17 +08:00
let SchedRW = [WriteMicrocoded] in {
Added a handful of x86-32 instructions that were missing so that llvm-mc would be more complete. These are only expected to be used by llvm-mc with assembly source so there is no pattern, [], in the .td files. Most are being added to X86InstrInfo.td as Chris suggested and only comments about register uses are added. Suggestions welcome on the .td changes as I'm not sure on every detail of the x86 records. More missing instructions will be coming. llvm-svn: 116716
2010-10-19 01:04:36 +08:00
// ASCII Adjust After Addition
// sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>,
[x86] Rename In32BitMode predicate to Not64BitMode That's what it actually means, and with 16-bit support it's going to be a little more relevant since in a few corner cases we may actually want to distinguish between 16-bit and 32-bit mode (for example the bare 'push' aliases to pushw/pushl etc.) Patch by David Woodhouse llvm-svn: 197768
2013-12-20 10:04:49 +08:00
Requires<[Not64BitMode]>;
Added a handful of x86-32 instructions that were missing so that llvm-mc would be more complete. These are only expected to be used by llvm-mc with assembly source so there is no pattern, [], in the .td files. Most are being added to X86InstrInfo.td as Chris suggested and only comments about register uses are added. Suggestions welcome on the .td changes as I'm not sure on every detail of the x86 records. More missing instructions will be coming. llvm-svn: 116716
2010-10-19 01:04:36 +08:00
// ASCII Adjust AX Before Division
// sets AL, AH and EFLAGS and uses AL and AH
def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
[x86] Rename In32BitMode predicate to Not64BitMode That's what it actually means, and with 16-bit support it's going to be a little more relevant since in a few corner cases we may actually want to distinguish between 16-bit and 32-bit mode (for example the bare 'push' aliases to pushw/pushl etc.) Patch by David Woodhouse llvm-svn: 197768
2013-12-20 10:04:49 +08:00
"aad\t$src", [], IIC_AAD>, Requires<[Not64BitMode]>;
Added a handful of x86-32 instructions that were missing so that llvm-mc would be more complete. These are only expected to be used by llvm-mc with assembly source so there is no pattern, [], in the .td files. Most are being added to X86InstrInfo.td as Chris suggested and only comments about register uses are added. Suggestions welcome on the .td changes as I'm not sure on every detail of the x86 records. More missing instructions will be coming. llvm-svn: 116716
2010-10-19 01:04:36 +08:00
// ASCII Adjust AX After Multiply
// sets AL, AH and EFLAGS and uses AL
def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
[x86] Rename In32BitMode predicate to Not64BitMode That's what it actually means, and with 16-bit support it's going to be a little more relevant since in a few corner cases we may actually want to distinguish between 16-bit and 32-bit mode (for example the bare 'push' aliases to pushw/pushl etc.) Patch by David Woodhouse llvm-svn: 197768
2013-12-20 10:04:49 +08:00
"aam\t$src", [], IIC_AAM>, Requires<[Not64BitMode]>;
Added a handful of x86-32 instructions that were missing so that llvm-mc would be more complete. These are only expected to be used by llvm-mc with assembly source so there is no pattern, [], in the .td files. Most are being added to X86InstrInfo.td as Chris suggested and only comments about register uses are added. Suggestions welcome on the .td changes as I'm not sure on every detail of the x86 records. More missing instructions will be coming. llvm-svn: 116716
2010-10-19 01:04:36 +08:00
Fix Whitespace. llvm-svn: 116972
2010-10-21 07:40:27 +08:00
// ASCII Adjust AL After Subtraction - sets
Added a handful of x86-32 instructions that were missing so that llvm-mc would be more complete. These are only expected to be used by llvm-mc with assembly source so there is no pattern, [], in the .td files. Most are being added to X86InstrInfo.td as Chris suggested and only comments about register uses are added. Suggestions welcome on the .td changes as I'm not sure on every detail of the x86 records. More missing instructions will be coming. llvm-svn: 116716
2010-10-19 01:04:36 +08:00
// sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>,
[x86] Rename In32BitMode predicate to Not64BitMode That's what it actually means, and with 16-bit support it's going to be a little more relevant since in a few corner cases we may actually want to distinguish between 16-bit and 32-bit mode (for example the bare 'push' aliases to pushw/pushl etc.) Patch by David Woodhouse llvm-svn: 197768
2013-12-20 10:04:49 +08:00
Requires<[Not64BitMode]>;
Added a handful of x86-32 instructions that were missing so that llvm-mc would be more complete. These are only expected to be used by llvm-mc with assembly source so there is no pattern, [], in the .td files. Most are being added to X86InstrInfo.td as Chris suggested and only comments about register uses are added. Suggestions welcome on the .td changes as I'm not sure on every detail of the x86 records. More missing instructions will be coming. llvm-svn: 116716
2010-10-19 01:04:36 +08:00
// Decimal Adjust AL after Addition
// sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>,
[x86] Rename In32BitMode predicate to Not64BitMode That's what it actually means, and with 16-bit support it's going to be a little more relevant since in a few corner cases we may actually want to distinguish between 16-bit and 32-bit mode (for example the bare 'push' aliases to pushw/pushl etc.) Patch by David Woodhouse llvm-svn: 197768
2013-12-20 10:04:49 +08:00
Requires<[Not64BitMode]>;
Added a handful of x86-32 instructions that were missing so that llvm-mc would be more complete. These are only expected to be used by llvm-mc with assembly source so there is no pattern, [], in the .td files. Most are being added to X86InstrInfo.td as Chris suggested and only comments about register uses are added. Suggestions welcome on the .td changes as I'm not sure on every detail of the x86 records. More missing instructions will be coming. llvm-svn: 116716
2010-10-19 01:04:36 +08:00
// Decimal Adjust AL after Subtraction
// sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
[x86] Rename In32BitMode predicate to Not64BitMode That's what it actually means, and with 16-bit support it's going to be a little more relevant since in a few corner cases we may actually want to distinguish between 16-bit and 32-bit mode (for example the bare 'push' aliases to pushw/pushl etc.) Patch by David Woodhouse llvm-svn: 197768
2013-12-20 10:04:49 +08:00
Requires<[Not64BitMode]>;
Add a WriteMicrocoded for ancient microcoded instructions. llvm-svn: 177611
2013-03-21 08:07:17 +08:00
} // SchedRW
Added a handful of x86-32 instructions that were missing so that llvm-mc would be more complete. These are only expected to be used by llvm-mc with assembly source so there is no pattern, [], in the .td files. Most are being added to X86InstrInfo.td as Chris suggested and only comments about register uses are added. Suggestions welcome on the .td changes as I'm not sure on every detail of the x86 records. More missing instructions will be coming. llvm-svn: 116716
2010-10-19 01:04:36 +08:00
Add a WriteMicrocoded for ancient microcoded instructions. llvm-svn: 177611
2013-03-21 08:07:17 +08:00
let SchedRW = [WriteSystem] in {
Added a handful of x86-32 instructions that were missing so that llvm-mc would be more complete. These are only expected to be used by llvm-mc with assembly source so there is no pattern, [], in the .td files. Most are being added to X86InstrInfo.td as Chris suggested and only comments about register uses are added. Suggestions welcome on the .td changes as I'm not sure on every detail of the x86 records. More missing instructions will be coming. llvm-svn: 116716
2010-10-19 01:04:36 +08:00
// Check Array Index Against Bounds
def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16,
[x86] Rename In32BitMode predicate to Not64BitMode That's what it actually means, and with 16-bit support it's going to be a little more relevant since in a few corner cases we may actually want to distinguish between 16-bit and 32-bit mode (for example the bare 'push' aliases to pushw/pushl etc.) Patch by David Woodhouse llvm-svn: 197768
2013-12-20 10:04:49 +08:00
Requires<[Not64BitMode]>;
Added a handful of x86-32 instructions that were missing so that llvm-mc would be more complete. These are only expected to be used by llvm-mc with assembly source so there is no pattern, [], in the .td files. Most are being added to X86InstrInfo.td as Chris suggested and only comments about register uses are added. Suggestions welcome on the .td changes as I'm not sure on every detail of the x86 records. More missing instructions will be coming. llvm-svn: 116716
2010-10-19 01:04:36 +08:00
def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
"bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize32,
[x86] Rename In32BitMode predicate to Not64BitMode That's what it actually means, and with 16-bit support it's going to be a little more relevant since in a few corner cases we may actually want to distinguish between 16-bit and 32-bit mode (for example the bare 'push' aliases to pushw/pushl etc.) Patch by David Woodhouse llvm-svn: 197768
2013-12-20 10:04:49 +08:00
Requires<[Not64BitMode]>;
Added a handful of x86-32 instructions that were missing so that llvm-mc would be more complete. These are only expected to be used by llvm-mc with assembly source so there is no pattern, [], in the .td files. Most are being added to X86InstrInfo.td as Chris suggested and only comments about register uses are added. Suggestions welcome on the .td changes as I'm not sure on every detail of the x86 records. More missing instructions will be coming. llvm-svn: 116716
2010-10-19 01:04:36 +08:00
// Adjust RPL Field of Segment Selector
Fix operands and encoding form for ARPL instruction. Register form had and reversed. Memory form writes memory, but was marked as MRMSrcMem. llvm-svn: 171123
2012-12-27 07:27:57 +08:00
def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>,
[x86] Rename In32BitMode predicate to Not64BitMode That's what it actually means, and with 16-bit support it's going to be a little more relevant since in a few corner cases we may actually want to distinguish between 16-bit and 32-bit mode (for example the bare 'push' aliases to pushw/pushl etc.) Patch by David Woodhouse llvm-svn: 197768
2013-12-20 10:04:49 +08:00
Requires<[Not64BitMode]>;
Fix operands and encoding form for ARPL instruction. Register form had and reversed. Memory form writes memory, but was marked as MRMSrcMem. llvm-svn: 171123
2012-12-27 07:27:57 +08:00
def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
"arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>,
[x86] Rename In32BitMode predicate to Not64BitMode That's what it actually means, and with 16-bit support it's going to be a little more relevant since in a few corner cases we may actually want to distinguish between 16-bit and 32-bit mode (for example the bare 'push' aliases to pushw/pushl etc.) Patch by David Woodhouse llvm-svn: 197768
2013-12-20 10:04:49 +08:00
Requires<[Not64BitMode]>;
Add a WriteMicrocoded for ancient microcoded instructions. llvm-svn: 177611
2013-03-21 08:07:17 +08:00
} // SchedRW
Add support for using the FLAGS result of or, xor, and and instructions on x86, to avoid explicit test instructions. A few existing tests changed due to arbitrary register allocation differences. llvm-svn: 82263
2009-09-19 03:59:53 +08:00
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. llvm-svn: 141007
2011-10-04 01:28:23 +08:00
//===----------------------------------------------------------------------===//
// MOVBE Instructions
//
let Predicates = [HasMOVBE] in {
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
let SchedRW = [WriteALULd] in {
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. llvm-svn: 141007
2011-10-04 01:28:23 +08:00
def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
X86: Add patterns for the movbe instruction (mov + bswap, only available on atom) llvm-svn: 141563
2011-10-11 02:34:56 +08:00
"movbe{w}\t{$src, $dst|$dst, $src}",
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
[(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
2014-02-18 08:21:49 +08:00
OpSize16, T8PS;
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. llvm-svn: 141007
2011-10-04 01:28:23 +08:00
def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
X86: Add patterns for the movbe instruction (mov + bswap, only available on atom) llvm-svn: 141563
2011-10-11 02:34:56 +08:00
"movbe{l}\t{$src, $dst|$dst, $src}",
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
[(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
2014-02-18 08:21:49 +08:00
OpSize32, T8PS;
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. llvm-svn: 141007
2011-10-04 01:28:23 +08:00
def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
X86: Add patterns for the movbe instruction (mov + bswap, only available on atom) llvm-svn: 141563
2011-10-11 02:34:56 +08:00
"movbe{q}\t{$src, $dst|$dst, $src}",
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
[(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
2014-02-18 08:21:49 +08:00
T8PS;
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
}
let SchedRW = [WriteStore] in {
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. llvm-svn: 141007
2011-10-04 01:28:23 +08:00
def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
X86: Add patterns for the movbe instruction (mov + bswap, only available on atom) llvm-svn: 141563
2011-10-11 02:34:56 +08:00
"movbe{w}\t{$src, $dst|$dst, $src}",
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
[(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
2014-02-18 08:21:49 +08:00
OpSize16, T8PS;
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. llvm-svn: 141007
2011-10-04 01:28:23 +08:00
def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
X86: Add patterns for the movbe instruction (mov + bswap, only available on atom) llvm-svn: 141563
2011-10-11 02:34:56 +08:00
"movbe{l}\t{$src, $dst|$dst, $src}",
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
[(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
2014-02-18 08:21:49 +08:00
OpSize32, T8PS;
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. llvm-svn: 141007
2011-10-04 01:28:23 +08:00
def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
X86: Add patterns for the movbe instruction (mov + bswap, only available on atom) llvm-svn: 141563
2011-10-11 02:34:56 +08:00
"movbe{q}\t{$src, $dst|$dst, $src}",
Added X86 Atom latencies for instructions in X86InstrInfo.td. llvm-svn: 156579
2012-05-11 05:58:35 +08:00
[(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
2014-02-18 08:21:49 +08:00
T8PS;
Annotate a lot of X86InstrInfo.td with SchedRW lists. llvm-svn: 177417
2013-03-20 02:03:55 +08:00
}
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. llvm-svn: 141007
2011-10-04 01:28:23 +08:00
}
//===----------------------------------------------------------------------===//
// RDRAND Instruction
//
let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
Add intrinsics for Ivy Bridge's rdrand instruction. The rdrand/cmov sequence is the same that is emitted by both GCC and ICC. Fixes PR13284. llvm-svn: 160117
2012-07-12 17:31:43 +08:00
"rdrand{w}\t$dst",
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
[(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB;
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. llvm-svn: 141007
2011-10-04 01:28:23 +08:00
def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
Add intrinsics for Ivy Bridge's rdrand instruction. The rdrand/cmov sequence is the same that is emitted by both GCC and ICC. Fixes PR13284. llvm-svn: 160117
2012-07-12 17:31:43 +08:00
"rdrand{l}\t$dst",
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
[(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize32, TB;
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. llvm-svn: 141007
2011-10-04 01:28:23 +08:00
def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
Add intrinsics for Ivy Bridge's rdrand instruction. The rdrand/cmov sequence is the same that is emitted by both GCC and ICC. Fixes PR13284. llvm-svn: 160117
2012-07-12 17:31:43 +08:00
"rdrand{q}\t$dst",
[(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. llvm-svn: 141007
2011-10-04 01:28:23 +08:00
}
Add support of RDSEED defined in AVX2 extension llvm-svn: 178314
2013-03-29 07:41:26 +08:00
//===----------------------------------------------------------------------===//
// RDSEED Instruction
//
let Predicates = [HasRDSEED], Defs = [EFLAGS] in {
def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins),
"rdseed{w}\t$dst",
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
[(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB;
Add support of RDSEED defined in AVX2 extension llvm-svn: 178314
2013-03-29 07:41:26 +08:00
def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
"rdseed{l}\t$dst",
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
[(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, TB;
Add support of RDSEED defined in AVX2 extension llvm-svn: 178314
2013-03-29 07:41:26 +08:00
def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
"rdseed{q}\t$dst",
[(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;
}
Add X86 LZCNT instruction. Including instruction selection support. llvm-svn: 141651
2011-10-11 14:44:02 +08:00
//===----------------------------------------------------------------------===//
// LZCNT Instruction
//
let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
"lzcnt{w}\t{$src, $dst|$dst, $src}",
Add 'implicit EFLAGS' to patterns for popcnt and lzcnt llvm-svn: 141853
2011-10-13 14:18:52 +08:00
[(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize16;
Add X86 LZCNT instruction. Including instruction selection support. llvm-svn: 141651
2011-10-11 14:44:02 +08:00
def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
"lzcnt{w}\t{$src, $dst|$dst, $src}",
Add 'implicit EFLAGS' to patterns for popcnt and lzcnt llvm-svn: 141853
2011-10-13 14:18:52 +08:00
[(set GR16:$dst, (ctlz (loadi16 addr:$src))),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
(implicit EFLAGS)]>, XS, OpSize16;
Add X86 LZCNT instruction. Including instruction selection support. llvm-svn: 141651
2011-10-11 14:44:02 +08:00
def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
"lzcnt{l}\t{$src, $dst|$dst, $src}",
[x86] Add OpSize16 to instructions that need it This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. llvm-svn: 198752
2014-01-08 20:57:40 +08:00
[(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize32;
Add X86 LZCNT instruction. Including instruction selection support. llvm-svn: 141651
2011-10-11 14:44:02 +08:00
def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
"lzcnt{l}\t{$src, $dst|$dst, $src}",
Add 'implicit EFLAGS' to patterns for popcnt and lzcnt llvm-svn: 141853
2011-10-13 14:18:52 +08:00
[(set GR32:$dst, (ctlz (loadi32 addr:$src))),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
(implicit EFLAGS)]>, XS, OpSize32;
Add X86 LZCNT instruction. Including instruction selection support. llvm-svn: 141651
2011-10-11 14:44:02 +08:00
def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
"lzcnt{q}\t{$src, $dst|$dst, $src}",
Add 'implicit EFLAGS' to patterns for popcnt and lzcnt llvm-svn: 141853
2011-10-13 14:18:52 +08:00
[(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
XS;
Add X86 LZCNT instruction. Including instruction selection support. llvm-svn: 141651
2011-10-11 14:44:02 +08:00
def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
"lzcnt{q}\t{$src, $dst|$dst, $src}",
Add 'implicit EFLAGS' to patterns for popcnt and lzcnt llvm-svn: 141853
2011-10-13 14:18:52 +08:00
[(set GR64:$dst, (ctlz (loadi64 addr:$src))),
(implicit EFLAGS)]>, XS;
Add X86 LZCNT instruction. Including instruction selection support. llvm-svn: 141651
2011-10-11 14:44:02 +08:00
}
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
let Predicates = [HasLZCNT] in {
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
def : Pat<(X86cmov (ctlz GR16:$src), (i16 16), (X86_COND_E_OR_NE),
[X86] Clean up whitespace as well as minor coding style llvm-svn: 223339
2014-12-04 13:20:33 +08:00
(X86cmp GR16:$src, (i16 0))),
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
(LZCNT16rr GR16:$src)>;
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
def : Pat<(X86cmov (ctlz GR32:$src), (i32 32), (X86_COND_E_OR_NE),
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
(X86cmp GR32:$src, (i32 0))),
(LZCNT32rr GR32:$src)>;
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
def : Pat<(X86cmov (ctlz GR64:$src), (i64 64), (X86_COND_E_OR_NE),
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
(X86cmp GR64:$src, (i64 0))),
(LZCNT64rr GR64:$src)>;
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
def : Pat<(X86cmov (i16 16), (ctlz GR16:$src), (X86_COND_E_OR_NE),
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
(X86cmp GR16:$src, (i16 0))),
(LZCNT16rr GR16:$src)>;
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
def : Pat<(X86cmov (i32 32), (ctlz GR32:$src), (X86_COND_E_OR_NE),
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
(X86cmp GR32:$src, (i32 0))),
(LZCNT32rr GR32:$src)>;
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
def : Pat<(X86cmov (i64 64), (ctlz GR64:$src), (X86_COND_E_OR_NE),
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
(X86cmp GR64:$src, (i64 0))),
(LZCNT64rr GR64:$src)>;
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
def : Pat<(X86cmov (ctlz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE),
[X86] Clean up whitespace as well as minor coding style llvm-svn: 223339
2014-12-04 13:20:33 +08:00
(X86cmp (loadi16 addr:$src), (i16 0))),
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
(LZCNT16rm addr:$src)>;
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
def : Pat<(X86cmov (ctlz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE),
[X86] Clean up whitespace as well as minor coding style llvm-svn: 223339
2014-12-04 13:20:33 +08:00
(X86cmp (loadi32 addr:$src), (i32 0))),
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
(LZCNT32rm addr:$src)>;
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
def : Pat<(X86cmov (ctlz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE),
[X86] Clean up whitespace as well as minor coding style llvm-svn: 223339
2014-12-04 13:20:33 +08:00
(X86cmp (loadi64 addr:$src), (i64 0))),
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
(LZCNT64rm addr:$src)>;
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
def : Pat<(X86cmov (i16 16), (ctlz (loadi16 addr:$src)), (X86_COND_E_OR_NE),
[X86] Clean up whitespace as well as minor coding style llvm-svn: 223339
2014-12-04 13:20:33 +08:00
(X86cmp (loadi16 addr:$src), (i16 0))),
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
(LZCNT16rm addr:$src)>;
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
def : Pat<(X86cmov (i32 32), (ctlz (loadi32 addr:$src)), (X86_COND_E_OR_NE),
[X86] Clean up whitespace as well as minor coding style llvm-svn: 223339
2014-12-04 13:20:33 +08:00
(X86cmp (loadi32 addr:$src), (i32 0))),
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
(LZCNT32rm addr:$src)>;
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
def : Pat<(X86cmov (i64 64), (ctlz (loadi64 addr:$src)), (X86_COND_E_OR_NE),
[X86] Clean up whitespace as well as minor coding style llvm-svn: 223339
2014-12-04 13:20:33 +08:00
(X86cmp (loadi64 addr:$src), (i64 0))),
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
(LZCNT64rm addr:$src)>;
}
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. llvm-svn: 141939
2011-10-14 11:21:46 +08:00
//===----------------------------------------------------------------------===//
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension. llvm-svn: 142082
2011-10-16 04:46:47 +08:00
// BMI Instructions
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. llvm-svn: 141939
2011-10-14 11:21:46 +08:00
//
let Predicates = [HasBMI], Defs = [EFLAGS] in {
def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
"tzcnt{w}\t{$src, $dst|$dst, $src}",
[(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize16;
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. llvm-svn: 141939
2011-10-14 11:21:46 +08:00
def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
"tzcnt{w}\t{$src, $dst|$dst, $src}",
[(set GR16:$dst, (cttz (loadi16 addr:$src))),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
(implicit EFLAGS)]>, XS, OpSize16;
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. llvm-svn: 141939
2011-10-14 11:21:46 +08:00
def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
"tzcnt{l}\t{$src, $dst|$dst, $src}",
[x86] Add OpSize16 to instructions that need it This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. llvm-svn: 198752
2014-01-08 20:57:40 +08:00
[(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS,
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
OpSize32;
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. llvm-svn: 141939
2011-10-14 11:21:46 +08:00
def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
"tzcnt{l}\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, (cttz (loadi32 addr:$src))),
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
2014-02-02 17:25:09 +08:00
(implicit EFLAGS)]>, XS, OpSize32;
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. llvm-svn: 141939
2011-10-14 11:21:46 +08:00
def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
"tzcnt{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
XS;
def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
"tzcnt{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, (cttz (loadi64 addr:$src))),
(implicit EFLAGS)]>, XS;
}
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension. llvm-svn: 142082
2011-10-16 04:46:47 +08:00
multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
Move matching for x86 BMI BLSI/BLSMSK/BLSR instructions to isel patterns instead of DAG combine. This weakens the ability to fold loads with them because we aren't able to match patterns that load the same thing twice. But maybe we should fix that if we care. The peephole optimizer will be able to fold some loads in its absense. llvm-svn: 200824
2014-02-05 15:09:40 +08:00
RegisterClass RC, X86MemOperand x86memop> {
let hasSideEffects = 0 in {
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension. llvm-svn: 142082
2011-10-16 04:46:47 +08:00
def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. llvm-svn: 142480
2011-10-19 15:48:35 +08:00
!strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
2014-02-18 08:21:49 +08:00
[]>, T8PS, VEX_4V;
Move matching for x86 BMI BLSI/BLSMSK/BLSR instructions to isel patterns instead of DAG combine. This weakens the ability to fold loads with them because we aren't able to match patterns that load the same thing twice. But maybe we should fix that if we care. The peephole optimizer will be able to fold some loads in its absense. llvm-svn: 200824
2014-02-05 15:09:40 +08:00
let mayLoad = 1 in
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension. llvm-svn: 142082
2011-10-16 04:46:47 +08:00
def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. llvm-svn: 142480
2011-10-19 15:48:35 +08:00
!strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
2014-02-18 08:21:49 +08:00
[]>, T8PS, VEX_4V;
Move matching for x86 BMI BLSI/BLSMSK/BLSR instructions to isel patterns instead of DAG combine. This weakens the ability to fold loads with them because we aren't able to match patterns that load the same thing twice. But maybe we should fix that if we care. The peephole optimizer will be able to fold some loads in its absense. llvm-svn: 200824
2014-02-05 15:09:40 +08:00
}
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension. llvm-svn: 142082
2011-10-16 04:46:47 +08:00
}
let Predicates = [HasBMI], Defs = [EFLAGS] in {
Move matching for x86 BMI BLSI/BLSMSK/BLSR instructions to isel patterns instead of DAG combine. This weakens the ability to fold loads with them because we aren't able to match patterns that load the same thing twice. But maybe we should fix that if we care. The peephole optimizer will be able to fold some loads in its absense. llvm-svn: 200824
2014-02-05 15:09:40 +08:00
defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>;
defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W;
defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>;
defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W;
defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>;
defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W;
}
//===----------------------------------------------------------------------===//
// Pattern fragments to auto generate BMI instructions.
//===----------------------------------------------------------------------===//
let Predicates = [HasBMI] in {
// FIXME: patterns for the load versions are not implemented
def : Pat<(and GR32:$src, (add GR32:$src, -1)),
(BLSR32rr GR32:$src)>;
def : Pat<(and GR64:$src, (add GR64:$src, -1)),
(BLSR64rr GR64:$src)>;
def : Pat<(xor GR32:$src, (add GR32:$src, -1)),
(BLSMSK32rr GR32:$src)>;
def : Pat<(xor GR64:$src, (add GR64:$src, -1)),
(BLSMSK64rr GR64:$src)>;
def : Pat<(and GR32:$src, (ineg GR32:$src)),
(BLSI32rr GR32:$src)>;
def : Pat<(and GR64:$src, (ineg GR64:$src)),
(BLSI64rr GR64:$src)>;
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen llvm-svn: 142105
2011-10-16 11:51:13 +08:00
}
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
let Predicates = [HasBMI] in {
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
def : Pat<(X86cmov (cttz GR16:$src), (i16 16), (X86_COND_E_OR_NE),
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
(X86cmp GR16:$src, (i16 0))),
(TZCNT16rr GR16:$src)>;
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
def : Pat<(X86cmov (cttz GR32:$src), (i32 32), (X86_COND_E_OR_NE),
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
(X86cmp GR32:$src, (i32 0))),
(TZCNT32rr GR32:$src)>;
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
def : Pat<(X86cmov (cttz GR64:$src), (i64 64), (X86_COND_E_OR_NE),
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
(X86cmp GR64:$src, (i64 0))),
(TZCNT64rr GR64:$src)>;
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
def : Pat<(X86cmov (i16 16), (cttz GR16:$src), (X86_COND_E_OR_NE),
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
(X86cmp GR16:$src, (i16 0))),
(TZCNT16rr GR16:$src)>;
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
def : Pat<(X86cmov (i32 32), (cttz GR32:$src), (X86_COND_E_OR_NE),
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
(X86cmp GR32:$src, (i32 0))),
(TZCNT32rr GR32:$src)>;
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
def : Pat<(X86cmov (i64 64), (cttz GR64:$src), (X86_COND_E_OR_NE),
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
(X86cmp GR64:$src, (i64 0))),
(TZCNT64rr GR64:$src)>;
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
def : Pat<(X86cmov (cttz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE),
[X86] Clean up whitespace as well as minor coding style llvm-svn: 223339
2014-12-04 13:20:33 +08:00
(X86cmp (loadi16 addr:$src), (i16 0))),
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
(TZCNT16rm addr:$src)>;
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
def : Pat<(X86cmov (cttz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE),
[X86] Clean up whitespace as well as minor coding style llvm-svn: 223339
2014-12-04 13:20:33 +08:00
(X86cmp (loadi32 addr:$src), (i32 0))),
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
(TZCNT32rm addr:$src)>;
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
def : Pat<(X86cmov (cttz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE),
[X86] Clean up whitespace as well as minor coding style llvm-svn: 223339
2014-12-04 13:20:33 +08:00
(X86cmp (loadi64 addr:$src), (i64 0))),
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
(TZCNT64rm addr:$src)>;
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
def : Pat<(X86cmov (i16 16), (cttz (loadi16 addr:$src)), (X86_COND_E_OR_NE),
[X86] Clean up whitespace as well as minor coding style llvm-svn: 223339
2014-12-04 13:20:33 +08:00
(X86cmp (loadi16 addr:$src), (i16 0))),
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
(TZCNT16rm addr:$src)>;
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
def : Pat<(X86cmov (i32 32), (cttz (loadi32 addr:$src)), (X86_COND_E_OR_NE),
[X86] Clean up whitespace as well as minor coding style llvm-svn: 223339
2014-12-04 13:20:33 +08:00
(X86cmp (loadi32 addr:$src), (i32 0))),
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
(TZCNT32rm addr:$src)>;
[X86] Improved tablegen patters for matching TZCNT/LZCNT. Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. llvm-svn: 223668
2014-12-09 01:47:18 +08:00
def : Pat<(X86cmov (i64 64), (cttz (loadi64 addr:$src)), (X86_COND_E_OR_NE),
[X86] Clean up whitespace as well as minor coding style llvm-svn: 223339
2014-12-04 13:20:33 +08:00
(X86cmp (loadi64 addr:$src), (i64 0))),
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
2014-05-20 04:38:59 +08:00
(TZCNT64rm addr:$src)>;
}
Add X86 BZHI instruction as well as BMI2 feature detection. llvm-svn: 142122
2011-10-16 15:55:05 +08:00
multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. llvm-svn: 142480
2011-10-19 15:48:35 +08:00
X86MemOperand x86memop, Intrinsic Int,
PatFrag ld_frag> {
Add X86 BZHI instruction as well as BMI2 feature detection. llvm-svn: 142122
2011-10-16 15:55:05 +08:00
def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen llvm-svn: 142105
2011-10-16 11:51:13 +08:00
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. llvm-svn: 142480
2011-10-19 15:48:35 +08:00
[(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
2014-02-18 08:21:49 +08:00
T8PS, VEX_4VOp3;
Add X86 BZHI instruction as well as BMI2 feature detection. llvm-svn: 142122
2011-10-16 15:55:05 +08:00
def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen llvm-svn: 142105
2011-10-16 11:51:13 +08:00
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. llvm-svn: 142480
2011-10-19 15:48:35 +08:00
[(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
2014-02-18 08:21:49 +08:00
(implicit EFLAGS)]>, T8PS, VEX_4VOp3;
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen llvm-svn: 142105
2011-10-16 11:51:13 +08:00
}
let Predicates = [HasBMI], Defs = [EFLAGS] in {
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. llvm-svn: 142480
2011-10-19 15:48:35 +08:00
defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
int_x86_bmi_bextr_32, loadi32>;
defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
int_x86_bmi_bextr_64, loadi64>, VEX_W;
Add X86 BZHI instruction as well as BMI2 feature detection. llvm-svn: 142122
2011-10-16 15:55:05 +08:00
}
let Predicates = [HasBMI2], Defs = [EFLAGS] in {
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. llvm-svn: 142480
2011-10-19 15:48:35 +08:00
defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
int_x86_bmi_bzhi_32, loadi32>;
defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
int_x86_bmi_bzhi_64, loadi64>, VEX_W;
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension. llvm-svn: 142082
2011-10-16 04:46:47 +08:00
}
[X86] Use tablegen instead of DAG combines to match BZHI instructions, as suggested by Ben Kramer in review of r206738. Thanks again Ben! llvm-svn: 206879
2014-04-22 18:41:56 +08:00
def CountTrailingOnes : SDNodeXForm<imm, [{
// Count the trailing ones in the immediate.
return getI8Imm(CountTrailingOnes_64(N->getZExtValue()));
}]>;
def BZHIMask : ImmLeaf<i64, [{
return isMask_64(Imm) && (CountTrailingOnes_64(Imm) > 32);
}]>;
[X86] Require HasBMI2 for the new BZHI tablegen patterns. Evidently tablegen doesn't infer this from the HasBMI2 predicate on the BZHI instructions. This should fix the recent bot failures. llvm-svn: 206885
2014-04-22 20:04:53 +08:00
let Predicates = [HasBMI2] in {
def : Pat<(and GR64:$src, BZHIMask:$mask),
(BZHI64rr GR64:$src,
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>;
def : Pat<(and GR32:$src, (add (shl 1, GR8:$lz), -1)),
(BZHI32rr GR32:$src,
(INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
def : Pat<(and (loadi32 addr:$src), (add (shl 1, GR8:$lz), -1)),
(BZHI32rm addr:$src,
(INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
def : Pat<(and GR64:$src, (add (shl 1, GR8:$lz), -1)),
(BZHI64rr GR64:$src,
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
def : Pat<(and (loadi64 addr:$src), (add (shl 1, GR8:$lz), -1)),
(BZHI64rm addr:$src,
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
} // HasBMI2
Teach X86 backend to create BMI2 BZHI instructions from (and X, (add (shl 1, Y), -1)). Fixes PR17038. llvm-svn: 189653
2013-08-30 14:52:21 +08:00
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
let Predicates = [HasBMI] in {
def : Pat<(X86bextr GR32:$src1, GR32:$src2),
(BEXTR32rr GR32:$src1, GR32:$src2)>;
def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2),
(BEXTR32rm addr:$src1, GR32:$src2)>;
def : Pat<(X86bextr GR64:$src1, GR64:$src2),
(BEXTR64rr GR64:$src1, GR64:$src2)>;
def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2),
(BEXTR64rm addr:$src1, GR64:$src2)>;
} // HasBMI
Create BEXTR instructions for (and ((sra or srl) x, imm), (2**size - 1)). Fixes PR17028. llvm-svn: 189742
2013-09-02 15:53:17 +08:00
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. llvm-svn: 142480
2011-10-19 15:48:35 +08:00
multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
X86MemOperand x86memop, Intrinsic Int,
PatFrag ld_frag> {
Add X86 PEXTR and PDEP instructions. llvm-svn: 142141
2011-10-17 00:50:08 +08:00
def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. llvm-svn: 142480
2011-10-19 15:48:35 +08:00
[(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
VEX_4V;
Add X86 PEXTR and PDEP instructions. llvm-svn: 142141
2011-10-17 00:50:08 +08:00
def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. llvm-svn: 142480
2011-10-19 15:48:35 +08:00
[(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
Add X86 PEXTR and PDEP instructions. llvm-svn: 142141
2011-10-17 00:50:08 +08:00
}
let Predicates = [HasBMI2] in {
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. llvm-svn: 142480
2011-10-19 15:48:35 +08:00
defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
int_x86_bmi_pdep_32, loadi32>, T8XD;
defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
int_x86_bmi_pext_32, loadi32>, T8XS;
defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
Add X86 PEXTR and PDEP instructions. llvm-svn: 142141
2011-10-17 00:50:08 +08:00
}
Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539
2013-09-28 02:38:42 +08:00
//===----------------------------------------------------------------------===//
// TBM Instructions
//
Add XOP disassembler support. Fixes PR13933. llvm-svn: 191874
2013-10-03 13:17:48 +08:00
let Predicates = [HasTBM], Defs = [EFLAGS] in {
Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539
2013-09-28 02:38:42 +08:00
multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr,
X86MemOperand x86memop, PatFrag ld_frag,
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
Intrinsic Int, Operand immtype,
SDPatternOperator immoperator> {
def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539
2013-09-28 02:38:42 +08:00
!strconcat(OpcodeStr,
"\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
[(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>,
Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field in TSFlags. llvm-svn: 200624
2014-02-02 15:08:01 +08:00
XOP, XOPA;
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst),
(ins x86memop:$src1, immtype:$cntl),
Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539
2013-09-28 02:38:42 +08:00
!strconcat(OpcodeStr,
"\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
[(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>,
Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field in TSFlags. llvm-svn: 200624
2014-02-02 15:08:01 +08:00
XOP, XOPA;
Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539
2013-09-28 02:38:42 +08:00
}
defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32,
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
int_x86_tbm_bextri_u32, i32imm, imm>;
[x86] Fix signed relocations for i64i32imm operands These should end up (in ELF) as R_X86_64_32S relocs, not R_X86_64_32. Kill the horrid and incomplete special case and FIXME in EncodeInstruction() and set things up so it can infer the signedness from the ImmType just like it can the size and whether it's PC-relative. llvm-svn: 200495
2014-01-31 06:20:41 +08:00
let ImmT = Imm32S in
Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539
2013-09-28 02:38:42 +08:00
defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64,
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
int_x86_tbm_bextri_u64, i64i32imm,
i64immSExt32>, VEX_W;
Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539
2013-09-28 02:38:42 +08:00
multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem,
RegisterClass RC, string OpcodeStr,
Remove unneeded TBM intrinsics. The arithmetic/logical operation patterns are sufficient. llvm-svn: 192039
2013-10-06 03:22:59 +08:00
X86MemOperand x86memop, PatFrag ld_frag> {
let hasSideEffects = 0 in {
Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539
2013-09-28 02:38:42 +08:00
def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src),
!strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field in TSFlags. llvm-svn: 200624
2014-02-02 15:08:01 +08:00
[]>, XOP_4V, XOP9;
Remove unneeded TBM intrinsics. The arithmetic/logical operation patterns are sufficient. llvm-svn: 192039
2013-10-06 03:22:59 +08:00
let mayLoad = 1 in
Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539
2013-09-28 02:38:42 +08:00
def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src),
!strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field in TSFlags. llvm-svn: 200624
2014-02-02 15:08:01 +08:00
[]>, XOP_4V, XOP9;
Remove unneeded TBM intrinsics. The arithmetic/logical operation patterns are sufficient. llvm-svn: 192039
2013-10-06 03:22:59 +08:00
}
Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539
2013-09-28 02:38:42 +08:00
}
multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr,
Remove unneeded TBM intrinsics. The arithmetic/logical operation patterns are sufficient. llvm-svn: 192039
2013-10-06 03:22:59 +08:00
Format FormReg, Format FormMem> {
Remove underscores from TBM instruction names for consistency with other instruction naming. llvm-svn: 192040
2013-10-06 03:27:26 +08:00
defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr, i32mem,
loadi32>;
defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr, i64mem,
loadi64>, VEX_W;
Remove unneeded TBM intrinsics. The arithmetic/logical operation patterns are sufficient. llvm-svn: 192039
2013-10-06 03:22:59 +08:00
}
defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>;
defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>;
defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>;
defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>;
defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m>;
defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>;
defm BLSIC : tbm_binary_intr<0x01, "blsic", MRM6r, MRM6m>;
defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>;
defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>;
Add XOP disassembler support. Fixes PR13933. llvm-svn: 191874
2013-10-03 13:17:48 +08:00
} // HasTBM, EFLAGS
Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539
2013-09-28 02:38:42 +08:00
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
//===----------------------------------------------------------------------===//
// Pattern fragments to auto generate TBM instructions.
//===----------------------------------------------------------------------===//
let Predicates = [HasTBM] in {
def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)),
(BEXTRI32ri GR32:$src1, imm:$src2)>;
def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)),
(BEXTRI32mi addr:$src1, imm:$src2)>;
def : Pat<(X86bextr GR64:$src1, i64immSExt32:$src2),
(BEXTRI64ri GR64:$src1, i64immSExt32:$src2)>;
def : Pat<(X86bextr (loadi64 addr:$src1), i64immSExt32:$src2),
(BEXTRI64mi addr:$src1, i64immSExt32:$src2)>;
// FIXME: patterns for the load versions are not implemented
def : Pat<(and GR32:$src, (add GR32:$src, 1)),
Remove underscores from TBM instruction names for consistency with other instruction naming. llvm-svn: 192040
2013-10-06 03:27:26 +08:00
(BLCFILL32rr GR32:$src)>;
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
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def : Pat<(and GR64:$src, (add GR64:$src, 1)),
Remove underscores from TBM instruction names for consistency with other instruction naming. llvm-svn: 192040
2013-10-06 03:27:26 +08:00
(BLCFILL64rr GR64:$src)>;
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
def : Pat<(or GR32:$src, (not (add GR32:$src, 1))),
Remove underscores from TBM instruction names for consistency with other instruction naming. llvm-svn: 192040
2013-10-06 03:27:26 +08:00
(BLCI32rr GR32:$src)>;
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
def : Pat<(or GR64:$src, (not (add GR64:$src, 1))),
Remove underscores from TBM instruction names for consistency with other instruction naming. llvm-svn: 192040
2013-10-06 03:27:26 +08:00
(BLCI64rr GR64:$src)>;
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
Add an additional pattern for BLCI since opt can turn (not (add x, 1)) into (sub -2, x). llvm-svn: 192037
2013-10-06 01:17:53 +08:00
// Extra patterns because opt can optimize the above patterns to this.
def : Pat<(or GR32:$src, (sub -2, GR32:$src)),
Remove underscores from TBM instruction names for consistency with other instruction naming. llvm-svn: 192040
2013-10-06 03:27:26 +08:00
(BLCI32rr GR32:$src)>;
Add an additional pattern for BLCI since opt can turn (not (add x, 1)) into (sub -2, x). llvm-svn: 192037
2013-10-06 01:17:53 +08:00
def : Pat<(or GR64:$src, (sub -2, GR64:$src)),
Remove underscores from TBM instruction names for consistency with other instruction naming. llvm-svn: 192040
2013-10-06 03:27:26 +08:00
(BLCI64rr GR64:$src)>;
Add an additional pattern for BLCI since opt can turn (not (add x, 1)) into (sub -2, x). llvm-svn: 192037
2013-10-06 01:17:53 +08:00
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
def : Pat<(and (not GR32:$src), (add GR32:$src, 1)),
Remove underscores from TBM instruction names for consistency with other instruction naming. llvm-svn: 192040
2013-10-06 03:27:26 +08:00
(BLCIC32rr GR32:$src)>;
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
def : Pat<(and (not GR64:$src), (add GR64:$src, 1)),
Remove underscores from TBM instruction names for consistency with other instruction naming. llvm-svn: 192040
2013-10-06 03:27:26 +08:00
(BLCIC64rr GR64:$src)>;
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
def : Pat<(xor GR32:$src, (add GR32:$src, 1)),
Remove underscores from TBM instruction names for consistency with other instruction naming. llvm-svn: 192040
2013-10-06 03:27:26 +08:00
(BLCMSK32rr GR32:$src)>;
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
def : Pat<(xor GR64:$src, (add GR64:$src, 1)),
Remove underscores from TBM instruction names for consistency with other instruction naming. llvm-svn: 192040
2013-10-06 03:27:26 +08:00
(BLCMSK64rr GR64:$src)>;
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
def : Pat<(or GR32:$src, (add GR32:$src, 1)),
Remove underscores from TBM instruction names for consistency with other instruction naming. llvm-svn: 192040
2013-10-06 03:27:26 +08:00
(BLCS32rr GR32:$src)>;
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
def : Pat<(or GR64:$src, (add GR64:$src, 1)),
Remove underscores from TBM instruction names for consistency with other instruction naming. llvm-svn: 192040
2013-10-06 03:27:26 +08:00
(BLCS64rr GR64:$src)>;
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
def : Pat<(or GR32:$src, (add GR32:$src, -1)),
Remove underscores from TBM instruction names for consistency with other instruction naming. llvm-svn: 192040
2013-10-06 03:27:26 +08:00
(BLSFILL32rr GR32:$src)>;
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
def : Pat<(or GR64:$src, (add GR64:$src, -1)),
Remove underscores from TBM instruction names for consistency with other instruction naming. llvm-svn: 192040
2013-10-06 03:27:26 +08:00
(BLSFILL64rr GR64:$src)>;
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
def : Pat<(or (not GR32:$src), (add GR32:$src, -1)),
Remove underscores from TBM instruction names for consistency with other instruction naming. llvm-svn: 192040
2013-10-06 03:27:26 +08:00
(BLSIC32rr GR32:$src)>;
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
def : Pat<(or (not GR64:$src), (add GR64:$src, -1)),
Remove underscores from TBM instruction names for consistency with other instruction naming. llvm-svn: 192040
2013-10-06 03:27:26 +08:00
(BLSIC64rr GR64:$src)>;
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
def : Pat<(or (not GR32:$src), (add GR32:$src, 1)),
Remove underscores from TBM instruction names for consistency with other instruction naming. llvm-svn: 192040
2013-10-06 03:27:26 +08:00
(T1MSKC32rr GR32:$src)>;
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
def : Pat<(or (not GR64:$src), (add GR64:$src, 1)),
Remove underscores from TBM instruction names for consistency with other instruction naming. llvm-svn: 192040
2013-10-06 03:27:26 +08:00
(T1MSKC64rr GR64:$src)>;
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
def : Pat<(and (not GR32:$src), (add GR32:$src, -1)),
Remove underscores from TBM instruction names for consistency with other instruction naming. llvm-svn: 192040
2013-10-06 03:27:26 +08:00
(TZMSK32rr GR32:$src)>;
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
def : Pat<(and (not GR64:$src), (add GR64:$src, -1)),
Remove underscores from TBM instruction names for consistency with other instruction naming. llvm-svn: 192040
2013-10-06 03:27:26 +08:00
(TZMSK64rr GR64:$src)>;
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
} // HasTBM
One more round of reorg so sabre doesn't freak out. :-) llvm-svn: 26303
2006-02-22 04:00:20 +08:00
//===----------------------------------------------------------------------===//
refactor .td files a bit, moving system instructions out to X86InstrSystem.td llvm-svn: 115591
2010-10-05 13:32:15 +08:00
// Subsystems.
One more round of reorg so sabre doesn't freak out. :-) llvm-svn: 26303
2006-02-22 04:00:20 +08:00
//===----------------------------------------------------------------------===//
split the 32-bit integer arithmetic instructions out to their own file. llvm-svn: 115627
2010-10-06 00:39:12 +08:00
include "X86InstrArithmetic.td"
split conditional moves and setcc's out to their own file. llvm-svn: 115601
2010-10-05 14:33:16 +08:00
include "X86InstrCMovSetCC.td"
move sign and zero extensions out to their own file. llvm-svn: 115605
2010-10-05 14:52:26 +08:00
include "X86InstrExtension.td"
continue moving stuff out to X86InstrSystem.td. Move control flow stuff out to X86InstrControl.td. Move some compiler pseudo instructions and Pat<> patterns out to X86InstrCompiler.td llvm-svn: 115596
2010-10-05 14:04:14 +08:00
include "X86InstrControl.td"
move 32-bit shift and rotates out to their own file. llvm-svn: 115607
2010-10-05 15:00:12 +08:00
include "X86InstrShiftRotate.td"
continue moving stuff out to X86InstrSystem.td. Move control flow stuff out to X86InstrControl.td. Move some compiler pseudo instructions and Pat<> patterns out to X86InstrCompiler.td llvm-svn: 115596
2010-10-05 14:04:14 +08:00
split the 32-bit integer arithmetic instructions out to their own file. llvm-svn: 115627
2010-10-06 00:39:12 +08:00
// X87 Floating Point Stack.
include "X86InstrFPStack.td"
TableGen fragment refactoring. Move some utility TableGen defs, classes, etc. into a common file so they may be used my multiple pattern files. We will use this for the AVX specification to help with the transition from the current SSE specification. llvm-svn: 95727
2010-02-10 07:52:19 +08:00
// SIMD support (SSE, MMX and AVX)
include "X86InstrFragmentsSIMD.td"
Add complete assembler support for FMA3 instructions, with descriptions and encodings taken from the AVX manual llvm-svn: 109204
2010-07-23 08:54:35 +08:00
// FMA - Fused Multiply-Add support (requires FMA)
include "X86InstrFMA.td"
XOP instructions and encoding tests. llvm-svn: 146407
2011-12-13 03:37:49 +08:00
// XOP
include "X86InstrXOP.td"
refactor .td files a bit, moving system instructions out to X86InstrSystem.td llvm-svn: 115591
2010-10-05 13:32:15 +08:00
// SSE, MMX and 3DNow! vector support.
Fix MMX_MOVQ2DQrr pattern. It's illegal to do a bitconvert from a smaller type to a larger one. llvm-svn: 50278
2008-04-26 02:19:54 +08:00
include "X86InstrSSE.td"
Added INSERT and EXTRACT intructions from AVX-512 ISA. All insertf*/extractf* functions replaced with insert/extract since we have insertf and inserti forms. Added lowering for INSERT_VECTOR_ELT / EXTRACT_VECTOR_ELT for 512-bit vectors. Added lowering for EXTRACT/INSERT subvector for 512-bit vectors. Added a test. llvm-svn: 187491
2013-07-31 19:35:14 +08:00
include "X86InstrAVX512.td"
Fix MMX_MOVQ2DQrr pattern. It's illegal to do a bitconvert from a smaller type to a larger one. llvm-svn: 50278
2008-04-26 02:19:54 +08:00
include "X86InstrMMX.td"
stub out a header to put 3dNow! instructions into. llvm-svn: 115429
2010-10-03 07:06:23 +08:00
include "X86Instr3DNow.td"
move VMX instructions out to their own file. llvm-svn: 115597
2010-10-05 14:06:53 +08:00
include "X86InstrVMX.td"
Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication. llvm-svn: 150873
2012-02-18 16:19:49 +08:00
include "X86InstrSVM.td"
move VMX instructions out to their own file. llvm-svn: 115597
2010-10-05 14:06:53 +08:00
Add support of RTM from TSX extension - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region llvm-svn: 167573
2012-11-08 15:28:54 +08:00
include "X86InstrTSX.td"
Add support for the X86 secure guard extensions instructions in assembler (SGX). This allows assembling the two new instructions, encls and enclu for the SKX processor model. Note the diffs are a bigger than what might think, but to fit the new MRM_CF and MRM_D7 in things in the right places things had to be renumbered and shuffled down causing a bit more diffs. rdar://16228228 llvm-svn: 214460
2014-08-01 07:57:38 +08:00
include "X86InstrSGX.td"
Add support of RTM from TSX extension - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region llvm-svn: 167573
2012-11-08 15:28:54 +08:00
refactor .td files a bit, moving system instructions out to X86InstrSystem.td llvm-svn: 115591
2010-10-05 13:32:15 +08:00
// System instructions.
include "X86InstrSystem.td"
continue moving stuff out to X86InstrSystem.td. Move control flow stuff out to X86InstrControl.td. Move some compiler pseudo instructions and Pat<> patterns out to X86InstrCompiler.td llvm-svn: 115596
2010-10-05 14:04:14 +08:00
// Compiler Pseudo Instructions and Pat Patterns
include "X86InstrCompiler.td"
implement (and document!) the first kind of MC assembler alias, which just remaps one mnemonic to another. Convert a few of the X86 aliases from .cpp to .td code. llvm-svn: 117815
2010-10-31 01:36:36 +08:00
//===----------------------------------------------------------------------===//
rearrange a bit. llvm-svn: 117967
2010-11-02 07:07:52 +08:00
// Assembler Mnemonic Aliases
implement (and document!) the first kind of MC assembler alias, which just remaps one mnemonic to another. Convert a few of the X86 aliases from .cpp to .td code. llvm-svn: 117815
2010-10-31 01:36:36 +08:00
//===----------------------------------------------------------------------===//
[x86] Add JMP16[rm],CALL16[rm] instructions, and fix up aliases llvm-svn: 198754
2014-01-08 20:57:49 +08:00
def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>;
def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>;
[asm parser] Add support for predicating MnemonicAlias based on the assembler variant/dialect. Addresses a FIXME in the emitMnemonicAliases function. Use and test case to come shortly. rdar://13688439 and part of PR13340. llvm-svn: 179804
2013-04-19 06:35:36 +08:00
def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>;
use our fancy new MnemonicAlias mechanism to remove a bunch of hacks from X86AsmParser.cpp llvm-svn: 117952
2010-11-02 05:06:34 +08:00
[asm parser] Add support for predicating MnemonicAlias based on the assembler variant/dialect. Addresses a FIXME in the emitMnemonicAliases function. Use and test case to come shortly. rdar://13688439 and part of PR13340. llvm-svn: 179804
2013-04-19 06:35:36 +08:00
def : MnemonicAlias<"cbw", "cbtw", "att">;
def : MnemonicAlias<"cwde", "cwtl", "att">;
def : MnemonicAlias<"cwd", "cwtd", "att">;
def : MnemonicAlias<"cdq", "cltd", "att">;
def : MnemonicAlias<"cdqe", "cltq", "att">;
def : MnemonicAlias<"cqo", "cqto", "att">;
move a bunch more aliases from .cpp -> .td file. llvm-svn: 117819
2010-10-31 02:07:17 +08:00
[x86] Fix retq/retl handling in 64-bit mode This finishes the job started in r198756, and creates separate opcodes for 64-bit vs. 32-bit versions of the rest of the RET instructions too. LRETL/LRETQ are interesting... I can't see any justification for their existence in the SDM. There should be no 'LRETL' in 64-bit mode, and no need for a REX.W prefix for LRETQ. But this is what GAS does, and my Sandybridge CPU and an Opteron 6376 concur when tested as follows: asm __volatile__("pushq $0x1234\nmovq $0x33,%rax\nsalq $32,%rax\norq $1f,%rax\npushq %rax\nlretl $8\n1:"); asm __volatile__("pushq $1234\npushq $0x33\npushq $1f\nlretq $8\n1:"); asm __volatile__("pushq $0x33\npushq $1f\nlretq\n1:"); asm __volatile__("pushq $0x1234\npushq $0x33\npushq $1f\nlretq $8\n1:"); cf. PR8592 and commit r118903, which added LRETQ. I only added LRETIQ to match it. I don't quite understand how the Intel syntax parsing for ret instructions is working, despite r154468 allegedly fixing it. Aren't the explicitly sized 'retw', 'retd' and 'retq' supposed to work? I have at least made the 'lretq' work with (and indeed *require*) the 'q'. llvm-svn: 199106
2014-01-13 22:05:59 +08:00
// In 64-bit mode lret maps to lretl; it is not ambiguous with lretq.
[x86] Disambiguate RET[QL] and fix aliases for 16-bit mode I couldn't see how to do this sanely without splitting RETQ from RETL. Eric says: "sad about the inability to roundtrip them now, but...". I have no idea what that means, but perhaps it wants preserving in the commit comment. llvm-svn: 198756
2014-01-08 20:58:07 +08:00
def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>;
def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>;
accept lret as an alias for lretl, fixing the reopened part of PR8592 llvm-svn: 118916
2010-11-13 02:54:56 +08:00
[x86] Rename In32BitMode predicate to Not64BitMode That's what it actually means, and with 16-bit support it's going to be a little more relevant since in a few corner cases we may actually want to distinguish between 16-bit and 32-bit mode (for example the bare 'push' aliases to pushw/pushl etc.) Patch by David Woodhouse llvm-svn: 197768
2013-12-20 10:04:49 +08:00
def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>;
[asm parser] Add support for predicating MnemonicAlias based on the assembler variant/dialect. Addresses a FIXME in the emitMnemonicAliases function. Use and test case to come shortly. rdar://13688439 and part of PR13340. llvm-svn: 179804
2013-04-19 06:35:36 +08:00
def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>;
Recognize leavel and leaveq aliases for leave. Validate encoding of leave in 64bit mode. llvm-svn: 125795
2011-02-18 07:36:39 +08:00
[asm parser] Add support for predicating MnemonicAlias based on the assembler variant/dialect. Addresses a FIXME in the emitMnemonicAliases function. Use and test case to come shortly. rdar://13688439 and part of PR13340. llvm-svn: 179804
2013-04-19 06:35:36 +08:00
def : MnemonicAlias<"loopz", "loope", "att">;
def : MnemonicAlias<"loopnz", "loopne", "att">;
Recognize loopz and loopnz as aliases for loope and loopne. From Dimitry Andric. llvm-svn: 126168
2011-02-22 08:43:07 +08:00
[x86] Add PUSHA16,POPA16 instructions, and fix aliases for 16-bit mode llvm-svn: 198753
2014-01-08 20:57:45 +08:00
def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>;
def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>;
[asm parser] Add support for predicating MnemonicAlias based on the assembler variant/dialect. Addresses a FIXME in the emitMnemonicAliases function. Use and test case to come shortly. rdar://13688439 and part of PR13340. llvm-svn: 179804
2013-04-19 06:35:36 +08:00
def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>;
[x86] Add PUSHA16,POPA16 instructions, and fix aliases for 16-bit mode llvm-svn: 198753
2014-01-08 20:57:45 +08:00
def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>;
def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>;
[asm parser] Add support for predicating MnemonicAlias based on the assembler variant/dialect. Addresses a FIXME in the emitMnemonicAliases function. Use and test case to come shortly. rdar://13688439 and part of PR13340. llvm-svn: 179804
2013-04-19 06:35:36 +08:00
def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>;
def : MnemonicAlias<"popfd", "popfl", "att">;
move a bunch more aliases from .cpp -> .td file. llvm-svn: 117819
2010-10-31 02:07:17 +08:00
sketch out the planned instruction alias mechanism, add some comments about how the push/pop mnemonic aliases are wrong. llvm-svn: 117857
2010-11-01 02:43:46 +08:00
// FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
// all modes. However: "push (addr)" and "push $42" should default to
// pushl/pushq depending on the current mode. Similar for "pop %bx"
[x86] Add PUSHA16,POPA16 instructions, and fix aliases for 16-bit mode llvm-svn: 198753
2014-01-08 20:57:45 +08:00
def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>;
def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>;
[asm parser] Add support for predicating MnemonicAlias based on the assembler variant/dialect. Addresses a FIXME in the emitMnemonicAliases function. Use and test case to come shortly. rdar://13688439 and part of PR13340. llvm-svn: 179804
2013-04-19 06:35:36 +08:00
def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>;
[x86] Add PUSHA16,POPA16 instructions, and fix aliases for 16-bit mode llvm-svn: 198753
2014-01-08 20:57:45 +08:00
def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>;
def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>;
[asm parser] Add support for predicating MnemonicAlias based on the assembler variant/dialect. Addresses a FIXME in the emitMnemonicAliases function. Use and test case to come shortly. rdar://13688439 and part of PR13340. llvm-svn: 179804
2013-04-19 06:35:36 +08:00
def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
def : MnemonicAlias<"pushfd", "pushfl", "att">;
Implement (and document!) support for MnemonicAlias's to have Requires directives, allowing things like this: def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>; def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>; Move the rest of the X86 MnemonicAliases over to the .td file. llvm-svn: 117830
2010-10-31 03:23:13 +08:00
[x86] Add PUSHA16,POPA16 instructions, and fix aliases for 16-bit mode llvm-svn: 198753
2014-01-08 20:57:45 +08:00
def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>;
def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>;
def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>;
def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>;
def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>;
def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>;
def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>;
def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>;
def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>;
def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>;
[ms-inline asm] Fix a crasher when we fail on a direct match. The issue was that the MatchingInlineAsm and VariantID args to the MatchInstructionImpl function weren't being set properly. Specifically, when parsing intel syntax, the parser thought it was parsing inline assembly in the at&t dialect; that will never be the case. The crash was caused when the emitter tried to emit the instruction, but the operands weren't set. When parsing inline assembly we only set the opcode, not the operands, which is used to lookup the instruction descriptor. rdar://13854391 and PR15945 Also, this commit reverts r176036. Now that we're correctly parsing the intel syntax the pushad/popad don't match properly. I've reimplemented that fix using a MnemonicAlias. llvm-svn: 181620
2013-05-11 02:24:17 +08:00
[asm parser] Add support for predicating MnemonicAlias based on the assembler variant/dialect. Addresses a FIXME in the emitMnemonicAliases function. Use and test case to come shortly. rdar://13688439 and part of PR13340. llvm-svn: 179804
2013-04-19 06:35:36 +08:00
def : MnemonicAlias<"repe", "rep", "att">;
def : MnemonicAlias<"repz", "rep", "att">;
def : MnemonicAlias<"repnz", "repne", "att">;
move rep aliases to td file llvm-svn: 117822
2010-10-31 02:17:33 +08:00
[x86] Disambiguate RET[QL] and fix aliases for 16-bit mode I couldn't see how to do this sanely without splitting RETQ from RETL. Eric says: "sad about the inability to roundtrip them now, but...". I have no idea what that means, but perhaps it wants preserving in the commit comment. llvm-svn: 198756
2014-01-08 20:58:07 +08:00
def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>;
def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>;
def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>;
Implement (and document!) support for MnemonicAlias's to have Requires directives, allowing things like this: def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>; def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>; Move the rest of the X86 MnemonicAliases over to the .td file. llvm-svn: 117830
2010-10-31 03:23:13 +08:00
[asm parser] Add support for predicating MnemonicAlias based on the assembler variant/dialect. Addresses a FIXME in the emitMnemonicAliases function. Use and test case to come shortly. rdar://13688439 and part of PR13340. llvm-svn: 179804
2013-04-19 06:35:36 +08:00
def : MnemonicAlias<"salb", "shlb", "att">;
def : MnemonicAlias<"salw", "shlw", "att">;
def : MnemonicAlias<"sall", "shll", "att">;
def : MnemonicAlias<"salq", "shlq", "att">;
move sal aliases to .td file. llvm-svn: 117821
2010-10-31 02:14:54 +08:00
[asm parser] Add support for predicating MnemonicAlias based on the assembler variant/dialect. Addresses a FIXME in the emitMnemonicAliases function. Use and test case to come shortly. rdar://13688439 and part of PR13340. llvm-svn: 179804
2013-04-19 06:35:36 +08:00
def : MnemonicAlias<"smovb", "movsb", "att">;
def : MnemonicAlias<"smovw", "movsw", "att">;
def : MnemonicAlias<"smovl", "movsl", "att">;
def : MnemonicAlias<"smovq", "movsq", "att">;
implement (and document!) the first kind of MC assembler alias, which just remaps one mnemonic to another. Convert a few of the X86 aliases from .cpp to .td code. llvm-svn: 117815
2010-10-31 01:36:36 +08:00
[asm parser] Add support for predicating MnemonicAlias based on the assembler variant/dialect. Addresses a FIXME in the emitMnemonicAliases function. Use and test case to come shortly. rdar://13688439 and part of PR13340. llvm-svn: 179804
2013-04-19 06:35:36 +08:00
def : MnemonicAlias<"ud2a", "ud2", "att">;
def : MnemonicAlias<"verrw", "verr", "att">;
implement (and document!) the first kind of MC assembler alias, which just remaps one mnemonic to another. Convert a few of the X86 aliases from .cpp to .td code. llvm-svn: 117815
2010-10-31 01:36:36 +08:00
use our fancy new MnemonicAlias mechanism to remove a bunch of hacks from X86AsmParser.cpp llvm-svn: 117952
2010-11-02 05:06:34 +08:00
// System instruction aliases.
[x86] Disambiguate RET[QL] and fix aliases for 16-bit mode I couldn't see how to do this sanely without splitting RETQ from RETL. Eric says: "sad about the inability to roundtrip them now, but...". I have no idea what that means, but perhaps it wants preserving in the commit comment. llvm-svn: 198756
2014-01-08 20:58:07 +08:00
def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>;
def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>;
[asm parser] Add support for predicating MnemonicAlias based on the assembler variant/dialect. Addresses a FIXME in the emitMnemonicAliases function. Use and test case to come shortly. rdar://13688439 and part of PR13340. llvm-svn: 179804
2013-04-19 06:35:36 +08:00
def : MnemonicAlias<"sysret", "sysretl", "att">;
def : MnemonicAlias<"sysexit", "sysexitl", "att">;
use our fancy new MnemonicAlias mechanism to remove a bunch of hacks from X86AsmParser.cpp llvm-svn: 117952
2010-11-02 05:06:34 +08:00
[x86] Disambiguate [LS][IG]DT{32,64}m and add 16-bit versions, fix aliases llvm-svn: 198755
2014-01-08 20:57:55 +08:00
def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>;
def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>;
def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>;
def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>;
def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>;
def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>;
def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>;
def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>;
def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>;
def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>;
def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>;
def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>;
use our fancy new MnemonicAlias mechanism to remove a bunch of hacks from X86AsmParser.cpp llvm-svn: 117952
2010-11-02 05:06:34 +08:00
implement (and document!) the first kind of MC assembler alias, which just remaps one mnemonic to another. Convert a few of the X86 aliases from .cpp to .td code. llvm-svn: 117815
2010-10-31 01:36:36 +08:00
move a bunch more aliases from .cpp -> .td file. llvm-svn: 117819
2010-10-31 02:07:17 +08:00
// Floating point stack aliases.
[asm parser] Add support for predicating MnemonicAlias based on the assembler variant/dialect. Addresses a FIXME in the emitMnemonicAliases function. Use and test case to come shortly. rdar://13688439 and part of PR13340. llvm-svn: 179804
2013-04-19 06:35:36 +08:00
def : MnemonicAlias<"fcmovz", "fcmove", "att">;
def : MnemonicAlias<"fcmova", "fcmovnbe", "att">;
def : MnemonicAlias<"fcmovnae", "fcmovb", "att">;
def : MnemonicAlias<"fcmovna", "fcmovbe", "att">;
def : MnemonicAlias<"fcmovae", "fcmovnb", "att">;
def : MnemonicAlias<"fcomip", "fcompi", "att">;
def : MnemonicAlias<"fildq", "fildll", "att">;
def : MnemonicAlias<"fistpq", "fistpll", "att">;
def : MnemonicAlias<"fisttpq", "fisttpll", "att">;
def : MnemonicAlias<"fldcww", "fldcw", "att">;
def : MnemonicAlias<"fnstcww", "fnstcw", "att">;
def : MnemonicAlias<"fnstsww", "fnstsw", "att">;
def : MnemonicAlias<"fucomip", "fucompi", "att">;
[x86 asm] allow fwait alias in both At&t and Intel modes (PR21208) Differential Revision: http://reviews.llvm.org/D5741 llvm-svn: 219725
2014-10-15 05:41:17 +08:00
def : MnemonicAlias<"fwait", "wait">;
move a bunch more aliases from .cpp -> .td file. llvm-svn: 117819
2010-10-31 02:07:17 +08:00
X86: Make the cmov aliases work with intel syntax too. llvm-svn: 183907
2013-06-13 23:45:24 +08:00
class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond,
string VariantName>
move cmov aliases to .td file. llvm-svn: 117818
2010-10-31 01:56:50 +08:00
: MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
X86: Make the cmov aliases work with intel syntax too. llvm-svn: 183907
2013-06-13 23:45:24 +08:00
!strconcat(Prefix, NewCond, Suffix), VariantName>;
move setcc and jcc aliases from .cpp to .td llvm-svn: 117817
2010-10-31 01:51:45 +08:00
/// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
/// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
/// example "setz" -> "sete".
X86: Make the cmov aliases work with intel syntax too. llvm-svn: 183907
2013-06-13 23:45:24 +08:00
multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix,
string V = ""> {
def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb
def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete
def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe
def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae
def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae
def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle
def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge
def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne
def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp
def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp
def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb
def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta
def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl
def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg
move setcc and jcc aliases from .cpp to .td llvm-svn: 117817
2010-10-31 01:51:45 +08:00
}
// Aliases for set<CC>
move cmov aliases to .td file. llvm-svn: 117818
2010-10-31 01:56:50 +08:00
defm : IntegerCondCodeMnemonicAlias<"set", "">;
move setcc and jcc aliases from .cpp to .td llvm-svn: 117817
2010-10-31 01:51:45 +08:00
// Aliases for j<CC>
move cmov aliases to .td file. llvm-svn: 117818
2010-10-31 01:56:50 +08:00
defm : IntegerCondCodeMnemonicAlias<"j", "">;
// Aliases for cmov<CC>{w,l,q}
X86: Make the cmov aliases work with intel syntax too. llvm-svn: 183907
2013-06-13 23:45:24 +08:00
defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">;
defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">;
defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">;
// No size suffix for intel-style asm.
defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">;
implement (and document!) the first kind of MC assembler alias, which just remaps one mnemonic to another. Convert a few of the X86 aliases from .cpp to .td code. llvm-svn: 117815
2010-10-31 01:36:36 +08:00
rearrange a bit. llvm-svn: 117967
2010-11-02 07:07:52 +08:00
//===----------------------------------------------------------------------===//
// Assembler Instruction Aliases
//===----------------------------------------------------------------------===//
generalize alias support to allow the result of an alias to add fixed immediate values. Move the aad and aam aliases to use this, and document it. llvm-svn: 118350
2010-11-07 03:25:43 +08:00
// aad/aam default to base 10 if no operand is specified.
def : InstAlias<"aad", (AAD8i8 10)>;
def : InstAlias<"aam", (AAM8i8 10)>;
implement PR9264: disambiguating 'bt mem, imm' as a btl. This is reasonable to do since all bt-mem forms do the same thing. llvm-svn: 126047
2011-02-20 05:06:36 +08:00
// Disambiguate the mem/imm form of bt-without-a-suffix as btl.
Add aliases to map 'imm, mem' form of x86 bts/btr/btc without a size suffix to their 32-bit forms. This makes them consistent with 'bt' which already had this handling. gas has the same behavior. There have been discussions on the mailing list about determining size based on the immediate, but my goal here was just to remove the inconsistency. llvm-svn: 186904
2013-07-23 08:56:15 +08:00
// Likewise for btc/btr/bts.
Reverse operands for Intel syntax form of 'bt' alias. llvm-svn: 186809
2013-07-22 15:47:51 +08:00
def : InstAlias<"bt {$imm, $mem|$mem, $imm}",
(BT32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
Add aliases to map 'imm, mem' form of x86 bts/btr/btc without a size suffix to their 32-bit forms. This makes them consistent with 'bt' which already had this handling. gas has the same behavior. There have been discussions on the mailing list about determining size based on the immediate, but my goal here was just to remove the inconsistency. llvm-svn: 186904
2013-07-23 08:56:15 +08:00
def : InstAlias<"btc {$imm, $mem|$mem, $imm}",
(BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
def : InstAlias<"btr {$imm, $mem|$mem, $imm}",
(BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
def : InstAlias<"bts {$imm, $mem|$mem, $imm}",
(BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
implement PR9264: disambiguating 'bt mem, imm' as a btl. This is reasonable to do since all bt-mem forms do the same thing. llvm-svn: 126047
2011-02-20 05:06:36 +08:00
fix some bugs in the alias support, unblocking changing of "clr" aliases from c++ hacks to proper .td InstAlias definitions. Change them! llvm-svn: 118330
2010-11-06 15:31:43 +08:00
// clr aliases.
Explicitly don't let the asm printer use the clrb/w/l aliases for xor %reg, %reg. It only didn't use it before because it seems InstAlias handling in the asm printer fails to count tied operands so it tried to find an xor with 2 operands instead of the 3 it wfails to count tied. llvm-svn: 186900
2013-07-23 08:15:19 +08:00
def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>;
def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg), 0>;
def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>;
def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>;
fix some bugs in the alias support, unblocking changing of "clr" aliases from c++ hacks to proper .td InstAlias definitions. Change them! llvm-svn: 118330
2010-11-06 15:31:43 +08:00
[x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385) llvm-svn: 199803
2014-01-22 23:08:08 +08:00
// lods aliases. Accept the destination being omitted because it's implicit
// in the mnemonic, or the mnemonic suffix being omitted because it's implicit
// in the destination.
def : InstAlias<"lodsb $src", (LODSB srcidx8:$src), 0>;
def : InstAlias<"lodsw $src", (LODSW srcidx16:$src), 0>;
def : InstAlias<"lods{l|d} $src", (LODSL srcidx32:$src), 0>;
def : InstAlias<"lodsq $src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
def : InstAlias<"lods {$src, %al|al, $src}", (LODSB srcidx8:$src), 0>;
def : InstAlias<"lods {$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>;
def : InstAlias<"lods {$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>;
def : InstAlias<"lods {$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
[x86] Allow address-size overrides for STOS[BWLQ] (PR9385) llvm-svn: 199804
2014-01-22 23:08:21 +08:00
// stos aliases. Accept the source being omitted because it's implicit in
// the mnemonic, or the mnemonic suffix being omitted because it's implicit
// in the source.
def : InstAlias<"stosb $dst", (STOSB dstidx8:$dst), 0>;
def : InstAlias<"stosw $dst", (STOSW dstidx16:$dst), 0>;
def : InstAlias<"stos{l|d} $dst", (STOSL dstidx32:$dst), 0>;
def : InstAlias<"stosq $dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
def : InstAlias<"stos {%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>;
def : InstAlias<"stos {%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>;
def : InstAlias<"stos {%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>;
def : InstAlias<"stos {%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
[x86] Allow address-size overrides for SCAS{8,16,32,64} (PR9385) llvm-svn: 199805
2014-01-22 23:08:27 +08:00
// scas aliases. Accept the destination being omitted because it's implicit
// in the mnemonic, or the mnemonic suffix being omitted because it's implicit
// in the destination.
[X86] Fix Uses/Defs lists for INS, OUTS, SCAS, CMPS, LODS llvm-svn: 202348
2014-02-27 13:08:25 +08:00
def : InstAlias<"scasb $dst", (SCASB dstidx8:$dst), 0>;
def : InstAlias<"scasw $dst", (SCASW dstidx16:$dst), 0>;
def : InstAlias<"scas{l|d} $dst", (SCASL dstidx32:$dst), 0>;
def : InstAlias<"scasq $dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
def : InstAlias<"scas {$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>;
def : InstAlias<"scas {$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>;
def : InstAlias<"scas {$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>;
def : InstAlias<"scas {$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
[x86] Allow address-size overrides for SCAS{8,16,32,64} (PR9385) llvm-svn: 199805
2014-01-22 23:08:27 +08:00
implement aliases for div/idiv that have an explicit A register operand, implementing rdar://8431864 llvm-svn: 118364
2010-11-07 06:41:18 +08:00
// div and idiv aliases for explicit A register.
Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax. Patch by Richard Mitton. llvm-svn: 187476
2013-07-31 10:47:52 +08:00
def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>;
def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>;
def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>;
def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>;
def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>;
def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>;
def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>;
def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>;
def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>;
def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>;
def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>;
def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>;
def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>;
def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>;
def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>;
def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>;
implement aliases for div/idiv that have an explicit A register operand, implementing rdar://8431864 llvm-svn: 118364
2010-11-07 06:41:18 +08:00
move the plethora of fp stack aliases to the .td file. llvm-svn: 118353
2010-11-07 04:47:38 +08:00
// Various unary fpstack operations default to operating on on ST1.
// For example, "fxch" -> "fxch %st(1)"
Have the X86 back-end emit the alias instead of what's being aliased. In most cases, it's much nicer and more informative reading the alias. llvm-svn: 129497
2011-04-14 09:11:51 +08:00
def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
Fix more Intel syntax issues with FP instruction aliases. Test cases coming in a subsequent patch. llvm-svn: 187187
2013-07-26 13:37:46 +08:00
def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>;
def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>;
Suppress argumentless aliases for some x86 FP operations from being used by the asm writer. Prefer to use the explicit %st(1) form. llvm-svn: 186897
2013-07-23 08:03:33 +08:00
def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>;
Fix more Intel syntax issues with FP instruction aliases. Test cases coming in a subsequent patch. llvm-svn: 187187
2013-07-26 13:37:46 +08:00
def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>;
def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>;
Suppress argumentless aliases for some x86 FP operations from being used by the asm writer. Prefer to use the explicit %st(1) form. llvm-svn: 186897
2013-07-23 08:03:33 +08:00
def : InstAlias<"fxch", (XCH_F ST1), 0>;
def : InstAlias<"fcom", (COM_FST0r ST1), 0>;
def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>;
def : InstAlias<"fcomi", (COM_FIr ST1), 0>;
def : InstAlias<"fcompi", (COM_FIPr ST1), 0>;
def : InstAlias<"fucom", (UCOM_Fr ST1), 0>;
def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>;
def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>;
def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>;
move the plethora of fp stack aliases to the .td file. llvm-svn: 118353
2010-11-07 04:47:38 +08:00
// Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
// For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
// instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
// gas.
Have the X86 back-end emit the alias instead of what's being aliased. In most cases, it's much nicer and more informative reading the alias. llvm-svn: 129497
2011-04-14 09:11:51 +08:00
multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax. Patch by Richard Mitton. llvm-svn: 187476
2013-07-31 10:47:52 +08:00
def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"),
Have the X86 back-end emit the alias instead of what's being aliased. In most cases, it's much nicer and more informative reading the alias. llvm-svn: 129497
2011-04-14 09:11:51 +08:00
(Inst RST:$op), EmitAlias>;
Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax. Patch by Richard Mitton. llvm-svn: 187476
2013-07-31 10:47:52 +08:00
def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"),
Have the X86 back-end emit the alias instead of what's being aliased. In most cases, it's much nicer and more informative reading the alias. llvm-svn: 129497
2011-04-14 09:11:51 +08:00
(Inst ST0), EmitAlias>;
move the plethora of fp stack aliases to the .td file. llvm-svn: 118353
2010-11-07 04:47:38 +08:00
}
defm : FpUnaryAlias<"fadd", ADD_FST0r>;
Have the X86 back-end emit the alias instead of what's being aliased. In most cases, it's much nicer and more informative reading the alias. llvm-svn: 129497
2011-04-14 09:11:51 +08:00
defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
move the plethora of fp stack aliases to the .td file. llvm-svn: 118353
2010-11-07 04:47:38 +08:00
defm : FpUnaryAlias<"fsub", SUB_FST0r>;
Fix more Intel syntax issues with FP instruction aliases. Test cases coming in a subsequent patch. llvm-svn: 187187
2013-07-26 13:37:46 +08:00
defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>;
move the plethora of fp stack aliases to the .td file. llvm-svn: 118353
2010-11-07 04:47:38 +08:00
defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
Fix more Intel syntax issues with FP instruction aliases. Test cases coming in a subsequent patch. llvm-svn: 187187
2013-07-26 13:37:46 +08:00
defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>;
move the plethora of fp stack aliases to the .td file. llvm-svn: 118353
2010-11-07 04:47:38 +08:00
defm : FpUnaryAlias<"fmul", MUL_FST0r>;
defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
Fix more Intel syntax issues with FP instruction aliases. Test cases coming in a subsequent patch. llvm-svn: 187187
2013-07-26 13:37:46 +08:00
defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>;
move the plethora of fp stack aliases to the .td file. llvm-svn: 118353
2010-11-07 04:47:38 +08:00
defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
Fix more Intel syntax issues with FP instruction aliases. Test cases coming in a subsequent patch. llvm-svn: 187187
2013-07-26 13:37:46 +08:00
defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>;
Have the X86 back-end emit the alias instead of what's being aliased. In most cases, it's much nicer and more informative reading the alias. llvm-svn: 129497
2011-04-14 09:11:51 +08:00
defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
go to great lengths to work around a GAS bug my previous patch exposed: GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)" even though st(0) is implicit in all other fp stack instructions. Fortunately, there is an alias for fcomip named "fcompi" and gas does accept the default argument for the alias (boggle!). As such, switch the canonical form of this instruction to "pi" instead of "ip". This makes the code generator and disassembler generate pi, avoiding the gas bug. llvm-svn: 118356
2010-11-07 05:37:06 +08:00
defm : FpUnaryAlias<"fcompi", COM_FIPr>;
defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
change the fp comparison instructions to not have %st0 explicitly listed in its asm string, for consistency with the other similar instructions. llvm-svn: 118354
2010-11-07 04:55:09 +08:00
move the plethora of fp stack aliases to the .td file. llvm-svn: 118353
2010-11-07 04:47:38 +08:00
// Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
Add another non-commutable instruction that gas accepts commuted forms for. Fixes PR8861. llvm-svn: 122641
2010-12-31 06:10:49 +08:00
// commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
// solely because gas supports it.
Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax. Patch by Richard Mitton. llvm-svn: 187476
2013-07-31 10:47:52 +08:00
def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>;
def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>;
def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>;
def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>;
def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>;
def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>;
add (and document) the ability for alias results to have fixed physical registers. Start moving fp comparison aliases to the .td file (which default to using %st1 if nothing is specified). llvm-svn: 118352
2010-11-07 03:57:21 +08:00
Add another non-commutable instruction that gas accepts commuted forms for. Fixes PR8861. llvm-svn: 122641
2010-12-31 06:10:49 +08:00
// We accept "fnstsw %eax" even though it only writes %ax.
Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax. Patch by Richard Mitton. llvm-svn: 187476
2013-07-31 10:47:52 +08:00
def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>;
def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>;
X86: Don't emit conditional floating point moves on when targeting pre-pentiumpro architectures. * Model FPSW (the FPU status word) as a register. * Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions. * During Legalize/Lowering, build a node sequence to transfer the comparison result from FPSW into EFLAGS. If you're wondering about the right-shift: That's an implicit sub-register extraction (%ax -> %ah) which is handled later on by the instruction selector. Fixes PR6679. Patch by Christoph Erhardt! llvm-svn: 155704
2012-04-27 20:07:43 +08:00
def : InstAlias<"fnstsw" , (FNSTSW16r)>;
move fnstsw aliases to .td file, fix typo llvm-svn: 118349
2010-11-07 02:58:32 +08:00
move the lcall/ljmp aliases to the .td file. llvm-svn: 118332
2010-11-06 15:48:45 +08:00
// lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
// this is compatible with what GAS does.
TableGen: use correct MIOperand when printing aliases Previously, TableGen assumed that every aliased operand consumed precisely 1 MachineInstr slot (this was reasonable because until a couple of days ago, nothing more complicated was eligible for printing). This allows a couple more ARM64 aliases to print so we can remove the special code. On the X86 side, I've gone for explicit AT&T size specifiers as the default, so turned off a few of the aliases that would have just started printing. llvm-svn: 208880
2014-05-15 21:36:01 +08:00
def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
[X86] Remove '*' from asm strings in far call/jump aliases for Intel syntax. llvm-svn: 224685
2014-12-21 07:05:55 +08:00
def : InstAlias<"lcall {*}$dst", (FARCALL32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
def : InstAlias<"ljmp {*}$dst", (FARJMP32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
TableGen: use correct MIOperand when printing aliases Previously, TableGen assumed that every aliased operand consumed precisely 1 MachineInstr slot (this was reasonable because until a couple of days ago, nothing more complicated was eligible for printing). This allows a couple more ARM64 aliases to print so we can remove the special code. On the X86 side, I've gone for explicit AT&T size specifiers as the default, so turned off a few of the aliases that would have just started printing. llvm-svn: 208880
2014-05-15 21:36:01 +08:00
def : InstAlias<"lcall $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
def : InstAlias<"ljmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
[X86] Remove '*' from asm strings in far call/jump aliases for Intel syntax. llvm-svn: 224685
2014-12-21 07:05:55 +08:00
def : InstAlias<"lcall {*}$dst", (FARCALL16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
def : InstAlias<"ljmp {*}$dst", (FARJMP16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
def : InstAlias<"call {*}$dst", (CALL64m i64mem:$dst), 0>, Requires<[In64BitMode]>;
def : InstAlias<"jmp {*}$dst", (JMP64m i64mem:$dst), 0>, Requires<[In64BitMode]>;
def : InstAlias<"call {*}$dst", (CALL32m i32mem:$dst), 0>, Requires<[In32BitMode]>;
def : InstAlias<"jmp {*}$dst", (JMP32m i32mem:$dst), 0>, Requires<[In32BitMode]>;
def : InstAlias<"call {*}$dst", (CALL16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
def : InstAlias<"jmp {*}$dst", (JMP16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
[x86] Add JMP16[rm],CALL16[rm] instructions, and fix up aliases llvm-svn: 198754
2014-01-08 20:57:49 +08:00
move the lcall/ljmp aliases to the .td file. llvm-svn: 118332
2010-11-06 15:48:45 +08:00
move sldt, imul, and movabsq aliases from c++ to .td file. llvm-svn: 118347
2010-11-07 02:44:26 +08:00
// "imul <imm>, B" is an alias for "imul <imm>, B, B".
[X86] Swap operand order of imul aliases in Intel syntax. Also disable printing of the alias instead of the real instruction. llvm-svn: 224686
2014-12-21 07:05:57 +08:00
def : InstAlias<"imulw {$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>;
def : InstAlias<"imulw {$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>;
def : InstAlias<"imull {$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>;
def : InstAlias<"imull {$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>;
def : InstAlias<"imulq {$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>;
def : InstAlias<"imulq {$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>;
move sldt, imul, and movabsq aliases from c++ to .td file. llvm-svn: 118347
2010-11-07 02:44:26 +08:00
move in/out aliases to the .td files. llvm-svn: 118348
2010-11-07 02:52:40 +08:00
// inb %dx -> inb %al, %dx
Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax. Patch by Richard Mitton. llvm-svn: 187476
2013-07-31 10:47:52 +08:00
def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>;
def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>;
def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>;
Recommit r186813: More Intel syntax alias fixes. With the addition of suppressing some of the aliases from being emitted by the asm printer. llvm-svn: 186869
2013-07-23 04:46:37 +08:00
def : InstAlias<"inb\t$port", (IN8ri i8imm:$port), 0>;
def : InstAlias<"inw\t$port", (IN16ri i8imm:$port), 0>;
def : InstAlias<"inl\t$port", (IN32ri i8imm:$port), 0>;
move in/out aliases to the .td files. llvm-svn: 118348
2010-11-07 02:52:40 +08:00
move sldt, imul, and movabsq aliases from c++ to .td file. llvm-svn: 118347
2010-11-07 02:44:26 +08:00
move the lcall/ljmp aliases to the .td file. llvm-svn: 118332
2010-11-06 15:48:45 +08:00
// jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
[x86] Add JMP16[rm],CALL16[rm] instructions, and fix up aliases llvm-svn: 198754
2014-01-08 20:57:49 +08:00
def : InstAlias<"call $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
def : InstAlias<"jmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
move the lcall/ljmp aliases to the .td file. llvm-svn: 118332
2010-11-06 15:48:45 +08:00
def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
add aliases for movs between seg registers and mem. There are multiple different forms of this instruction (movw/movl/movq) which we reported as being ambiguous. Since they all do the same thing, gas just picks the one with the shortest encoding. Follow its lead here. This implements rdar://8208615 llvm-svn: 118362
2010-11-07 06:35:34 +08:00
// Force mov without a suffix with a segment and mem to prefer the 'l' form of
// the move. All segment/mem forms are equivalent, this has the shortest
// encoding.
X86: disable printing of bare "mov" aliases In AT&T syntax, we should probably print the full "movl" or "movw". TableGen used to ignore these aliases because it was miscounting the number of operands. This fixes the issue. This will be tested when the TableGen "should I print this Alias" heuristic is fixed (very soon). llvm-svn: 208963
2014-05-16 17:41:26 +08:00
def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem), 0>;
def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg), 0>;
move the lcall/ljmp aliases to the .td file. llvm-svn: 118332
2010-11-06 15:48:45 +08:00
move sldt, imul, and movabsq aliases from c++ to .td file. llvm-svn: 118347
2010-11-07 02:44:26 +08:00
// Match 'movq <largeimm>, <reg>' as an alias for movabsq.
X86: disable printing of bare "mov" aliases In AT&T syntax, we should probably print the full "movl" or "movw". TableGen used to ignore these aliases because it was miscounting the number of operands. This fixes the issue. This will be tested when the TableGen "should I print this Alias" heuristic is fixed (very soon). llvm-svn: 208963
2014-05-16 17:41:26 +08:00
def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm), 0>;
move sldt, imul, and movabsq aliases from c++ to .td file. llvm-svn: 118347
2010-11-07 02:44:26 +08:00
implement PR8524, apparently mainline gas accepts movq as an alias for movd when transfering between i64 gprs and mmx regs. llvm-svn: 119931
2010-11-21 16:18:57 +08:00
// Match 'movq GR64, MMX' as an alias for movd.
Add an option to not print the alias of an instruction. It defaults to "print the alias". llvm-svn: 129485
2011-04-14 07:36:21 +08:00
def : InstAlias<"movq $src, $dst",
Have the X86 back-end emit the alias instead of what's being aliased. In most cases, it's much nicer and more informative reading the alias. llvm-svn: 129497
2011-04-14 09:11:51 +08:00
(MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
Add an option to not print the alias of an instruction. It defaults to "print the alias". llvm-svn: 129485
2011-04-14 07:36:21 +08:00
def : InstAlias<"movq $src, $dst",
Have the X86 back-end emit the alias instead of what's being aliased. In most cases, it's much nicer and more informative reading the alias. llvm-svn: 129497
2011-04-14 09:11:51 +08:00
(MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
implement PR8524, apparently mainline gas accepts movq as an alias for movd when transfering between i64 gprs and mmx regs. llvm-svn: 119931
2010-11-21 16:18:57 +08:00
rearrange a bit. llvm-svn: 117967
2010-11-02 07:07:52 +08:00
// movsx aliases
Re-commit 131641 with fixes; de-pseudoize MOVSX16rr8 and friends. rdar://problem/8614450 llvm-svn: 131746
2011-05-21 03:04:40 +08:00
def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
As Dan pointed out, movzbl, movsbl, and friends are nicer than their alias (movzx/movsx) because they give more information. Revert that part of the patch. llvm-svn: 129498
2011-04-14 09:46:37 +08:00
def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
rearrange a bit. llvm-svn: 117967
2010-11-02 07:07:52 +08:00
// movzx aliases
Re-commit 131641 with fixes; de-pseudoize MOVSX16rr8 and friends. rdar://problem/8614450 llvm-svn: 131746
2011-05-21 03:04:40 +08:00
def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
As Dan pointed out, movzbl, movsbl, and friends are nicer than their alias (movzx/movsx) because they give more information. Revert that part of the patch. llvm-svn: 129498
2011-04-14 09:46:37 +08:00
def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
rearrange a bit. llvm-svn: 117967
2010-11-02 07:07:52 +08:00
// Note: No GR32->GR64 movzx form.
move in/out aliases to the .td files. llvm-svn: 118348
2010-11-07 02:52:40 +08:00
// outb %dx -> outb %al, %dx
Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax. Patch by Richard Mitton. llvm-svn: 187476
2013-07-31 10:47:52 +08:00
def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>;
def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>;
def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>;
Recommit r186813: More Intel syntax alias fixes. With the addition of suppressing some of the aliases from being emitted by the asm printer. llvm-svn: 186869
2013-07-23 04:46:37 +08:00
def : InstAlias<"outb\t$port", (OUT8ir i8imm:$port), 0>;
def : InstAlias<"outw\t$port", (OUT16ir i8imm:$port), 0>;
def : InstAlias<"outl\t$port", (OUT32ir i8imm:$port), 0>;
move in/out aliases to the .td files. llvm-svn: 118348
2010-11-07 02:52:40 +08:00
move sldt, imul, and movabsq aliases from c++ to .td file. llvm-svn: 118347
2010-11-07 02:44:26 +08:00
// 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
// effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
// errors, since its encoding is the most compact.
TableGen: use correct MIOperand when printing aliases Previously, TableGen assumed that every aliased operand consumed precisely 1 MachineInstr slot (this was reasonable because until a couple of days ago, nothing more complicated was eligible for printing). This allows a couple more ARM64 aliases to print so we can remove the special code. On the X86 side, I've gone for explicit AT&T size specifiers as the default, so turned off a few of the aliases that would have just started printing. llvm-svn: 208880
2014-05-15 21:36:01 +08:00
def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>;
move sldt, imul, and movabsq aliases from c++ to .td file. llvm-svn: 118347
2010-11-07 02:44:26 +08:00
Make aliases for shld and shrd match gas. PR12173. llvm-svn: 152014
2012-03-05 12:31:54 +08:00
// shld/shrd op,op -> shld op, op, CL
Fix aliases for shrd/shld to handle Intel syntax properly. Also suppress them from being used by the asm printer. llvm-svn: 187020
2013-07-24 12:38:13 +08:00
def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>;
def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>;
def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>;
def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>;
def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>;
def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>;
def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>;
def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>;
def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>;
def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>;
def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>;
def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>;
move the "sh[lr]d op,op" -> "shld $1, op,op" aliases to the .td file. llvm-svn: 118361
2010-11-07 06:25:39 +08:00
/* FIXME: This is disabled because the asm matcher is currently incapable of
* matching a fixed immediate like $1.
work-in-progress llvm-svn: 118358
2010-11-07 06:05:43 +08:00
// "shl X, $1" is an alias for "shl X".
multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
rework the rotate-by-1 instructions to be defined like the shift-by-1 instructions, where the asmstring doesn't contain the implicit 1. It turns out that a bunch of these rotate instructions were completely broken because they used 1 instead of $1. This fixes assembly mismatches on "rclb $1, %bl" and friends, where we used to generate the 3 byte form, we now generate the proper 2-byte form. llvm-svn: 118355
2010-11-07 05:23:40 +08:00
def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
(!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
(!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
(!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
(!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
(!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
(!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
(!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
(!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
}
work-in-progress llvm-svn: 118358
2010-11-07 06:05:43 +08:00
defm : ShiftRotateByOneAlias<"rcl", "RCL">;
defm : ShiftRotateByOneAlias<"rcr", "RCR">;
defm : ShiftRotateByOneAlias<"rol", "ROL">;
defm : ShiftRotateByOneAlias<"ror", "ROR">;
move the "sh[lr]d op,op" -> "shld $1, op,op" aliases to the .td file. llvm-svn: 118361
2010-11-07 06:25:39 +08:00
FIXME */
rework the rotate-by-1 instructions to be defined like the shift-by-1 instructions, where the asmstring doesn't contain the implicit 1. It turns out that a bunch of these rotate instructions were completely broken because they used 1 instead of $1. This fixes assembly mismatches on "rclb $1, %bl" and friends, where we used to generate the 3 byte form, we now generate the proper 2-byte form. llvm-svn: 118355
2010-11-07 05:23:40 +08:00
fix a bug where we had an implicit assumption that the result instruction operand numbering matched the result pattern. Fixing this allows us to move the xchg/test aliases to the .td file. llvm-svn: 118334
2010-11-06 16:20:59 +08:00
// test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
TableGen/ARM64: print aliases even if they have syntax variants. To get at least one use of the change (and some actual tests) in with its commit, I've enabled the AArch64 & ARM64 NEON mov aliases. llvm-svn: 208867
2014-05-15 19:16:32 +08:00
def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}",
(TEST8rm GR8 :$val, i8mem :$mem), 0>;
def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}",
(TEST16rm GR16:$val, i16mem:$mem), 0>;
def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}",
(TEST32rm GR32:$val, i32mem:$mem), 0>;
def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}",
(TEST64rm GR64:$val, i64mem:$mem), 0>;
fix a bug where we had an implicit assumption that the result instruction operand numbering matched the result pattern. Fixing this allows us to move the xchg/test aliases to the .td file. llvm-svn: 118334
2010-11-06 16:20:59 +08:00
// xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
TableGen/ARM64: print aliases even if they have syntax variants. To get at least one use of the change (and some actual tests) in with its commit, I've enabled the AArch64 & ARM64 NEON mov aliases. llvm-svn: 208867
2014-05-15 19:16:32 +08:00
def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}",
(XCHG8rm GR8 :$val, i8mem :$mem), 0>;
def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}",
(XCHG16rm GR16:$val, i16mem:$mem), 0>;
def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}",
(XCHG32rm GR32:$val, i32mem:$mem), 0>;
def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}",
(XCHG64rm GR64:$val, i64mem:$mem), 0>;
Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax. llvm-svn: 141274
2011-10-06 14:44:41 +08:00
// xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
TableGen/ARM64: print aliases even if they have syntax variants. To get at least one use of the change (and some actual tests) in with its commit, I've enabled the AArch64 & ARM64 NEON mov aliases. llvm-svn: 208867
2014-05-15 19:16:32 +08:00
def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>;
def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}",
(XCHG32ar GR32:$src), 0>, Requires<[Not64BitMode]>;
def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}",
(XCHG32ar64 GR32_NOAX:$src), 0>, Requires<[In64BitMode]>;
def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>;