2016-12-10 06:06:55 +08:00
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//===-- SIMachineScheduler.h - SI Scheduler Interface -----------*- C++ -*-===//
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2016-01-14 00:10:10 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief SI Machine Scheduler interface
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINESCHEDULER_H
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#define LLVM_LIB_TARGET_AMDGPU_SIMACHINESCHEDULER_H
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#include "SIInstrInfo.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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#include "llvm/CodeGen/RegisterPressure.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include <cassert>
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#include <cstdint>
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#include <map>
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#include <memory>
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#include <set>
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#include <vector>
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namespace llvm {
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enum SIScheduleCandReason {
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NoCand,
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RegUsage,
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Latency,
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Successor,
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Depth,
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NodeOrder
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};
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struct SISchedulerCandidate {
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// The reason for this candidate.
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SIScheduleCandReason Reason = NoCand;
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// Set of reasons that apply to multiple candidates.
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uint32_t RepeatReasonSet = 0;
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SISchedulerCandidate() = default;
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bool isRepeat(SIScheduleCandReason R) { return RepeatReasonSet & (1 << R); }
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void setRepeat(SIScheduleCandReason R) { RepeatReasonSet |= (1 << R); }
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};
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class SIScheduleDAGMI;
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class SIScheduleBlockCreator;
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class SIScheduleBlock {
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SIScheduleDAGMI *DAG;
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SIScheduleBlockCreator *BC;
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std::vector<SUnit*> SUnits;
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std::map<unsigned, unsigned> NodeNum2Index;
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std::vector<SUnit*> TopReadySUs;
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std::vector<SUnit*> ScheduledSUnits;
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/// The top of the unscheduled zone.
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IntervalPressure TopPressure;
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RegPressureTracker TopRPTracker;
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// Pressure: number of said class of registers needed to
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// store the live virtual and real registers.
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// We do care only of SGPR32 and VGPR32 and do track only virtual registers.
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// Pressure of additional registers required inside the block.
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std::vector<unsigned> InternalAdditionnalPressure;
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// Pressure of input and output registers
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std::vector<unsigned> LiveInPressure;
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std::vector<unsigned> LiveOutPressure;
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// Registers required by the block, and outputs.
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// We do track only virtual registers.
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// Note that some registers are not 32 bits,
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// and thus the pressure is not equal
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// to the number of live registers.
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std::set<unsigned> LiveInRegs;
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std::set<unsigned> LiveOutRegs;
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bool Scheduled = false;
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bool HighLatencyBlock = false;
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std::vector<unsigned> HasLowLatencyNonWaitedParent;
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// Unique ID, the index of the Block in the SIScheduleDAGMI Blocks table.
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unsigned ID;
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std::vector<SIScheduleBlock*> Preds; // All blocks predecessors.
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std::vector<SIScheduleBlock*> Succs; // All blocks successors.
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unsigned NumHighLatencySuccessors = 0;
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public:
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SIScheduleBlock(SIScheduleDAGMI *DAG, SIScheduleBlockCreator *BC,
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unsigned ID):
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DAG(DAG), BC(BC), TopRPTracker(TopPressure), ID(ID) {}
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~SIScheduleBlock() = default;
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unsigned getID() const { return ID; }
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/// Functions for Block construction.
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void addUnit(SUnit *SU);
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// When all SUs have been added.
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void finalizeUnits();
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// Add block pred, which has instruction predecessor of SU.
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void addPred(SIScheduleBlock *Pred);
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void addSucc(SIScheduleBlock *Succ);
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const std::vector<SIScheduleBlock*>& getPreds() const { return Preds; }
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const std::vector<SIScheduleBlock*>& getSuccs() const { return Succs; }
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unsigned Height; // Maximum topdown path length to block without outputs
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unsigned Depth; // Maximum bottomup path length to block without inputs
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unsigned getNumHighLatencySuccessors() const {
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return NumHighLatencySuccessors;
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}
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bool isHighLatencyBlock() { return HighLatencyBlock; }
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// This is approximative.
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// Ideally should take into accounts some instructions (rcp, etc)
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// are 4 times slower.
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int getCost() { return SUnits.size(); }
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// The block Predecessors and Successors must be all registered
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// before fastSchedule().
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// Fast schedule with no particular requirement.
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void fastSchedule();
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std::vector<SUnit*> getScheduledUnits() { return ScheduledSUnits; }
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// Complete schedule that will try to minimize reg pressure and
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// low latencies, and will fill liveins and liveouts.
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// Needs all MIs to be grouped between BeginBlock and EndBlock.
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// The MIs can be moved after the scheduling,
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// it is just used to allow correct track of live registers.
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void schedule(MachineBasicBlock::iterator BeginBlock,
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MachineBasicBlock::iterator EndBlock);
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bool isScheduled() { return Scheduled; }
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// Needs the block to be scheduled inside
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// TODO: find a way to compute it.
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std::vector<unsigned> &getInternalAdditionnalRegUsage() {
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return InternalAdditionnalPressure;
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}
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std::set<unsigned> &getInRegs() { return LiveInRegs; }
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std::set<unsigned> &getOutRegs() { return LiveOutRegs; }
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void printDebug(bool Full);
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private:
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struct SISchedCandidate : SISchedulerCandidate {
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// The best SUnit candidate.
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SUnit *SU = nullptr;
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unsigned SGPRUsage;
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unsigned VGPRUsage;
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bool IsLowLatency;
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unsigned LowLatencyOffset;
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bool HasLowLatencyNonWaitedParent;
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SISchedCandidate() = default;
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bool isValid() const { return SU; }
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// Copy the status of another candidate without changing policy.
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void setBest(SISchedCandidate &Best) {
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assert(Best.Reason != NoCand && "uninitialized Sched candidate");
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SU = Best.SU;
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Reason = Best.Reason;
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SGPRUsage = Best.SGPRUsage;
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VGPRUsage = Best.VGPRUsage;
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IsLowLatency = Best.IsLowLatency;
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LowLatencyOffset = Best.LowLatencyOffset;
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HasLowLatencyNonWaitedParent = Best.HasLowLatencyNonWaitedParent;
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}
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};
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void undoSchedule();
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void undoReleaseSucc(SUnit *SU, SDep *SuccEdge);
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void releaseSucc(SUnit *SU, SDep *SuccEdge);
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// InOrOutBlock: restrict to links pointing inside the block (true),
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// or restrict to links pointing outside the block (false).
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void releaseSuccessors(SUnit *SU, bool InOrOutBlock);
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void nodeScheduled(SUnit *SU);
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void tryCandidateTopDown(SISchedCandidate &Cand, SISchedCandidate &TryCand);
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void tryCandidateBottomUp(SISchedCandidate &Cand, SISchedCandidate &TryCand);
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SUnit* pickNode();
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void traceCandidate(const SISchedCandidate &Cand);
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void initRegPressure(MachineBasicBlock::iterator BeginBlock,
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MachineBasicBlock::iterator EndBlock);
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};
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struct SIScheduleBlocks {
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std::vector<SIScheduleBlock*> Blocks;
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std::vector<int> TopDownIndex2Block;
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std::vector<int> TopDownBlock2Index;
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};
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enum SISchedulerBlockCreatorVariant {
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LatenciesAlone,
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LatenciesGrouped,
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LatenciesAlonePlusConsecutive
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};
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class SIScheduleBlockCreator {
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SIScheduleDAGMI *DAG;
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// unique_ptr handles freeing memory for us.
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std::vector<std::unique_ptr<SIScheduleBlock>> BlockPtrs;
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std::map<SISchedulerBlockCreatorVariant,
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SIScheduleBlocks> Blocks;
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std::vector<SIScheduleBlock*> CurrentBlocks;
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std::vector<int> Node2CurrentBlock;
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// Topological sort
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// Maps topological index to the node number.
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std::vector<int> TopDownIndex2Block;
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std::vector<int> TopDownBlock2Index;
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std::vector<int> BottomUpIndex2Block;
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// 0 -> Color not given.
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// 1 to SUnits.size() -> Reserved group (you should only add elements to them).
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// Above -> Other groups.
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int NextReservedID;
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int NextNonReservedID;
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std::vector<int> CurrentColoring;
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std::vector<int> CurrentTopDownReservedDependencyColoring;
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std::vector<int> CurrentBottomUpReservedDependencyColoring;
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public:
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SIScheduleBlockCreator(SIScheduleDAGMI *DAG);
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~SIScheduleBlockCreator();
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SIScheduleBlocks
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getBlocks(SISchedulerBlockCreatorVariant BlockVariant);
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bool isSUInBlock(SUnit *SU, unsigned ID);
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private:
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// Give a Reserved color to every high latency.
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void colorHighLatenciesAlone();
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// Create groups of high latencies with a Reserved color.
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void colorHighLatenciesGroups();
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// Compute coloring for topdown and bottom traversals with
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// different colors depending on dependencies on Reserved colors.
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void colorComputeReservedDependencies();
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// Give color to all non-colored SUs according to Reserved groups dependencies.
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void colorAccordingToReservedDependencies();
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// Divides Blocks having no bottom up or top down dependencies on Reserved groups.
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// The new colors are computed according to the dependencies on the other blocks
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// formed with colorAccordingToReservedDependencies.
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void colorEndsAccordingToDependencies();
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// Cut groups into groups with SUs in consecutive order (except for Reserved groups).
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void colorForceConsecutiveOrderInGroup();
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// Merge Constant loads that have all their users into another group to the group.
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// (TODO: else if all their users depend on the same group, put them there)
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void colorMergeConstantLoadsNextGroup();
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// Merge SUs that have all their users into another group to the group
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void colorMergeIfPossibleNextGroup();
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// Merge SUs that have all their users into another group to the group,
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// but only for Reserved groups.
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void colorMergeIfPossibleNextGroupOnlyForReserved();
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// Merge SUs that have all their users into another group to the group,
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// but only if the group is no more than a few SUs.
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void colorMergeIfPossibleSmallGroupsToNextGroup();
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// Divides Blocks with important size.
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// Idea of implementation: attribute new colors depending on topdown and
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// bottom up links to other blocks.
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void cutHugeBlocks();
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// Put in one group all instructions with no users in this scheduling region
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// (we'd want these groups be at the end).
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void regroupNoUserInstructions();
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void createBlocksForVariant(SISchedulerBlockCreatorVariant BlockVariant);
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void topologicalSort();
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void scheduleInsideBlocks();
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void fillStats();
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};
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enum SISchedulerBlockSchedulerVariant {
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BlockLatencyRegUsage,
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BlockRegUsageLatency,
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BlockRegUsage
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};
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class SIScheduleBlockScheduler {
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SIScheduleDAGMI *DAG;
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SISchedulerBlockSchedulerVariant Variant;
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std::vector<SIScheduleBlock*> Blocks;
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std::vector<std::map<unsigned, unsigned>> LiveOutRegsNumUsages;
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std::set<unsigned> LiveRegs;
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// Num of schedulable unscheduled blocks reading the register.
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std::map<unsigned, unsigned> LiveRegsConsumers;
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std::vector<unsigned> LastPosHighLatencyParentScheduled;
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int LastPosWaitedHighLatency;
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std::vector<SIScheduleBlock*> BlocksScheduled;
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unsigned NumBlockScheduled;
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std::vector<SIScheduleBlock*> ReadyBlocks;
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unsigned VregCurrentUsage;
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unsigned SregCurrentUsage;
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// Currently is only approximation.
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unsigned maxVregUsage;
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unsigned maxSregUsage;
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std::vector<unsigned> BlockNumPredsLeft;
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std::vector<unsigned> BlockNumSuccsLeft;
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public:
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SIScheduleBlockScheduler(SIScheduleDAGMI *DAG,
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SISchedulerBlockSchedulerVariant Variant,
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SIScheduleBlocks BlocksStruct);
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~SIScheduleBlockScheduler() = default;
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std::vector<SIScheduleBlock*> getBlocks() { return BlocksScheduled; }
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unsigned getVGPRUsage() { return maxVregUsage; }
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unsigned getSGPRUsage() { return maxSregUsage; }
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private:
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struct SIBlockSchedCandidate : SISchedulerCandidate {
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// The best Block candidate.
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SIScheduleBlock *Block = nullptr;
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bool IsHighLatency;
|
|
|
|
int VGPRUsageDiff;
|
|
|
|
unsigned NumSuccessors;
|
|
|
|
unsigned NumHighLatencySuccessors;
|
|
|
|
unsigned LastPosHighLatParentScheduled;
|
|
|
|
unsigned Height;
|
|
|
|
|
2016-12-10 06:06:55 +08:00
|
|
|
SIBlockSchedCandidate() = default;
|
2016-01-14 00:10:10 +08:00
|
|
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|
|
bool isValid() const { return Block; }
|
|
|
|
|
|
|
|
// Copy the status of another candidate without changing policy.
|
|
|
|
void setBest(SIBlockSchedCandidate &Best) {
|
|
|
|
assert(Best.Reason != NoCand && "uninitialized Sched candidate");
|
|
|
|
Block = Best.Block;
|
|
|
|
Reason = Best.Reason;
|
|
|
|
IsHighLatency = Best.IsHighLatency;
|
|
|
|
VGPRUsageDiff = Best.VGPRUsageDiff;
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|
|
|
NumSuccessors = Best.NumSuccessors;
|
|
|
|
NumHighLatencySuccessors = Best.NumHighLatencySuccessors;
|
|
|
|
LastPosHighLatParentScheduled = Best.LastPosHighLatParentScheduled;
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|
|
|
Height = Best.Height;
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|
|
|
}
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|
|
|
};
|
|
|
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|
|
|
bool tryCandidateLatency(SIBlockSchedCandidate &Cand,
|
|
|
|
SIBlockSchedCandidate &TryCand);
|
|
|
|
bool tryCandidateRegUsage(SIBlockSchedCandidate &Cand,
|
|
|
|
SIBlockSchedCandidate &TryCand);
|
|
|
|
SIScheduleBlock *pickBlock();
|
|
|
|
|
|
|
|
void addLiveRegs(std::set<unsigned> &Regs);
|
|
|
|
void decreaseLiveRegs(SIScheduleBlock *Block, std::set<unsigned> &Regs);
|
|
|
|
void releaseBlockSuccs(SIScheduleBlock *Parent);
|
|
|
|
void blockScheduled(SIScheduleBlock *Block);
|
|
|
|
|
|
|
|
// Check register pressure change
|
|
|
|
// by scheduling a block with these LiveIn and LiveOut.
|
|
|
|
std::vector<int> checkRegUsageImpact(std::set<unsigned> &InRegs,
|
|
|
|
std::set<unsigned> &OutRegs);
|
|
|
|
|
|
|
|
void schedule();
|
|
|
|
};
|
|
|
|
|
|
|
|
struct SIScheduleBlockResult {
|
|
|
|
std::vector<unsigned> SUs;
|
|
|
|
unsigned MaxSGPRUsage;
|
|
|
|
unsigned MaxVGPRUsage;
|
|
|
|
};
|
|
|
|
|
|
|
|
class SIScheduler {
|
|
|
|
SIScheduleDAGMI *DAG;
|
|
|
|
SIScheduleBlockCreator BlockCreator;
|
|
|
|
|
|
|
|
public:
|
2016-12-10 06:06:55 +08:00
|
|
|
SIScheduler(SIScheduleDAGMI *DAG) : DAG(DAG), BlockCreator(DAG) {}
|
2016-01-14 00:10:10 +08:00
|
|
|
|
2016-12-10 06:06:55 +08:00
|
|
|
~SIScheduler() = default;
|
2016-01-14 00:10:10 +08:00
|
|
|
|
|
|
|
struct SIScheduleBlockResult
|
|
|
|
scheduleVariant(SISchedulerBlockCreatorVariant BlockVariant,
|
|
|
|
SISchedulerBlockSchedulerVariant ScheduleVariant);
|
|
|
|
};
|
|
|
|
|
2016-03-11 16:00:27 +08:00
|
|
|
class SIScheduleDAGMI final : public ScheduleDAGMILive {
|
2016-01-14 00:10:10 +08:00
|
|
|
const SIInstrInfo *SITII;
|
|
|
|
const SIRegisterInfo *SITRI;
|
|
|
|
|
|
|
|
std::vector<SUnit> SUnitsLinksBackup;
|
|
|
|
|
|
|
|
// For moveLowLatencies. After all Scheduling variants are tested.
|
|
|
|
std::vector<unsigned> ScheduledSUnits;
|
|
|
|
std::vector<unsigned> ScheduledSUnitsInv;
|
|
|
|
|
|
|
|
unsigned VGPRSetID;
|
|
|
|
unsigned SGPRSetID;
|
|
|
|
|
|
|
|
public:
|
|
|
|
SIScheduleDAGMI(MachineSchedContext *C);
|
|
|
|
|
|
|
|
~SIScheduleDAGMI() override;
|
|
|
|
|
|
|
|
// Entry point for the schedule.
|
|
|
|
void schedule() override;
|
|
|
|
|
|
|
|
// To init Block's RPTracker.
|
|
|
|
void initRPTracker(RegPressureTracker &RPTracker) {
|
2017-02-14 22:29:05 +08:00
|
|
|
RPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin, false, false);
|
2016-01-14 00:10:10 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
MachineBasicBlock *getBB() { return BB; }
|
2016-12-10 06:06:55 +08:00
|
|
|
MachineBasicBlock::iterator getCurrentTop() { return CurrentTop; }
|
|
|
|
MachineBasicBlock::iterator getCurrentBottom() { return CurrentBottom; }
|
2016-01-14 00:10:10 +08:00
|
|
|
LiveIntervals *getLIS() { return LIS; }
|
|
|
|
MachineRegisterInfo *getMRI() { return &MRI; }
|
|
|
|
const TargetRegisterInfo *getTRI() { return TRI; }
|
2016-12-10 06:06:55 +08:00
|
|
|
SUnit& getEntrySU() { return EntrySU; }
|
|
|
|
SUnit& getExitSU() { return ExitSU; }
|
2016-01-14 00:10:10 +08:00
|
|
|
|
|
|
|
void restoreSULinksLeft();
|
|
|
|
|
|
|
|
template<typename _Iterator> void fillVgprSgprCost(_Iterator First,
|
|
|
|
_Iterator End,
|
|
|
|
unsigned &VgprUsage,
|
|
|
|
unsigned &SgprUsage);
|
2016-12-10 06:06:55 +08:00
|
|
|
|
2016-01-14 00:10:10 +08:00
|
|
|
std::set<unsigned> getInRegs() {
|
2016-01-20 08:23:26 +08:00
|
|
|
std::set<unsigned> InRegs;
|
|
|
|
for (const auto &RegMaskPair : RPTracker.getPressure().LiveInRegs) {
|
|
|
|
InRegs.insert(RegMaskPair.RegUnit);
|
|
|
|
}
|
2016-01-14 00:10:10 +08:00
|
|
|
return InRegs;
|
2016-12-10 06:06:55 +08:00
|
|
|
}
|
2016-01-14 00:10:10 +08:00
|
|
|
|
|
|
|
unsigned getVGPRSetID() const { return VGPRSetID; }
|
|
|
|
unsigned getSGPRSetID() const { return SGPRSetID; }
|
|
|
|
|
|
|
|
private:
|
|
|
|
void topologicalSort();
|
|
|
|
// After scheduling is done, improve low latency placements.
|
|
|
|
void moveLowLatencies();
|
|
|
|
|
|
|
|
public:
|
|
|
|
// Some stats for scheduling inside blocks.
|
|
|
|
std::vector<unsigned> IsLowLatencySU;
|
|
|
|
std::vector<unsigned> LowLatencyOffset;
|
|
|
|
std::vector<unsigned> IsHighLatencySU;
|
|
|
|
// Topological sort
|
|
|
|
// Maps topological index to the node number.
|
|
|
|
std::vector<int> TopDownIndex2SU;
|
|
|
|
std::vector<int> BottomUpIndex2SU;
|
|
|
|
};
|
|
|
|
|
2016-12-10 06:06:55 +08:00
|
|
|
} // end namespace llvm
|
2016-01-14 00:10:10 +08:00
|
|
|
|
2016-12-10 06:06:55 +08:00
|
|
|
#endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINESCHEDULER_H
|