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llvm-project/llvm/test/CodeGen/AMDGPU/multi-dword-vgpr-spill.ll

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[AMDGPU] Support for v3i32/v3f32 Added support for dwordx3 for most load/store types, but not DS, and not intrinsics yet. SI (gfx6) does not have dwordx3 instructions, so they are not enabled there. Some of this patch is from Matt Arsenault, also of AMD. Differential Revision: https://reviews.llvm.org/D58902 Change-Id: I913ef54f1433a7149da8d72f4af54dbb13436bd9 llvm-svn: 356659
2019-03-21 20:01:21 +08:00
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -enable-misched=0 -post-RA-scheduler=0 -stress-regalloc=8 < %s | FileCheck %s
; CHECK-LABEL: spill_v2i32:
AMDGPU: Don't fix emergency stack slot at offset 0 This forced the caller to be aware of this, which is an ugly ABI feature. Partially reverts r295877. The original reasons for doing this are mostly fixed. Alloca is now in a non-0 address space, so it should be OK to have 0 as a valid pointer. Since we treat the absolute address as the pointer value, this part only really needed to apply to kernels. Since r357093, we avoid the need to increment/decrement the offset register in more cases, and since r354816 the scavenger can fail without spilling, so it's less critical that we try to avoid an offset that fits in the MUBUF offset. Restrict to callable functions for now to split this into 2 steps to limit thte number of test updates and in case anything breaks. llvm-svn: 362665
2019-06-06 06:37:50 +08:00
; CHECK-DAG: buffer_store_dword v{{.*}} offset:16 ; 4-byte Folded Spill
; CHECK-DAG: buffer_store_dword v{{.*}} offset:20 ; 4-byte Folded Spill
[AMDGPU] Support for v3i32/v3f32 Added support for dwordx3 for most load/store types, but not DS, and not intrinsics yet. SI (gfx6) does not have dwordx3 instructions, so they are not enabled there. Some of this patch is from Matt Arsenault, also of AMD. Differential Revision: https://reviews.llvm.org/D58902 Change-Id: I913ef54f1433a7149da8d72f4af54dbb13436bd9 llvm-svn: 356659
2019-03-21 20:01:21 +08:00
; CHECK: ;;#ASMSTART
; CHECK-NEXT: ;;#ASMEND
AMDGPU: Don't fix emergency stack slot at offset 0 This forced the caller to be aware of this, which is an ugly ABI feature. Partially reverts r295877. The original reasons for doing this are mostly fixed. Alloca is now in a non-0 address space, so it should be OK to have 0 as a valid pointer. Since we treat the absolute address as the pointer value, this part only really needed to apply to kernels. Since r357093, we avoid the need to increment/decrement the offset register in more cases, and since r354816 the scavenger can fail without spilling, so it's less critical that we try to avoid an offset that fits in the MUBUF offset. Restrict to callable functions for now to split this into 2 steps to limit thte number of test updates and in case anything breaks. llvm-svn: 362665
2019-06-06 06:37:50 +08:00
; CHECK-DAG: buffer_load_dword v{{.*}} offset:16 ; 4-byte Folded Reload
; CHECK-DAG: buffer_load_dword v{{.*}} offset:20 ; 4-byte Folded Reload
[AMDGPU] Support for v3i32/v3f32 Added support for dwordx3 for most load/store types, but not DS, and not intrinsics yet. SI (gfx6) does not have dwordx3 instructions, so they are not enabled there. Some of this patch is from Matt Arsenault, also of AMD. Differential Revision: https://reviews.llvm.org/D58902 Change-Id: I913ef54f1433a7149da8d72f4af54dbb13436bd9 llvm-svn: 356659
2019-03-21 20:01:21 +08:00
define void @spill_v2i32() {
entry:
%alloca = alloca <2 x i32>, i32 2, align 4, addrspace(5)
%aptr = getelementptr <2 x i32>, <2 x i32> addrspace(5)* %alloca, i32 1
%a = load volatile <2 x i32>, <2 x i32> addrspace(5)* %aptr
; Force %a to spill.
call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}" ()
%outptr = getelementptr <2 x i32>, <2 x i32> addrspace(5)* %alloca, i32 1
store volatile <2 x i32> %a, <2 x i32> addrspace(5)* %outptr
ret void
}
; CHECK-LABEL: spill_v2f32:
AMDGPU: Don't fix emergency stack slot at offset 0 This forced the caller to be aware of this, which is an ugly ABI feature. Partially reverts r295877. The original reasons for doing this are mostly fixed. Alloca is now in a non-0 address space, so it should be OK to have 0 as a valid pointer. Since we treat the absolute address as the pointer value, this part only really needed to apply to kernels. Since r357093, we avoid the need to increment/decrement the offset register in more cases, and since r354816 the scavenger can fail without spilling, so it's less critical that we try to avoid an offset that fits in the MUBUF offset. Restrict to callable functions for now to split this into 2 steps to limit thte number of test updates and in case anything breaks. llvm-svn: 362665
2019-06-06 06:37:50 +08:00
; CHECK-DAG: buffer_store_dword v{{.*}} offset:16 ; 4-byte Folded Spill
; CHECK-DAG: buffer_store_dword v{{.*}} offset:20 ; 4-byte Folded Spill
[AMDGPU] Support for v3i32/v3f32 Added support for dwordx3 for most load/store types, but not DS, and not intrinsics yet. SI (gfx6) does not have dwordx3 instructions, so they are not enabled there. Some of this patch is from Matt Arsenault, also of AMD. Differential Revision: https://reviews.llvm.org/D58902 Change-Id: I913ef54f1433a7149da8d72f4af54dbb13436bd9 llvm-svn: 356659
2019-03-21 20:01:21 +08:00
; CHECK: ;;#ASMSTART
; CHECK-NEXT: ;;#ASMEND
AMDGPU: Don't fix emergency stack slot at offset 0 This forced the caller to be aware of this, which is an ugly ABI feature. Partially reverts r295877. The original reasons for doing this are mostly fixed. Alloca is now in a non-0 address space, so it should be OK to have 0 as a valid pointer. Since we treat the absolute address as the pointer value, this part only really needed to apply to kernels. Since r357093, we avoid the need to increment/decrement the offset register in more cases, and since r354816 the scavenger can fail without spilling, so it's less critical that we try to avoid an offset that fits in the MUBUF offset. Restrict to callable functions for now to split this into 2 steps to limit thte number of test updates and in case anything breaks. llvm-svn: 362665
2019-06-06 06:37:50 +08:00
; CHECK-DAG: buffer_load_dword v{{.*}} offset:16 ; 4-byte Folded Reload
; CHECK-DAG: buffer_load_dword v{{.*}} offset:20 ; 4-byte Folded Reload
[AMDGPU] Support for v3i32/v3f32 Added support for dwordx3 for most load/store types, but not DS, and not intrinsics yet. SI (gfx6) does not have dwordx3 instructions, so they are not enabled there. Some of this patch is from Matt Arsenault, also of AMD. Differential Revision: https://reviews.llvm.org/D58902 Change-Id: I913ef54f1433a7149da8d72f4af54dbb13436bd9 llvm-svn: 356659
2019-03-21 20:01:21 +08:00
define void @spill_v2f32() {
entry:
%alloca = alloca <2 x i32>, i32 2, align 4, addrspace(5)
%aptr = getelementptr <2 x i32>, <2 x i32> addrspace(5)* %alloca, i32 1
%a = load volatile <2 x i32>, <2 x i32> addrspace(5)* %aptr
; Force %a to spill.
call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}" ()
%outptr = getelementptr <2 x i32>, <2 x i32> addrspace(5)* %alloca, i32 1
store volatile <2 x i32> %a, <2 x i32> addrspace(5)* %outptr
ret void
}
; CHECK-LABEL: spill_v3i32:
AMDGPU: Don't fix emergency stack slot at offset 0 This forced the caller to be aware of this, which is an ugly ABI feature. Partially reverts r295877. The original reasons for doing this are mostly fixed. Alloca is now in a non-0 address space, so it should be OK to have 0 as a valid pointer. Since we treat the absolute address as the pointer value, this part only really needed to apply to kernels. Since r357093, we avoid the need to increment/decrement the offset register in more cases, and since r354816 the scavenger can fail without spilling, so it's less critical that we try to avoid an offset that fits in the MUBUF offset. Restrict to callable functions for now to split this into 2 steps to limit thte number of test updates and in case anything breaks. llvm-svn: 362665
2019-06-06 06:37:50 +08:00
; CHECK-DAG: buffer_store_dword v{{.*}} offset:32 ; 4-byte Folded Spill
; CHECK-DAG: buffer_store_dword v{{.*}} offset:36 ; 4-byte Folded Spill
; CHECK-DAG: buffer_store_dword v{{.*}} offset:40 ; 4-byte Folded Spill
[AMDGPU] Support for v3i32/v3f32 Added support for dwordx3 for most load/store types, but not DS, and not intrinsics yet. SI (gfx6) does not have dwordx3 instructions, so they are not enabled there. Some of this patch is from Matt Arsenault, also of AMD. Differential Revision: https://reviews.llvm.org/D58902 Change-Id: I913ef54f1433a7149da8d72f4af54dbb13436bd9 llvm-svn: 356659
2019-03-21 20:01:21 +08:00
; CHECK: ;;#ASMSTART
; CHECK-NEXT: ;;#ASMEND
AMDGPU: Don't fix emergency stack slot at offset 0 This forced the caller to be aware of this, which is an ugly ABI feature. Partially reverts r295877. The original reasons for doing this are mostly fixed. Alloca is now in a non-0 address space, so it should be OK to have 0 as a valid pointer. Since we treat the absolute address as the pointer value, this part only really needed to apply to kernels. Since r357093, we avoid the need to increment/decrement the offset register in more cases, and since r354816 the scavenger can fail without spilling, so it's less critical that we try to avoid an offset that fits in the MUBUF offset. Restrict to callable functions for now to split this into 2 steps to limit thte number of test updates and in case anything breaks. llvm-svn: 362665
2019-06-06 06:37:50 +08:00
; CHECK-DAG: buffer_load_dword v{{.*}} offset:32 ; 4-byte Folded Reload
; CHECK-DAG: buffer_load_dword v{{.*}} offset:36 ; 4-byte Folded Reload
; CHECK-DAG: buffer_load_dword v{{.*}} offset:40 ; 4-byte Folded Reload
[AMDGPU] Support for v3i32/v3f32 Added support for dwordx3 for most load/store types, but not DS, and not intrinsics yet. SI (gfx6) does not have dwordx3 instructions, so they are not enabled there. Some of this patch is from Matt Arsenault, also of AMD. Differential Revision: https://reviews.llvm.org/D58902 Change-Id: I913ef54f1433a7149da8d72f4af54dbb13436bd9 llvm-svn: 356659
2019-03-21 20:01:21 +08:00
define void @spill_v3i32() {
entry:
%alloca = alloca <3 x i32>, i32 2, align 4, addrspace(5)
%aptr = getelementptr <3 x i32>, <3 x i32> addrspace(5)* %alloca, i32 1
%a = load volatile <3 x i32>, <3 x i32> addrspace(5)* %aptr
; Force %a to spill.
call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}" ()
%outptr = getelementptr <3 x i32>, <3 x i32> addrspace(5)* %alloca, i32 1
store volatile <3 x i32> %a, <3 x i32> addrspace(5)* %outptr
ret void
}
; CHECK-LABEL: spill_v3f32:
AMDGPU: Don't fix emergency stack slot at offset 0 This forced the caller to be aware of this, which is an ugly ABI feature. Partially reverts r295877. The original reasons for doing this are mostly fixed. Alloca is now in a non-0 address space, so it should be OK to have 0 as a valid pointer. Since we treat the absolute address as the pointer value, this part only really needed to apply to kernels. Since r357093, we avoid the need to increment/decrement the offset register in more cases, and since r354816 the scavenger can fail without spilling, so it's less critical that we try to avoid an offset that fits in the MUBUF offset. Restrict to callable functions for now to split this into 2 steps to limit thte number of test updates and in case anything breaks. llvm-svn: 362665
2019-06-06 06:37:50 +08:00
; CHECK-DAG: buffer_store_dword v{{.*}} offset:32 ; 4-byte Folded Spill
; CHECK-DAG: buffer_store_dword v{{.*}} offset:36 ; 4-byte Folded Spill
; CHECK-DAG: buffer_store_dword v{{.*}} offset:40 ; 4-byte Folded Spill
[AMDGPU] Support for v3i32/v3f32 Added support for dwordx3 for most load/store types, but not DS, and not intrinsics yet. SI (gfx6) does not have dwordx3 instructions, so they are not enabled there. Some of this patch is from Matt Arsenault, also of AMD. Differential Revision: https://reviews.llvm.org/D58902 Change-Id: I913ef54f1433a7149da8d72f4af54dbb13436bd9 llvm-svn: 356659
2019-03-21 20:01:21 +08:00
; CHECK: ;;#ASMSTART
; CHECK-NEXT: ;;#ASMEND
AMDGPU: Don't fix emergency stack slot at offset 0 This forced the caller to be aware of this, which is an ugly ABI feature. Partially reverts r295877. The original reasons for doing this are mostly fixed. Alloca is now in a non-0 address space, so it should be OK to have 0 as a valid pointer. Since we treat the absolute address as the pointer value, this part only really needed to apply to kernels. Since r357093, we avoid the need to increment/decrement the offset register in more cases, and since r354816 the scavenger can fail without spilling, so it's less critical that we try to avoid an offset that fits in the MUBUF offset. Restrict to callable functions for now to split this into 2 steps to limit thte number of test updates and in case anything breaks. llvm-svn: 362665
2019-06-06 06:37:50 +08:00
; CHECK-DAG: buffer_load_dword v{{.*}} offset:32 ; 4-byte Folded Reload
; CHECK-DAG: buffer_load_dword v{{.*}} offset:36 ; 4-byte Folded Reload
; CHECK-DAG: buffer_load_dword v{{.*}} offset:40 ; 4-byte Folded Reload
[AMDGPU] Support for v3i32/v3f32 Added support for dwordx3 for most load/store types, but not DS, and not intrinsics yet. SI (gfx6) does not have dwordx3 instructions, so they are not enabled there. Some of this patch is from Matt Arsenault, also of AMD. Differential Revision: https://reviews.llvm.org/D58902 Change-Id: I913ef54f1433a7149da8d72f4af54dbb13436bd9 llvm-svn: 356659
2019-03-21 20:01:21 +08:00
define void @spill_v3f32() {
entry:
%alloca = alloca <3 x i32>, i32 2, align 4, addrspace(5)
%aptr = getelementptr <3 x i32>, <3 x i32> addrspace(5)* %alloca, i32 1
%a = load volatile <3 x i32>, <3 x i32> addrspace(5)* %aptr
; Force %a to spill.
call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}" ()
%outptr = getelementptr <3 x i32>, <3 x i32> addrspace(5)* %alloca, i32 1
store volatile <3 x i32> %a, <3 x i32> addrspace(5)* %outptr
ret void
}
; CHECK-LABEL: spill_v4i32:
AMDGPU: Don't fix emergency stack slot at offset 0 This forced the caller to be aware of this, which is an ugly ABI feature. Partially reverts r295877. The original reasons for doing this are mostly fixed. Alloca is now in a non-0 address space, so it should be OK to have 0 as a valid pointer. Since we treat the absolute address as the pointer value, this part only really needed to apply to kernels. Since r357093, we avoid the need to increment/decrement the offset register in more cases, and since r354816 the scavenger can fail without spilling, so it's less critical that we try to avoid an offset that fits in the MUBUF offset. Restrict to callable functions for now to split this into 2 steps to limit thte number of test updates and in case anything breaks. llvm-svn: 362665
2019-06-06 06:37:50 +08:00
; CHECK-DAG: buffer_store_dword v{{.*}} offset:32 ; 4-byte Folded Spill
; CHECK-DAG: buffer_store_dword v{{.*}} offset:36 ; 4-byte Folded Spill
; CHECK-DAG: buffer_store_dword v{{.*}} offset:40 ; 4-byte Folded Spill
; CHECK-DAG: buffer_store_dword v{{.*}} offset:44 ; 4-byte Folded Spill
[AMDGPU] Support for v3i32/v3f32 Added support for dwordx3 for most load/store types, but not DS, and not intrinsics yet. SI (gfx6) does not have dwordx3 instructions, so they are not enabled there. Some of this patch is from Matt Arsenault, also of AMD. Differential Revision: https://reviews.llvm.org/D58902 Change-Id: I913ef54f1433a7149da8d72f4af54dbb13436bd9 llvm-svn: 356659
2019-03-21 20:01:21 +08:00
; CHECK: ;;#ASMSTART
; CHECK-NEXT: ;;#ASMEND
AMDGPU: Don't fix emergency stack slot at offset 0 This forced the caller to be aware of this, which is an ugly ABI feature. Partially reverts r295877. The original reasons for doing this are mostly fixed. Alloca is now in a non-0 address space, so it should be OK to have 0 as a valid pointer. Since we treat the absolute address as the pointer value, this part only really needed to apply to kernels. Since r357093, we avoid the need to increment/decrement the offset register in more cases, and since r354816 the scavenger can fail without spilling, so it's less critical that we try to avoid an offset that fits in the MUBUF offset. Restrict to callable functions for now to split this into 2 steps to limit thte number of test updates and in case anything breaks. llvm-svn: 362665
2019-06-06 06:37:50 +08:00
; CHECK-DAG: buffer_load_dword v{{.*}} offset:32 ; 4-byte Folded Reload
; CHECK-DAG: buffer_load_dword v{{.*}} offset:36 ; 4-byte Folded Reload
; CHECK-DAG: buffer_load_dword v{{.*}} offset:40 ; 4-byte Folded Reload
; CHECK-DAG: buffer_load_dword v{{.*}} offset:44 ; 4-byte Folded Reload
[AMDGPU] Support for v3i32/v3f32 Added support for dwordx3 for most load/store types, but not DS, and not intrinsics yet. SI (gfx6) does not have dwordx3 instructions, so they are not enabled there. Some of this patch is from Matt Arsenault, also of AMD. Differential Revision: https://reviews.llvm.org/D58902 Change-Id: I913ef54f1433a7149da8d72f4af54dbb13436bd9 llvm-svn: 356659
2019-03-21 20:01:21 +08:00
define void @spill_v4i32() {
entry:
%alloca = alloca <4 x i32>, i32 2, align 4, addrspace(5)
%aptr = getelementptr <4 x i32>, <4 x i32> addrspace(5)* %alloca, i32 1
%a = load volatile <4 x i32>, <4 x i32> addrspace(5)* %aptr
; Force %a to spill.
call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}" ()
%outptr = getelementptr <4 x i32>, <4 x i32> addrspace(5)* %alloca, i32 1
store volatile <4 x i32> %a, <4 x i32> addrspace(5)* %outptr
ret void
}
; CHECK-LABEL: spill_v4f32:
AMDGPU: Don't fix emergency stack slot at offset 0 This forced the caller to be aware of this, which is an ugly ABI feature. Partially reverts r295877. The original reasons for doing this are mostly fixed. Alloca is now in a non-0 address space, so it should be OK to have 0 as a valid pointer. Since we treat the absolute address as the pointer value, this part only really needed to apply to kernels. Since r357093, we avoid the need to increment/decrement the offset register in more cases, and since r354816 the scavenger can fail without spilling, so it's less critical that we try to avoid an offset that fits in the MUBUF offset. Restrict to callable functions for now to split this into 2 steps to limit thte number of test updates and in case anything breaks. llvm-svn: 362665
2019-06-06 06:37:50 +08:00
; CHECK-DAG: buffer_store_dword v{{.*}} offset:32 ; 4-byte Folded Spill
; CHECK-DAG: buffer_store_dword v{{.*}} offset:36 ; 4-byte Folded Spill
; CHECK-DAG: buffer_store_dword v{{.*}} offset:40 ; 4-byte Folded Spill
; CHECK-DAG: buffer_store_dword v{{.*}} offset:44 ; 4-byte Folded Spill
[AMDGPU] Support for v3i32/v3f32 Added support for dwordx3 for most load/store types, but not DS, and not intrinsics yet. SI (gfx6) does not have dwordx3 instructions, so they are not enabled there. Some of this patch is from Matt Arsenault, also of AMD. Differential Revision: https://reviews.llvm.org/D58902 Change-Id: I913ef54f1433a7149da8d72f4af54dbb13436bd9 llvm-svn: 356659
2019-03-21 20:01:21 +08:00
; CHECK: ;;#ASMSTART
; CHECK-NEXT: ;;#ASMEND
AMDGPU: Don't fix emergency stack slot at offset 0 This forced the caller to be aware of this, which is an ugly ABI feature. Partially reverts r295877. The original reasons for doing this are mostly fixed. Alloca is now in a non-0 address space, so it should be OK to have 0 as a valid pointer. Since we treat the absolute address as the pointer value, this part only really needed to apply to kernels. Since r357093, we avoid the need to increment/decrement the offset register in more cases, and since r354816 the scavenger can fail without spilling, so it's less critical that we try to avoid an offset that fits in the MUBUF offset. Restrict to callable functions for now to split this into 2 steps to limit thte number of test updates and in case anything breaks. llvm-svn: 362665
2019-06-06 06:37:50 +08:00
; CHECK-DAG: buffer_load_dword v{{.*}} offset:32 ; 4-byte Folded Reload
; CHECK-DAG: buffer_load_dword v{{.*}} offset:36 ; 4-byte Folded Reload
; CHECK-DAG: buffer_load_dword v{{.*}} offset:40 ; 4-byte Folded Reload
; CHECK-DAG: buffer_load_dword v{{.*}} offset:44 ; 4-byte Folded Reload
[AMDGPU] Support for v3i32/v3f32 Added support for dwordx3 for most load/store types, but not DS, and not intrinsics yet. SI (gfx6) does not have dwordx3 instructions, so they are not enabled there. Some of this patch is from Matt Arsenault, also of AMD. Differential Revision: https://reviews.llvm.org/D58902 Change-Id: I913ef54f1433a7149da8d72f4af54dbb13436bd9 llvm-svn: 356659
2019-03-21 20:01:21 +08:00
define void @spill_v4f32() {
entry:
%alloca = alloca <4 x i32>, i32 2, align 4, addrspace(5)
%aptr = getelementptr <4 x i32>, <4 x i32> addrspace(5)* %alloca, i32 1
%a = load volatile <4 x i32>, <4 x i32> addrspace(5)* %aptr
; Force %a to spill.
call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}" ()
%outptr = getelementptr <4 x i32>, <4 x i32> addrspace(5)* %alloca, i32 1
store volatile <4 x i32> %a, <4 x i32> addrspace(5)* %outptr
ret void
}
; CHECK-LABEL: spill_v5i32:
AMDGPU: Don't fix emergency stack slot at offset 0 This forced the caller to be aware of this, which is an ugly ABI feature. Partially reverts r295877. The original reasons for doing this are mostly fixed. Alloca is now in a non-0 address space, so it should be OK to have 0 as a valid pointer. Since we treat the absolute address as the pointer value, this part only really needed to apply to kernels. Since r357093, we avoid the need to increment/decrement the offset register in more cases, and since r354816 the scavenger can fail without spilling, so it's less critical that we try to avoid an offset that fits in the MUBUF offset. Restrict to callable functions for now to split this into 2 steps to limit thte number of test updates and in case anything breaks. llvm-svn: 362665
2019-06-06 06:37:50 +08:00
; CHECK-DAG: buffer_store_dword v{{.*}} offset:64 ; 4-byte Folded Spill
; CHECK-DAG: buffer_store_dword v{{.*}} offset:68 ; 4-byte Folded Spill
; CHECK-DAG: buffer_store_dword v{{.*}} offset:72 ; 4-byte Folded Spill
; CHECK-DAG: buffer_store_dword v{{.*}} offset:76 ; 4-byte Folded Spill
[AMDGPU] Support for v3i32/v3f32 Added support for dwordx3 for most load/store types, but not DS, and not intrinsics yet. SI (gfx6) does not have dwordx3 instructions, so they are not enabled there. Some of this patch is from Matt Arsenault, also of AMD. Differential Revision: https://reviews.llvm.org/D58902 Change-Id: I913ef54f1433a7149da8d72f4af54dbb13436bd9 llvm-svn: 356659
2019-03-21 20:01:21 +08:00
; CHECK: ;;#ASMSTART
; CHECK-NEXT: ;;#ASMEND
AMDGPU: Don't fix emergency stack slot at offset 0 This forced the caller to be aware of this, which is an ugly ABI feature. Partially reverts r295877. The original reasons for doing this are mostly fixed. Alloca is now in a non-0 address space, so it should be OK to have 0 as a valid pointer. Since we treat the absolute address as the pointer value, this part only really needed to apply to kernels. Since r357093, we avoid the need to increment/decrement the offset register in more cases, and since r354816 the scavenger can fail without spilling, so it's less critical that we try to avoid an offset that fits in the MUBUF offset. Restrict to callable functions for now to split this into 2 steps to limit thte number of test updates and in case anything breaks. llvm-svn: 362665
2019-06-06 06:37:50 +08:00
; CHECK-DAG: buffer_load_dword v{{.*}} offset:64 ; 4-byte Folded Reload
; CHECK-DAG: buffer_load_dword v{{.*}} offset:68 ; 4-byte Folded Reload
; CHECK-DAG: buffer_load_dword v{{.*}} offset:72 ; 4-byte Folded Reload
; CHECK-DAG: buffer_load_dword v{{.*}} offset:76 ; 4-byte Folded Reload
[AMDGPU] Support for v3i32/v3f32 Added support for dwordx3 for most load/store types, but not DS, and not intrinsics yet. SI (gfx6) does not have dwordx3 instructions, so they are not enabled there. Some of this patch is from Matt Arsenault, also of AMD. Differential Revision: https://reviews.llvm.org/D58902 Change-Id: I913ef54f1433a7149da8d72f4af54dbb13436bd9 llvm-svn: 356659
2019-03-21 20:01:21 +08:00
define void @spill_v5i32() {
entry:
%alloca = alloca <5 x i32>, i32 2, align 4, addrspace(5)
%aptr = getelementptr <5 x i32>, <5 x i32> addrspace(5)* %alloca, i32 1
%a = load volatile <5 x i32>, <5 x i32> addrspace(5)* %aptr
; Force %a to spill.
call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}" ()
%outptr = getelementptr <5 x i32>, <5 x i32> addrspace(5)* %alloca, i32 1
store volatile <5 x i32> %a, <5 x i32> addrspace(5)* %outptr
ret void
}
; CHECK-LABEL: spill_v5f32:
AMDGPU: Don't fix emergency stack slot at offset 0 This forced the caller to be aware of this, which is an ugly ABI feature. Partially reverts r295877. The original reasons for doing this are mostly fixed. Alloca is now in a non-0 address space, so it should be OK to have 0 as a valid pointer. Since we treat the absolute address as the pointer value, this part only really needed to apply to kernels. Since r357093, we avoid the need to increment/decrement the offset register in more cases, and since r354816 the scavenger can fail without spilling, so it's less critical that we try to avoid an offset that fits in the MUBUF offset. Restrict to callable functions for now to split this into 2 steps to limit thte number of test updates and in case anything breaks. llvm-svn: 362665
2019-06-06 06:37:50 +08:00
; CHECK-DAG: buffer_store_dword v{{.*}} offset:64 ; 4-byte Folded Spill
; CHECK-DAG: buffer_store_dword v{{.*}} offset:68 ; 4-byte Folded Spill
; CHECK-DAG: buffer_store_dword v{{.*}} offset:72 ; 4-byte Folded Spill
; CHECK-DAG: buffer_store_dword v{{.*}} offset:76 ; 4-byte Folded Spill
[AMDGPU] Support for v3i32/v3f32 Added support for dwordx3 for most load/store types, but not DS, and not intrinsics yet. SI (gfx6) does not have dwordx3 instructions, so they are not enabled there. Some of this patch is from Matt Arsenault, also of AMD. Differential Revision: https://reviews.llvm.org/D58902 Change-Id: I913ef54f1433a7149da8d72f4af54dbb13436bd9 llvm-svn: 356659
2019-03-21 20:01:21 +08:00
; CHECK: ;;#ASMSTART
; CHECK-NEXT: ;;#ASMEND
AMDGPU: Don't fix emergency stack slot at offset 0 This forced the caller to be aware of this, which is an ugly ABI feature. Partially reverts r295877. The original reasons for doing this are mostly fixed. Alloca is now in a non-0 address space, so it should be OK to have 0 as a valid pointer. Since we treat the absolute address as the pointer value, this part only really needed to apply to kernels. Since r357093, we avoid the need to increment/decrement the offset register in more cases, and since r354816 the scavenger can fail without spilling, so it's less critical that we try to avoid an offset that fits in the MUBUF offset. Restrict to callable functions for now to split this into 2 steps to limit thte number of test updates and in case anything breaks. llvm-svn: 362665
2019-06-06 06:37:50 +08:00
; CHECK-DAG: buffer_load_dword v{{.*}} offset:64 ; 4-byte Folded Reload
; CHECK-DAG: buffer_load_dword v{{.*}} offset:68 ; 4-byte Folded Reload
; CHECK-DAG: buffer_load_dword v{{.*}} offset:72 ; 4-byte Folded Reload
; CHECK-DAG: buffer_load_dword v{{.*}} offset:76 ; 4-byte Folded Reload
[AMDGPU] Support for v3i32/v3f32 Added support for dwordx3 for most load/store types, but not DS, and not intrinsics yet. SI (gfx6) does not have dwordx3 instructions, so they are not enabled there. Some of this patch is from Matt Arsenault, also of AMD. Differential Revision: https://reviews.llvm.org/D58902 Change-Id: I913ef54f1433a7149da8d72f4af54dbb13436bd9 llvm-svn: 356659
2019-03-21 20:01:21 +08:00
define void @spill_v5f32() {
entry:
%alloca = alloca <5 x i32>, i32 2, align 4, addrspace(5)
%aptr = getelementptr <5 x i32>, <5 x i32> addrspace(5)* %alloca, i32 1
%a = load volatile <5 x i32>, <5 x i32> addrspace(5)* %aptr
; Force %a to spill.
call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}" ()
%outptr = getelementptr <5 x i32>, <5 x i32> addrspace(5)* %alloca, i32 1
store volatile <5 x i32> %a, <5 x i32> addrspace(5)* %outptr
ret void
}