2018-10-23 00:27:27 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=SI %s
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; RUN: llc -mtriple=amdgcn-- -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI,SIVI %s
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; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s
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2016-11-13 15:01:11 +08:00
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declare half @llvm.maxnum.f16(half %a, half %b)
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declare <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> %b)
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2018-05-23 04:42:00 +08:00
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declare <3 x half> @llvm.maxnum.v3f16(<3 x half> %a, <3 x half> %b)
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declare <4 x half> @llvm.maxnum.v4f16(<4 x half> %a, <4 x half> %b)
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2016-11-13 15:01:11 +08:00
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2017-03-22 05:39:51 +08:00
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define amdgpu_kernel void @maxnum_f16(
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2018-10-23 00:27:27 +08:00
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; SI-LABEL: maxnum_f16:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
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; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
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; SI-NEXT: s_mov_b32 s11, 0xf000
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; SI-NEXT: s_mov_b32 s10, -1
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; SI-NEXT: s_mov_b32 s2, s10
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; SI-NEXT: s_mov_b32 s3, s11
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_mov_b32 s12, s6
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; SI-NEXT: s_mov_b32 s13, s7
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; SI-NEXT: s_mov_b32 s14, s10
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; SI-NEXT: s_mov_b32 s15, s11
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; SI-NEXT: buffer_load_ushort v0, off, s[12:15], 0
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; SI-NEXT: buffer_load_ushort v1, off, s[0:3], 0
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; SI-NEXT: s_mov_b32 s8, s4
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; SI-NEXT: s_mov_b32 s9, s5
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; SI-NEXT: s_waitcnt vmcnt(1)
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; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
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; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
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; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
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; SI-NEXT: v_max_f32_e32 v0, v0, v1
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; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
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; SI-NEXT: buffer_store_short v0, off, s[8:11], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: maxnum_f16:
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; VI: ; %bb.0: ; %entry
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; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
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; VI-NEXT: s_mov_b32 s3, 0xf000
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; VI-NEXT: s_mov_b32 s2, -1
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; VI-NEXT: s_mov_b32 s10, s2
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_mov_b32 s0, s4
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; VI-NEXT: s_mov_b32 s1, s5
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; VI-NEXT: s_mov_b32 s4, s6
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; VI-NEXT: s_mov_b32 s5, s7
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; VI-NEXT: s_mov_b32 s11, s3
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; VI-NEXT: s_mov_b32 s6, s2
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; VI-NEXT: s_mov_b32 s7, s3
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; VI-NEXT: buffer_load_ushort v0, off, s[4:7], 0
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; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0
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; VI-NEXT: s_waitcnt vmcnt(1)
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; VI-NEXT: v_max_f16_e32 v0, v0, v0
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_max_f16_e32 v1, v1, v1
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; VI-NEXT: v_max_f16_e32 v0, v0, v1
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; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
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; VI-NEXT: s_endpgm
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;
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; GFX9-LABEL: maxnum_f16:
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; GFX9: ; %bb.0: ; %entry
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; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
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; GFX9-NEXT: s_mov_b32 s3, 0xf000
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; GFX9-NEXT: s_mov_b32 s2, -1
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; GFX9-NEXT: s_mov_b32 s10, s2
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_mov_b32 s0, s4
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; GFX9-NEXT: s_mov_b32 s1, s5
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; GFX9-NEXT: s_mov_b32 s4, s6
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; GFX9-NEXT: s_mov_b32 s5, s7
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; GFX9-NEXT: s_mov_b32 s11, s3
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; GFX9-NEXT: s_mov_b32 s6, s2
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; GFX9-NEXT: s_mov_b32 s7, s3
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; GFX9-NEXT: buffer_load_ushort v0, off, s[4:7], 0
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; GFX9-NEXT: buffer_load_ushort v1, off, s[8:11], 0
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; GFX9-NEXT: s_waitcnt vmcnt(1)
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; GFX9-NEXT: v_max_f16_e32 v0, v0, v0
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_max_f16_e32 v1, v1, v1
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; GFX9-NEXT: v_max_f16_e32 v0, v0, v1
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; GFX9-NEXT: buffer_store_short v0, off, s[0:3], 0
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; GFX9-NEXT: s_endpgm
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2016-11-13 15:01:11 +08:00
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half addrspace(1)* %r,
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half addrspace(1)* %a,
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half addrspace(1)* %b) {
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entry:
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AMDGPU: Add pass to lower kernel arguments to loads
This replaces most argument uses with loads, but for
now not all.
The code in SelectionDAG for calling convention lowering
is actively harmful for amdgpu_kernel. It attempts to
split the argument types into register legal types, which
results in low quality code for arbitary types. Since
all kernel arguments are passed in memory, we just want the
raw types.
I've tried a couple of methods of mitigating this in SelectionDAG,
but it's easier to just bypass this problem alltogether. It's
possible to hack around the problem in the initial lowering,
but the real problem is the DAG then expects to be able to use
CopyToReg/CopyFromReg for uses of the arguments outside the block.
Exposing the argument loads in the IR also has the advantage
that the LoadStoreVectorizer can merge them.
I'm not sure the best approach to dealing with the IR
argument list is. The patch as-is just leaves the IR arguments
in place, so all the existing code will still compute the same
kernarg size and pointlessly lowers the arguments.
Arguably the frontend should emit kernels with an empty argument
list in the first place. Alternatively a dummy array could be
inserted as a single argument just to reserve space.
This does have some disadvantages. Local pointer kernel arguments can
no longer have AssertZext placed on them as the equivalent !range
metadata is not valid on pointer typed loads. This is mostly bad
for SI which needs to know about the known bits in order to use the
DS instruction offset, so in this case this is not done.
More importantly, this skips noalias arguments since this pass
does not yet convert this to the equivalent !alias.scope and !noalias
metadata. Producing this metadata correctly seems to be tricky,
although this logically is the same as inlining into a function which
doesn't exist. Additionally, exposing these loads to the vectorizer
may result in degraded aliasing information if a pointer load is
merged with another argument load.
I'm also not entirely sure this is preserving the current clover
ABI, although I would greatly prefer if it would stop widening
arguments and match the HSA ABI. As-is I think it is extending
< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.
llvm-svn: 335650
2018-06-27 03:10:00 +08:00
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%a.val = load volatile half, half addrspace(1)* %a
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%b.val = load volatile half, half addrspace(1)* %b
|
2016-11-13 15:01:11 +08:00
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%r.val = call half @llvm.maxnum.f16(half %a.val, half %b.val)
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store half %r.val, half addrspace(1)* %r
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ret void
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}
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2017-03-22 05:39:51 +08:00
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define amdgpu_kernel void @maxnum_f16_imm_a(
|
2018-10-23 00:27:27 +08:00
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; SI-LABEL: maxnum_f16_imm_a:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: s_mov_b32 s10, s2
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; SI-NEXT: s_mov_b32 s11, s3
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_mov_b32 s8, s6
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; SI-NEXT: s_mov_b32 s9, s7
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; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 0
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; SI-NEXT: s_mov_b32 s0, s4
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; SI-NEXT: s_mov_b32 s1, s5
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
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; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
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; SI-NEXT: v_max_f32_e32 v0, 0x40400000, v0
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; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
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|
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
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|
|
; SI-NEXT: s_endpgm
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|
;
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|
; VI-LABEL: maxnum_f16_imm_a:
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|
; VI: ; %bb.0: ; %entry
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|
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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; VI-NEXT: s_mov_b32 s3, 0xf000
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; VI-NEXT: s_mov_b32 s2, -1
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_mov_b32 s0, s4
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; VI-NEXT: s_mov_b32 s1, s5
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; VI-NEXT: s_mov_b32 s4, s6
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; VI-NEXT: s_mov_b32 s5, s7
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; VI-NEXT: s_mov_b32 s6, s2
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; VI-NEXT: s_mov_b32 s7, s3
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; VI-NEXT: buffer_load_ushort v0, off, s[4:7], 0
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_max_f16_e32 v0, v0, v0
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; VI-NEXT: v_max_f16_e32 v0, 0x4200, v0
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; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
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; VI-NEXT: s_endpgm
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;
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; GFX9-LABEL: maxnum_f16_imm_a:
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; GFX9: ; %bb.0: ; %entry
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; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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; GFX9-NEXT: s_mov_b32 s3, 0xf000
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; GFX9-NEXT: s_mov_b32 s2, -1
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_mov_b32 s0, s4
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; GFX9-NEXT: s_mov_b32 s1, s5
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; GFX9-NEXT: s_mov_b32 s4, s6
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; GFX9-NEXT: s_mov_b32 s5, s7
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; GFX9-NEXT: s_mov_b32 s6, s2
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; GFX9-NEXT: s_mov_b32 s7, s3
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; GFX9-NEXT: buffer_load_ushort v0, off, s[4:7], 0
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_max_f16_e32 v0, v0, v0
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; GFX9-NEXT: v_max_f16_e32 v0, 0x4200, v0
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; GFX9-NEXT: buffer_store_short v0, off, s[0:3], 0
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; GFX9-NEXT: s_endpgm
|
2016-11-13 15:01:11 +08:00
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half addrspace(1)* %r,
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half addrspace(1)* %b) {
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entry:
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%b.val = load half, half addrspace(1)* %b
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%r.val = call half @llvm.maxnum.f16(half 3.0, half %b.val)
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|
|
store half %r.val, half addrspace(1)* %r
|
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|
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ret void
|
|
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}
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|
|
|
2017-03-22 05:39:51 +08:00
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|
|
define amdgpu_kernel void @maxnum_f16_imm_b(
|
2018-10-23 00:27:27 +08:00
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|
|
; SI-LABEL: maxnum_f16_imm_b:
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|
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; SI: ; %bb.0: ; %entry
|
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; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
|
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|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
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|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
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|
|
; SI-NEXT: s_mov_b32 s10, s2
|
|
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|
|
; SI-NEXT: s_mov_b32 s11, s3
|
|
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|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_mov_b32 s8, s6
|
|
|
|
|
; SI-NEXT: s_mov_b32 s9, s7
|
|
|
|
|
; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 0
|
|
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|
|
; SI-NEXT: s_mov_b32 s0, s4
|
|
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|
|
; SI-NEXT: s_mov_b32 s1, s5
|
|
|
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
|
|
|
|
|
; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
|
|
|
|
|
; SI-NEXT: v_max_f32_e32 v0, 4.0, v0
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
|
|
|
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: maxnum_f16_imm_b:
|
|
|
|
|
; VI: ; %bb.0: ; %entry
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0xf000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_mov_b32 s0, s4
|
|
|
|
|
; VI-NEXT: s_mov_b32 s1, s5
|
|
|
|
|
; VI-NEXT: s_mov_b32 s4, s6
|
|
|
|
|
; VI-NEXT: s_mov_b32 s5, s7
|
|
|
|
|
; VI-NEXT: s_mov_b32 s6, s2
|
|
|
|
|
; VI-NEXT: s_mov_b32 s7, s3
|
|
|
|
|
; VI-NEXT: buffer_load_ushort v0, off, s[4:7], 0
|
|
|
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
|
|
|
; VI-NEXT: v_max_f16_e32 v0, v0, v0
|
|
|
|
|
; VI-NEXT: v_max_f16_e32 v0, 4.0, v0
|
|
|
|
|
; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; GFX9-LABEL: maxnum_f16_imm_b:
|
|
|
|
|
; GFX9: ; %bb.0: ; %entry
|
|
|
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s3, 0xf000
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s0, s4
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s1, s5
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s4, s6
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s5, s7
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s6, s2
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s7, s3
|
|
|
|
|
; GFX9-NEXT: buffer_load_ushort v0, off, s[4:7], 0
|
|
|
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
|
|
|
; GFX9-NEXT: v_max_f16_e32 v0, v0, v0
|
|
|
|
|
; GFX9-NEXT: v_max_f16_e32 v0, 4.0, v0
|
|
|
|
|
; GFX9-NEXT: buffer_store_short v0, off, s[0:3], 0
|
|
|
|
|
; GFX9-NEXT: s_endpgm
|
2016-11-13 15:01:11 +08:00
|
|
|
half addrspace(1)* %r,
|
|
|
|
|
half addrspace(1)* %a) {
|
|
|
|
|
entry:
|
|
|
|
|
%a.val = load half, half addrspace(1)* %a
|
|
|
|
|
%r.val = call half @llvm.maxnum.f16(half %a.val, half 4.0)
|
|
|
|
|
store half %r.val, half addrspace(1)* %r
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @maxnum_v2f16(
|
2018-10-23 00:27:27 +08:00
|
|
|
; SI-LABEL: maxnum_v2f16:
|
|
|
|
|
; SI: ; %bb.0: ; %entry
|
|
|
|
|
; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_load_dword s6, s[6:7], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dword s0, s[0:1], 0x0
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_lshr_b32 s1, s6, 16
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, s0
|
|
|
|
|
; SI-NEXT: s_lshr_b32 s0, s0, 16
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, s0
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, s1
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, s6
|
|
|
|
|
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
|
|
|
|
|
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
|
|
|
|
|
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v3
|
|
|
|
|
; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
|
|
|
|
|
; SI-NEXT: v_max_f32_e32 v2, v3, v2
|
|
|
|
|
; SI-NEXT: v_max_f32_e32 v0, v0, v1
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s0, s4
|
|
|
|
|
; SI-NEXT: s_mov_b32 s1, s5
|
|
|
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
|
|
|
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
|
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: maxnum_v2f16:
|
|
|
|
|
; VI: ; %bb.0: ; %entry
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0xf000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_mov_b32 s0, s4
|
|
|
|
|
; VI-NEXT: s_mov_b32 s1, s5
|
|
|
|
|
; VI-NEXT: s_load_dword s4, s[6:7], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dword s5, s[8:9], 0x0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: v_max_f16_e64 v1, s4, s4
|
|
|
|
|
; VI-NEXT: v_max_f16_e64 v0, s5, s5
|
|
|
|
|
; VI-NEXT: s_lshr_b32 s4, s4, 16
|
|
|
|
|
; VI-NEXT: s_lshr_b32 s5, s5, 16
|
|
|
|
|
; VI-NEXT: v_max_f16_e32 v0, v1, v0
|
|
|
|
|
; VI-NEXT: v_max_f16_e64 v1, s5, s5
|
|
|
|
|
; VI-NEXT: v_max_f16_e64 v2, s4, s4
|
|
|
|
|
; VI-NEXT: v_max_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; GFX9-LABEL: maxnum_v2f16:
|
|
|
|
|
; GFX9: ; %bb.0: ; %entry
|
|
|
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
|
|
; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s3, 0xf000
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s0, s4
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s1, s5
|
|
|
|
|
; GFX9-NEXT: s_load_dword s4, s[6:7], 0x0
|
|
|
|
|
; GFX9-NEXT: s_load_dword s5, s[8:9], 0x0
|
|
|
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; GFX9-NEXT: v_pk_max_f16 v1, s4, s4
|
|
|
|
|
; GFX9-NEXT: v_pk_max_f16 v0, s5, s5
|
|
|
|
|
; GFX9-NEXT: v_pk_max_f16 v0, v1, v0
|
|
|
|
|
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
|
|
|
; GFX9-NEXT: s_endpgm
|
2016-11-13 15:01:11 +08:00
|
|
|
<2 x half> addrspace(1)* %r,
|
|
|
|
|
<2 x half> addrspace(1)* %a,
|
|
|
|
|
<2 x half> addrspace(1)* %b) {
|
|
|
|
|
entry:
|
|
|
|
|
%a.val = load <2 x half>, <2 x half> addrspace(1)* %a
|
|
|
|
|
%b.val = load <2 x half>, <2 x half> addrspace(1)* %b
|
|
|
|
|
%r.val = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %a.val, <2 x half> %b.val)
|
|
|
|
|
store <2 x half> %r.val, <2 x half> addrspace(1)* %r
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @maxnum_v2f16_imm_a(
|
2018-10-23 00:27:27 +08:00
|
|
|
; SI-LABEL: maxnum_v2f16_imm_a:
|
|
|
|
|
; SI: ; %bb.0: ; %entry
|
|
|
|
|
; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_load_dword s2, s[2:3], 0x0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, s2
|
|
|
|
|
; SI-NEXT: s_lshr_b32 s2, s2, 16
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, s2
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
|
|
|
|
|
; SI-NEXT: v_max_f32_e32 v0, 0x40400000, v0
|
|
|
|
|
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
|
|
|
|
|
; SI-NEXT: v_max_f32_e32 v1, 4.0, v1
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
|
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
|
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
|
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: maxnum_v2f16_imm_a:
|
|
|
|
|
; VI: ; %bb.0: ; %entry
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, 0x4400
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0xf000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_mov_b32 s0, s4
|
|
|
|
|
; VI-NEXT: s_load_dword s4, s[6:7], 0x0
|
|
|
|
|
; VI-NEXT: s_mov_b32 s1, s5
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: v_max_f16_e64 v0, s4, s4
|
|
|
|
|
; VI-NEXT: s_lshr_b32 s4, s4, 16
|
|
|
|
|
; VI-NEXT: v_max_f16_e64 v1, s4, s4
|
|
|
|
|
; VI-NEXT: v_max_f16_e32 v0, 0x4200, v0
|
|
|
|
|
; VI-NEXT: v_max_f16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; GFX9-LABEL: maxnum_v2f16_imm_a:
|
|
|
|
|
; GFX9: ; %bb.0: ; %entry
|
|
|
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s3, 0xf000
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s0, s4
|
|
|
|
|
; GFX9-NEXT: s_load_dword s4, s[6:7], 0x0
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s1, s5
|
|
|
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; GFX9-NEXT: v_pk_max_f16 v0, s4, s4
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s4, 0x44004200
|
|
|
|
|
; GFX9-NEXT: v_pk_max_f16 v0, v0, s4
|
|
|
|
|
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
|
|
|
; GFX9-NEXT: s_endpgm
|
2016-11-13 15:01:11 +08:00
|
|
|
<2 x half> addrspace(1)* %r,
|
|
|
|
|
<2 x half> addrspace(1)* %b) {
|
|
|
|
|
entry:
|
|
|
|
|
%b.val = load <2 x half>, <2 x half> addrspace(1)* %b
|
|
|
|
|
%r.val = call <2 x half> @llvm.maxnum.v2f16(<2 x half> <half 3.0, half 4.0>, <2 x half> %b.val)
|
|
|
|
|
store <2 x half> %r.val, <2 x half> addrspace(1)* %r
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @maxnum_v2f16_imm_b(
|
2018-10-23 00:27:27 +08:00
|
|
|
; SI-LABEL: maxnum_v2f16_imm_b:
|
|
|
|
|
; SI: ; %bb.0: ; %entry
|
|
|
|
|
; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_load_dword s2, s[2:3], 0x0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, s2
|
|
|
|
|
; SI-NEXT: s_lshr_b32 s2, s2, 16
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, s2
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
|
|
|
|
|
; SI-NEXT: v_max_f32_e32 v0, 4.0, v0
|
|
|
|
|
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
|
|
|
|
|
; SI-NEXT: v_max_f32_e32 v1, 0x40400000, v1
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
|
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
|
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
|
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: maxnum_v2f16_imm_b:
|
|
|
|
|
; VI: ; %bb.0: ; %entry
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v2, 0x4200
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0xf000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_mov_b32 s0, s4
|
|
|
|
|
; VI-NEXT: s_load_dword s4, s[6:7], 0x0
|
|
|
|
|
; VI-NEXT: s_mov_b32 s1, s5
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: v_max_f16_e64 v0, s4, s4
|
|
|
|
|
; VI-NEXT: s_lshr_b32 s4, s4, 16
|
|
|
|
|
; VI-NEXT: v_max_f16_e64 v1, s4, s4
|
|
|
|
|
; VI-NEXT: v_max_f16_e32 v0, 4.0, v0
|
|
|
|
|
; VI-NEXT: v_max_f16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; GFX9-LABEL: maxnum_v2f16_imm_b:
|
|
|
|
|
; GFX9: ; %bb.0: ; %entry
|
|
|
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s3, 0xf000
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s0, s4
|
|
|
|
|
; GFX9-NEXT: s_load_dword s4, s[6:7], 0x0
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s1, s5
|
|
|
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; GFX9-NEXT: v_pk_max_f16 v0, s4, s4
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s4, 0x42004400
|
|
|
|
|
; GFX9-NEXT: v_pk_max_f16 v0, v0, s4
|
|
|
|
|
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
|
|
|
; GFX9-NEXT: s_endpgm
|
2016-11-13 15:01:11 +08:00
|
|
|
<2 x half> addrspace(1)* %r,
|
|
|
|
|
<2 x half> addrspace(1)* %a) {
|
|
|
|
|
entry:
|
|
|
|
|
%a.val = load <2 x half>, <2 x half> addrspace(1)* %a
|
|
|
|
|
%r.val = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %a.val, <2 x half> <half 4.0, half 3.0>)
|
|
|
|
|
store <2 x half> %r.val, <2 x half> addrspace(1)* %r
|
|
|
|
|
ret void
|
|
|
|
|
}
|
2018-05-23 04:42:00 +08:00
|
|
|
|
|
|
|
|
; FIXME: Scalarize with undef half
|
|
|
|
|
define amdgpu_kernel void @maxnum_v3f16(
|
2018-10-23 00:27:27 +08:00
|
|
|
; SI-LABEL: maxnum_v3f16:
|
|
|
|
|
; SI: ; %bb.0: ; %entry
|
|
|
|
|
; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[6:7], s[6:7], 0x0
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[8:9], s[8:9], 0x0
|
|
|
|
|
; SI-NEXT: s_mov_b32 s0, s4
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_lshr_b32 s1, s6, 16
|
|
|
|
|
; SI-NEXT: s_lshr_b32 s4, s8, 16
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, s1
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, s4
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, s6
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, s8
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, s7
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, s9
|
|
|
|
|
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
|
|
|
|
|
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v3
|
|
|
|
|
; SI-NEXT: v_max_f32_e32 v2, v3, v2
|
|
|
|
|
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v5
|
|
|
|
|
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
|
|
|
|
|
; SI-NEXT: v_max_f32_e32 v1, v1, v3
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
|
|
|
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v4
|
|
|
|
|
; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
|
|
|
|
|
; SI-NEXT: v_max_f32_e32 v0, v0, v3
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
|
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
|
|
|
; SI-NEXT: s_mov_b32 s1, s5
|
|
|
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
|
|
|
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:4
|
|
|
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: maxnum_v3f16:
|
|
|
|
|
; VI: ; %bb.0: ; %entry
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0xf000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_mov_b32 s0, s4
|
|
|
|
|
; VI-NEXT: s_mov_b32 s1, s5
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[6:7], s[8:9], 0x0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: v_max_f16_e64 v1, s4, s4
|
|
|
|
|
; VI-NEXT: v_max_f16_e64 v0, s6, s6
|
|
|
|
|
; VI-NEXT: s_lshr_b32 s4, s4, 16
|
|
|
|
|
; VI-NEXT: s_lshr_b32 s6, s6, 16
|
|
|
|
|
; VI-NEXT: v_max_f16_e32 v0, v1, v0
|
|
|
|
|
; VI-NEXT: v_max_f16_e64 v1, s6, s6
|
|
|
|
|
; VI-NEXT: v_max_f16_e64 v2, s4, s4
|
|
|
|
|
; VI-NEXT: v_max_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: v_max_f16_e64 v1, s7, s7
|
|
|
|
|
; VI-NEXT: v_max_f16_e64 v2, s5, s5
|
|
|
|
|
; VI-NEXT: v_max_f16_e32 v1, v2, v1
|
|
|
|
|
; VI-NEXT: buffer_store_short v1, off, s[0:3], 0 offset:4
|
|
|
|
|
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; GFX9-LABEL: maxnum_v3f16:
|
|
|
|
|
; GFX9: ; %bb.0: ; %entry
|
|
|
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
|
|
; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s3, 0xf000
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s0, s4
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s1, s5
|
|
|
|
|
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x0
|
|
|
|
|
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[8:9], 0x0
|
|
|
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; GFX9-NEXT: v_pk_max_f16 v1, s4, s4
|
|
|
|
|
; GFX9-NEXT: v_pk_max_f16 v0, s6, s6
|
|
|
|
|
; GFX9-NEXT: v_pk_max_f16 v0, v1, v0
|
|
|
|
|
; GFX9-NEXT: v_pk_max_f16 v2, s7, s7
|
|
|
|
|
; GFX9-NEXT: v_pk_max_f16 v1, s5, s5
|
|
|
|
|
; GFX9-NEXT: v_pk_max_f16 v1, v1, v2
|
|
|
|
|
; GFX9-NEXT: buffer_store_short v1, off, s[0:3], 0 offset:4
|
|
|
|
|
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
|
|
|
; GFX9-NEXT: s_endpgm
|
2018-05-23 04:42:00 +08:00
|
|
|
<3 x half> addrspace(1)* %r,
|
|
|
|
|
<3 x half> addrspace(1)* %a,
|
|
|
|
|
<3 x half> addrspace(1)* %b) {
|
|
|
|
|
entry:
|
|
|
|
|
%a.val = load <3 x half>, <3 x half> addrspace(1)* %a
|
|
|
|
|
%b.val = load <3 x half>, <3 x half> addrspace(1)* %b
|
|
|
|
|
%r.val = call <3 x half> @llvm.maxnum.v3f16(<3 x half> %a.val, <3 x half> %b.val)
|
|
|
|
|
store <3 x half> %r.val, <3 x half> addrspace(1)* %r
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define amdgpu_kernel void @maxnum_v4f16(
|
2018-10-23 00:27:27 +08:00
|
|
|
; SI-LABEL: maxnum_v4f16:
|
|
|
|
|
; SI: ; %bb.0: ; %entry
|
|
|
|
|
; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_mov_b32 s0, s4
|
|
|
|
|
; SI-NEXT: s_mov_b32 s1, s5
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x0
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, s4
|
[AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtr
Summary:
The typo has been present since memOpsHaveSameBasePtr was introduced in
r313208.
It caused SIInstrInfo::shouldClusterMemOps to cluster more mem ops than
it was supposed to.
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71616
2019-12-18 00:09:02 +08:00
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, s5
|
2018-10-23 00:27:27 +08:00
|
|
|
; SI-NEXT: s_lshr_b32 s4, s4, 16
|
[AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtr
Summary:
The typo has been present since memOpsHaveSameBasePtr was introduced in
r313208.
It caused SIInstrInfo::shouldClusterMemOps to cluster more mem ops than
it was supposed to.
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71616
2019-12-18 00:09:02 +08:00
|
|
|
; SI-NEXT: s_lshr_b32 s5, s5, 16
|
2018-10-23 00:27:27 +08:00
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, s4
|
[AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtr
Summary:
The typo has been present since memOpsHaveSameBasePtr was introduced in
r313208.
It caused SIInstrInfo::shouldClusterMemOps to cluster more mem ops than
it was supposed to.
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71616
2019-12-18 00:09:02 +08:00
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, s5
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0
|
|
|
|
|
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
|
|
|
|
|
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
|
|
|
|
|
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v3
|
|
|
|
|
; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_lshr_b32 s6, s5, 16
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, s6
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, s4
|
|
|
|
|
; SI-NEXT: s_lshr_b32 s4, s4, 16
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, s5
|
2018-10-23 00:27:27 +08:00
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v6, s4
|
|
|
|
|
; SI-NEXT: v_mul_f32_e32 v5, 1.0, v5
|
|
|
|
|
; SI-NEXT: v_max_f32_e32 v3, v3, v5
|
|
|
|
|
; SI-NEXT: v_mul_f32_e32 v5, 1.0, v7
|
|
|
|
|
; SI-NEXT: v_max_f32_e32 v1, v1, v5
|
|
|
|
|
; SI-NEXT: v_mul_f32_e32 v5, 1.0, v6
|
|
|
|
|
; SI-NEXT: v_max_f32_e32 v2, v2, v5
|
|
|
|
|
; SI-NEXT: v_mul_f32_e32 v4, 1.0, v4
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
|
|
|
; SI-NEXT: v_max_f32_e32 v0, v0, v4
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
|
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
|
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
|
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
|
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v2
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: maxnum_v4f16:
|
|
|
|
|
; VI: ; %bb.0: ; %entry
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0xf000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_mov_b32 s0, s4
|
|
|
|
|
; VI-NEXT: s_mov_b32 s1, s5
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x0
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[6:7], s[8:9], 0x0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: v_max_f16_e64 v1, s5, s5
|
|
|
|
|
; VI-NEXT: v_max_f16_e64 v0, s7, s7
|
|
|
|
|
; VI-NEXT: s_lshr_b32 s5, s5, 16
|
|
|
|
|
; VI-NEXT: s_lshr_b32 s7, s7, 16
|
|
|
|
|
; VI-NEXT: v_max_f16_e32 v0, v1, v0
|
|
|
|
|
; VI-NEXT: v_max_f16_e64 v2, s5, s5
|
|
|
|
|
; VI-NEXT: v_max_f16_e64 v1, s7, s7
|
|
|
|
|
; VI-NEXT: v_max_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: v_or_b32_sdwa v1, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: v_max_f16_e64 v2, s4, s4
|
|
|
|
|
; VI-NEXT: v_max_f16_e64 v0, s6, s6
|
|
|
|
|
; VI-NEXT: s_lshr_b32 s4, s4, 16
|
|
|
|
|
; VI-NEXT: s_lshr_b32 s5, s6, 16
|
|
|
|
|
; VI-NEXT: v_max_f16_e32 v0, v2, v0
|
|
|
|
|
; VI-NEXT: v_max_f16_e64 v2, s5, s5
|
|
|
|
|
; VI-NEXT: v_max_f16_e64 v3, s4, s4
|
|
|
|
|
; VI-NEXT: v_max_f16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; GFX9-LABEL: maxnum_v4f16:
|
|
|
|
|
; GFX9: ; %bb.0: ; %entry
|
|
|
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
|
|
; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s3, 0xf000
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s0, s4
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s1, s5
|
|
|
|
|
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x0
|
|
|
|
|
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[8:9], 0x0
|
|
|
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; GFX9-NEXT: v_pk_max_f16 v1, s5, s5
|
|
|
|
|
; GFX9-NEXT: v_pk_max_f16 v0, s7, s7
|
|
|
|
|
; GFX9-NEXT: v_pk_max_f16 v1, v1, v0
|
|
|
|
|
; GFX9-NEXT: v_pk_max_f16 v2, s6, s6
|
|
|
|
|
; GFX9-NEXT: v_pk_max_f16 v0, s4, s4
|
|
|
|
|
; GFX9-NEXT: v_pk_max_f16 v0, v0, v2
|
|
|
|
|
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
|
|
|
; GFX9-NEXT: s_endpgm
|
2018-05-23 04:42:00 +08:00
|
|
|
<4 x half> addrspace(1)* %r,
|
|
|
|
|
<4 x half> addrspace(1)* %a,
|
|
|
|
|
<4 x half> addrspace(1)* %b) {
|
|
|
|
|
entry:
|
|
|
|
|
%a.val = load <4 x half>, <4 x half> addrspace(1)* %a
|
|
|
|
|
%b.val = load <4 x half>, <4 x half> addrspace(1)* %b
|
|
|
|
|
%r.val = call <4 x half> @llvm.maxnum.v4f16(<4 x half> %a.val, <4 x half> %b.val)
|
|
|
|
|
store <4 x half> %r.val, <4 x half> addrspace(1)* %r
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define amdgpu_kernel void @fmax_v4f16_imm_a(
|
2018-10-23 00:27:27 +08:00
|
|
|
; SI-LABEL: fmax_v4f16_imm_a:
|
|
|
|
|
; SI: ; %bb.0: ; %entry
|
|
|
|
|
; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
|
|
|
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
|
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: s_mov_b32 s0, s4
|
|
|
|
|
; SI-NEXT: s_mov_b32 s1, s5
|
|
|
|
|
; SI-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x0
|
|
|
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, s5
|
|
|
|
|
; SI-NEXT: s_lshr_b32 s5, s5, 16
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, s4
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, s5
|
|
|
|
|
; SI-NEXT: s_lshr_b32 s4, s4, 16
|
|
|
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, s4
|
|
|
|
|
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
|
|
|
|
|
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
|
|
|
|
|
; SI-NEXT: v_max_f32_e32 v2, 4.0, v2
|
|
|
|
|
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v3
|
|
|
|
|
; SI-NEXT: v_max_f32_e32 v1, 0x40400000, v1
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
|
|
|
; SI-NEXT: v_max_f32_e32 v3, 2.0, v3
|
|
|
|
|
; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
|
|
|
|
|
; SI-NEXT: v_max_f32_e32 v0, 0x41000000, v0
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
|
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
|
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
|
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
|
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3
|
|
|
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v2
|
|
|
|
|
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
|
|
|
; SI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; VI-LABEL: fmax_v4f16_imm_a:
|
|
|
|
|
; VI: ; %bb.0: ; %entry
|
|
|
|
|
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v0, 0x4400
|
|
|
|
|
; VI-NEXT: s_mov_b32 s3, 0xf000
|
|
|
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: s_mov_b32 s0, s4
|
|
|
|
|
; VI-NEXT: s_mov_b32 s1, s5
|
|
|
|
|
; VI-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x0
|
|
|
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; VI-NEXT: v_max_f16_e64 v1, s5, s5
|
|
|
|
|
; VI-NEXT: s_lshr_b32 s5, s5, 16
|
|
|
|
|
; VI-NEXT: v_max_f16_e64 v3, s5, s5
|
|
|
|
|
; VI-NEXT: v_max_f16_e64 v2, s4, s4
|
|
|
|
|
; VI-NEXT: v_max_f16_sdwa v0, v3, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: v_max_f16_e32 v1, 0x4200, v1
|
|
|
|
|
; VI-NEXT: s_lshr_b32 s4, s4, 16
|
|
|
|
|
; VI-NEXT: v_or_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: v_max_f16_e32 v0, 0x4800, v2
|
|
|
|
|
; VI-NEXT: v_max_f16_e64 v2, s4, s4
|
|
|
|
|
; VI-NEXT: v_mov_b32_e32 v3, 0x4000
|
|
|
|
|
; VI-NEXT: v_max_f16_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
|
|
|
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
|
|
|
; VI-NEXT: s_endpgm
|
|
|
|
|
;
|
|
|
|
|
; GFX9-LABEL: fmax_v4f16_imm_a:
|
|
|
|
|
; GFX9: ; %bb.0: ; %entry
|
|
|
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s8, 0x44004200
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s9, 0x40004800
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s3, 0xf000
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s2, -1
|
|
|
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s0, s4
|
|
|
|
|
; GFX9-NEXT: s_mov_b32 s1, s5
|
|
|
|
|
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x0
|
|
|
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
|
|
; GFX9-NEXT: v_pk_max_f16 v0, s5, s5
|
|
|
|
|
; GFX9-NEXT: v_pk_max_f16 v2, s4, s4
|
|
|
|
|
; GFX9-NEXT: v_pk_max_f16 v1, v0, s8
|
|
|
|
|
; GFX9-NEXT: v_pk_max_f16 v0, v2, s9
|
|
|
|
|
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
|
|
|
; GFX9-NEXT: s_endpgm
|
2018-05-23 04:42:00 +08:00
|
|
|
<4 x half> addrspace(1)* %r,
|
|
|
|
|
<4 x half> addrspace(1)* %b) {
|
|
|
|
|
entry:
|
|
|
|
|
%b.val = load <4 x half>, <4 x half> addrspace(1)* %b
|
|
|
|
|
%r.val = call <4 x half> @llvm.maxnum.v4f16(<4 x half> <half 8.0, half 2.0, half 3.0, half 4.0>, <4 x half> %b.val)
|
|
|
|
|
store <4 x half> %r.val, <4 x half> addrspace(1)* %r
|
|
|
|
|
ret void
|
|
|
|
|
}
|