maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/SystemZ/shift-10.ll

92 lines
2.1 KiB
LLVM
Raw Normal View History

Handle (shl (anyext (shr ...))) in SimpilfyDemandedBits This is really an extension of the current (shl (shr ...)) -> shl optimization. The main difference is that certain upper bits must also not be demanded. The motivating examples are the first two in the testcase, which occur in llvmpipe output. llvm-svn: 192783
2013-10-16 18:26:19 +08:00
; Test compound shifts.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
; Test a shift right followed by a sign extension. This can use two shifts.
define i64 @f1(i32 %a) {
; CHECK-LABEL: f1:
[DAG] optimize negation of bool Use mask and negate for legalization of i1 source type with SIGN_EXTEND_INREG. With the mask, this should be no worse than 2 shifts. The mask can be eliminated in some cases, so that should be better than 2 shifts. This change exposed some missing folds related to negation: https://reviews.llvm.org/rL284239 https://reviews.llvm.org/rL284395 There may be others, so please let me know if you see any regressions. Differential Revision: https://reviews.llvm.org/D25485 llvm-svn: 284611
2016-10-20 00:58:59 +08:00
; CHECK: risbg %r0, %r2, 63, 191, 63
; CHECK: lcgr %r2, %r0
Handle (shl (anyext (shr ...))) in SimpilfyDemandedBits This is really an extension of the current (shl (shr ...)) -> shl optimization. The main difference is that certain upper bits must also not be demanded. The motivating examples are the first two in the testcase, which occur in llvmpipe output. llvm-svn: 192783
2013-10-16 18:26:19 +08:00
; CHECK: br %r14
%shr = lshr i32 %a, 1
%trunc = trunc i32 %shr to i1
%ext = sext i1 %trunc to i64
ret i64 %ext
}
[SystemZ] Optimize (sext (ashr (shl ...), ...)) ...into (ashr (shl (anyext X), ...), ...), which requires one fewer instruction. The (anyext X) can sometimes be simplified too. I didn't do this in DAGCombiner because widening shifts isn't a win on all targets. llvm-svn: 199114
2014-01-13 23:17:53 +08:00
; ...and again with the highest shift count that doesn't reduce to an
; ashr/sext pair.
Handle (shl (anyext (shr ...))) in SimpilfyDemandedBits This is really an extension of the current (shl (shr ...)) -> shl optimization. The main difference is that certain upper bits must also not be demanded. The motivating examples are the first two in the testcase, which occur in llvmpipe output. llvm-svn: 192783
2013-10-16 18:26:19 +08:00
define i64 @f2(i32 %a) {
; CHECK-LABEL: f2:
[DAG] optimize negation of bool Use mask and negate for legalization of i1 source type with SIGN_EXTEND_INREG. With the mask, this should be no worse than 2 shifts. The mask can be eliminated in some cases, so that should be better than 2 shifts. This change exposed some missing folds related to negation: https://reviews.llvm.org/rL284239 https://reviews.llvm.org/rL284395 There may be others, so please let me know if you see any regressions. Differential Revision: https://reviews.llvm.org/D25485 llvm-svn: 284611
2016-10-20 00:58:59 +08:00
; CHECK: risbg %r0, %r2, 63, 191, 34
; CHECK: lcgr %r2, %r0
Handle (shl (anyext (shr ...))) in SimpilfyDemandedBits This is really an extension of the current (shl (shr ...)) -> shl optimization. The main difference is that certain upper bits must also not be demanded. The motivating examples are the first two in the testcase, which occur in llvmpipe output. llvm-svn: 192783
2013-10-16 18:26:19 +08:00
; CHECK: br %r14
[SystemZ] Optimize (sext (ashr (shl ...), ...)) ...into (ashr (shl (anyext X), ...), ...), which requires one fewer instruction. The (anyext X) can sometimes be simplified too. I didn't do this in DAGCombiner because widening shifts isn't a win on all targets. llvm-svn: 199114
2014-01-13 23:17:53 +08:00
%shr = lshr i32 %a, 30
Handle (shl (anyext (shr ...))) in SimpilfyDemandedBits This is really an extension of the current (shl (shr ...)) -> shl optimization. The main difference is that certain upper bits must also not be demanded. The motivating examples are the first two in the testcase, which occur in llvmpipe output. llvm-svn: 192783
2013-10-16 18:26:19 +08:00
%trunc = trunc i32 %shr to i1
%ext = sext i1 %trunc to i64
ret i64 %ext
}
; Test a left shift that of an extended right shift in a case where folding
; is possible.
define i64 @f3(i32 %a) {
; CHECK-LABEL: f3:
; CHECK: risbg %r2, %r2, 27, 181, 9
; CHECK: br %r14
%shr = lshr i32 %a, 1
%ext = zext i32 %shr to i64
%shl = shl i64 %ext, 10
%and = and i64 %shl, 137438952960
ret i64 %and
}
; ...and again with a larger right shift.
define i64 @f4(i32 %a) {
; CHECK-LABEL: f4:
; CHECK: risbg %r2, %r2, 30, 158, 3
; CHECK: br %r14
%shr = lshr i32 %a, 30
%ext = sext i32 %shr to i64
%shl = shl i64 %ext, 33
%and = and i64 %shl, 8589934592
ret i64 %and
}
; Repeat the previous test in a case where all bits outside the
[SystemZ] Handle extensions in RxSBG optimizations The input to an RxSBG operation can be narrower as long as the upper bits are don't care. This fixes a FIXME added in r192783. llvm-svn: 192790
2013-10-16 21:35:13 +08:00
; bottom 3 matter.
Handle (shl (anyext (shr ...))) in SimpilfyDemandedBits This is really an extension of the current (shl (shr ...)) -> shl optimization. The main difference is that certain upper bits must also not be demanded. The motivating examples are the first two in the testcase, which occur in llvmpipe output. llvm-svn: 192783
2013-10-16 18:26:19 +08:00
define i64 @f5(i32 %a) {
; CHECK-LABEL: f5:
[SystemZ] Handle extensions in RxSBG optimizations The input to an RxSBG operation can be narrower as long as the upper bits are don't care. This fixes a FIXME added in r192783. llvm-svn: 192790
2013-10-16 21:35:13 +08:00
; CHECK: risbg %r2, %r2, 29, 158, 3
Handle (shl (anyext (shr ...))) in SimpilfyDemandedBits This is really an extension of the current (shl (shr ...)) -> shl optimization. The main difference is that certain upper bits must also not be demanded. The motivating examples are the first two in the testcase, which occur in llvmpipe output. llvm-svn: 192783
2013-10-16 18:26:19 +08:00
; CHECK: lhi %r2, 7
; CHECK: br %r14
%shr = lshr i32 %a, 30
%ext = sext i32 %shr to i64
%shl = shl i64 %ext, 33
%or = or i64 %shl, 7
ret i64 %or
}
Replace sra with srl if a single sign bit is required E.g. (and (sra (i32 x) 31) 2) -> (and (srl (i32 x) 30) 2). llvm-svn: 192884
2013-10-17 19:16:57 +08:00
; Test that SRA gets replaced with SRL if the sign bit is the only one
; that matters.
define i64 @f6(i64 %a) {
; CHECK-LABEL: f6:
; CHECK: risbg %r2, %r2, 55, 183, 19
; CHECK: br %r14
%shl = shl i64 %a, 10
%shr = ashr i64 %shl, 60
%and = and i64 %shr, 256
ret i64 %and
}
[SystemZ] Optimize (sext (ashr (shl ...), ...)) ...into (ashr (shl (anyext X), ...), ...), which requires one fewer instruction. The (anyext X) can sometimes be simplified too. I didn't do this in DAGCombiner because widening shifts isn't a win on all targets. llvm-svn: 199114
2014-01-13 23:17:53 +08:00
; Test another form of f1.
define i64 @f7(i32 %a) {
; CHECK-LABEL: f7:
; CHECK: sllg [[REG:%r[0-5]]], %r2, 62
; CHECK: srag %r2, [[REG]], 63
; CHECK: br %r14
%1 = shl i32 %a, 30
%sext = ashr i32 %1, 31
%ext = sext i32 %sext to i64
ret i64 %ext
}