2017-03-25 03:52:05 +08:00
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//===- AMDGPUUnifyDivergentExitNodes.cpp ----------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This is a variant of the UnifyDivergentExitNodes pass. Rather than ensuring
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// there is at most one ret and one unreachable instruction, it ensures there is
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// at most one divergent exiting block.
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//
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// StructurizeCFG can't deal with multi-exit regions formed by branches to
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// multiple return nodes. It is not desirable to structurize regions with
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// uniform branches, so unifying those to the same return block as divergent
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// branches inhibits use of scalar branching. It still can't deal with the case
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// where one branch goes to return, and one unreachable. Replace unreachable in
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// this case with a return.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Analysis/DivergenceAnalysis.h"
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#include "llvm/Analysis/PostDominators.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/IR/BasicBlock.h"
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#include "llvm/IR/CFG.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Transforms/Scalar.h"
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#include "llvm/Transforms/Utils/Local.h"
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using namespace llvm;
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#define DEBUG_TYPE "amdgpu-unify-divergent-exit-nodes"
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namespace {
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class AMDGPUUnifyDivergentExitNodes : public FunctionPass {
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public:
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static char ID; // Pass identification, replacement for typeid
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AMDGPUUnifyDivergentExitNodes() : FunctionPass(ID) {
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initializeAMDGPUUnifyDivergentExitNodesPass(*PassRegistry::getPassRegistry());
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}
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// We can preserve non-critical-edgeness when we unify function exit nodes
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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bool runOnFunction(Function &F) override;
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};
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}
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char AMDGPUUnifyDivergentExitNodes::ID = 0;
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INITIALIZE_PASS_BEGIN(AMDGPUUnifyDivergentExitNodes, DEBUG_TYPE,
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"Unify divergent function exit nodes", false, false)
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INITIALIZE_PASS_DEPENDENCY(PostDominatorTreeWrapperPass)
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INITIALIZE_PASS_DEPENDENCY(DivergenceAnalysis)
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INITIALIZE_PASS_END(AMDGPUUnifyDivergentExitNodes, DEBUG_TYPE,
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"Unify divergent function exit nodes", false, false)
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char &llvm::AMDGPUUnifyDivergentExitNodesID = AMDGPUUnifyDivergentExitNodes::ID;
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void AMDGPUUnifyDivergentExitNodes::getAnalysisUsage(AnalysisUsage &AU) const{
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// TODO: Preserve dominator tree.
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AU.addRequired<PostDominatorTreeWrapperPass>();
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AU.addRequired<DivergenceAnalysis>();
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// No divergent values are changed, only blocks and branch edges.
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AU.addPreserved<DivergenceAnalysis>();
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// We preserve the non-critical-edgeness property
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AU.addPreservedID(BreakCriticalEdgesID);
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// This is a cluster of orthogonal Transforms
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AU.addPreservedID(LowerSwitchID);
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FunctionPass::getAnalysisUsage(AU);
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AU.addRequired<TargetTransformInfoWrapperPass>();
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}
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/// \returns true if \p BB is reachable through only uniform branches.
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/// XXX - Is there a more efficient way to find this?
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static bool isUniformlyReached(const DivergenceAnalysis &DA,
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BasicBlock &BB) {
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SmallVector<BasicBlock *, 8> Stack;
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SmallPtrSet<BasicBlock *, 8> Visited;
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for (BasicBlock *Pred : predecessors(&BB))
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Stack.push_back(Pred);
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while (!Stack.empty()) {
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BasicBlock *Top = Stack.pop_back_val();
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if (!DA.isUniform(Top->getTerminator()))
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return false;
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for (BasicBlock *Pred : predecessors(Top)) {
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if (Visited.insert(Pred).second)
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Stack.push_back(Pred);
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}
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}
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return true;
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}
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static BasicBlock *unifyReturnBlockSet(Function &F,
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ArrayRef<BasicBlock *> ReturningBlocks,
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const TargetTransformInfo &TTI,
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StringRef Name) {
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// Otherwise, we need to insert a new basic block into the function, add a PHI
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// nodes (if the function returns values), and convert all of the return
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// instructions into unconditional branches.
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//
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BasicBlock *NewRetBlock = BasicBlock::Create(F.getContext(), Name, &F);
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PHINode *PN = nullptr;
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if (F.getReturnType()->isVoidTy()) {
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ReturnInst::Create(F.getContext(), nullptr, NewRetBlock);
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} else {
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// If the function doesn't return void... add a PHI node to the block...
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PN = PHINode::Create(F.getReturnType(), ReturningBlocks.size(),
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"UnifiedRetVal");
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NewRetBlock->getInstList().push_back(PN);
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ReturnInst::Create(F.getContext(), PN, NewRetBlock);
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}
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// Loop over all of the blocks, replacing the return instruction with an
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// unconditional branch.
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//
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for (BasicBlock *BB : ReturningBlocks) {
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// Add an incoming element to the PHI node for every return instruction that
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// is merging into this new block...
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if (PN)
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PN->addIncoming(BB->getTerminator()->getOperand(0), BB);
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BB->getInstList().pop_back(); // Remove the return insn
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BranchInst::Create(NewRetBlock, BB);
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}
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for (BasicBlock *BB : ReturningBlocks) {
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// Cleanup possible branch to unconditional branch to the return.
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2017-09-27 22:54:16 +08:00
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SimplifyCFG(BB, TTI, nullptr, {2});
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2017-03-25 03:52:05 +08:00
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}
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return NewRetBlock;
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}
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bool AMDGPUUnifyDivergentExitNodes::runOnFunction(Function &F) {
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auto &PDT = getAnalysis<PostDominatorTreeWrapperPass>().getPostDomTree();
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if (PDT.getRoots().size() <= 1)
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return false;
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DivergenceAnalysis &DA = getAnalysis<DivergenceAnalysis>();
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// Loop over all of the blocks in a function, tracking all of the blocks that
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// return.
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//
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SmallVector<BasicBlock *, 4> ReturningBlocks;
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SmallVector<BasicBlock *, 4> UnreachableBlocks;
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for (BasicBlock *BB : PDT.getRoots()) {
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if (isa<ReturnInst>(BB->getTerminator())) {
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if (!isUniformlyReached(DA, *BB))
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ReturningBlocks.push_back(BB);
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} else if (isa<UnreachableInst>(BB->getTerminator())) {
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if (!isUniformlyReached(DA, *BB))
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UnreachableBlocks.push_back(BB);
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}
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}
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if (!UnreachableBlocks.empty()) {
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BasicBlock *UnreachableBlock = nullptr;
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if (UnreachableBlocks.size() == 1) {
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UnreachableBlock = UnreachableBlocks.front();
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} else {
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UnreachableBlock = BasicBlock::Create(F.getContext(),
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"UnifiedUnreachableBlock", &F);
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new UnreachableInst(F.getContext(), UnreachableBlock);
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for (BasicBlock *BB : UnreachableBlocks) {
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BB->getInstList().pop_back(); // Remove the unreachable inst.
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BranchInst::Create(UnreachableBlock, BB);
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}
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}
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if (!ReturningBlocks.empty()) {
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// Don't create a new unreachable inst if we have a return. The
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// structurizer/annotator can't handle the multiple exits
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Type *RetTy = F.getReturnType();
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Value *RetVal = RetTy->isVoidTy() ? nullptr : UndefValue::get(RetTy);
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UnreachableBlock->getInstList().pop_back(); // Remove the unreachable inst.
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Function *UnreachableIntrin =
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Intrinsic::getDeclaration(F.getParent(), Intrinsic::amdgcn_unreachable);
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// Insert a call to an intrinsic tracking that this is an unreachable
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// point, in case we want to kill the active lanes or something later.
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CallInst::Create(UnreachableIntrin, {}, "", UnreachableBlock);
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// Don't create a scalar trap. We would only want to trap if this code was
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// really reached, but a scalar trap would happen even if no lanes
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// actually reached here.
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ReturnInst::Create(F.getContext(), RetVal, UnreachableBlock);
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ReturningBlocks.push_back(UnreachableBlock);
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}
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}
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// Now handle return blocks.
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if (ReturningBlocks.empty())
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return false; // No blocks return
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if (ReturningBlocks.size() == 1)
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return false; // Already has a single return block
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const TargetTransformInfo &TTI
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= getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
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unifyReturnBlockSet(F, ReturningBlocks, TTI, "UnifiedReturnBlock");
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return true;
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}
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