llvm-project/llvm/test/CodeGen/X86/vshift_split.ll

; RUN: llc < %s -march=x86 -mattr=+sse2

; Example that requires splitting and expanding a vector shift.
define <2 x i64> @update(<2 x i64> %val) nounwind readnone {
entry:
	%shr = lshr <2 x i64> %val, < i64 2, i64 3 >
	ret <2 x i64> %shr
}
Eliminate more uses of llvm-as and llvm-dis. llvm-svn: 81290 2009-09-09 07:54:48 +08:00			`; RUN: llc < %s -march=x86 -mattr=+sse2`
Fix getNode to allow a vector for the shift amount for shifts of vectors. Fix the shift amount when unrolling a vector shift into scalar shifts. Fix problem in getShuffleScalarElt where it assumes that the input of a bit convert must be a vector. llvm-svn: 60740 2008-12-09 13:46:39 +08:00
			`; Example that requires splitting and expanding a vector shift.`
			`define <2 x i64> @update(<2 x i64> %val) nounwind readnone {`
			`entry:`
Make x86 test actually test x86 code generation. Fix the construct on ARM, which was breaking by coincidence, and add a similar testcase for ARM. llvm-svn: 79719 2009-08-22 11:13:10 +08:00			`%shr = lshr <2 x i64> %val, < i64 2, i64 3 >`
Fix getNode to allow a vector for the shift amount for shifts of vectors. Fix the shift amount when unrolling a vector shift into scalar shifts. Fix problem in getShuffleScalarElt where it assumes that the input of a bit convert must be a vector. llvm-svn: 60740 2008-12-09 13:46:39 +08:00			`ret <2 x i64> %shr`
			`}`