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llvm-project/llvm/test/CodeGen/PowerPC/trunc-srl-load.ll

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[AArch64][PowerPC] add tests for shift sandwich; NFC
2019-12-13 01:36:10 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[DAGCombine] Improve ReduceLoad for SRL Recommitting r329283, third time lucky... If the SRL node is only used by an AND, we may be able to set the ExtVT to the width of the mask, making the AND redundant. To support this, another check has been added in isLegalNarrowLoad which queries whether the load is valid. Differential Revision: https://reviews.llvm.org/D41350 llvm-svn: 329551
2018-04-09 16:16:11 +08:00
; RUN: llc -mtriple=powerpc64-unknown-unknown %s -o - | FileCheck %s
define dso_local fastcc void @trunc_srl_load(i32 zeroext %AttrArgNo) {
[AArch64][PowerPC] add tests for shift sandwich; NFC
2019-12-13 01:36:10 +08:00
; CHECK-LABEL: trunc_srl_load:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz 4, 2(0)
[PowerPC] Ignore implicit register operands for MCInst Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118
2020-04-17 00:22:43 +08:00
; CHECK-NEXT: cmplw 4, 3
[AArch64][PowerPC] add tests for shift sandwich; NFC
2019-12-13 01:36:10 +08:00
; CHECK-NEXT: ble 0, .LBB0_2
; CHECK-NEXT: # %bb.1: # %exit
; CHECK-NEXT: .LBB0_2: # %cond.false
[DAGCombine] Improve ReduceLoad for SRL Recommitting r329283, third time lucky... If the SRL node is only used by an AND, we may be able to set the ExtVT to the width of the mask, making the AND redundant. To support this, another check has been added in isLegalNarrowLoad which queries whether the load is valid. Differential Revision: https://reviews.llvm.org/D41350 llvm-svn: 329551
2018-04-09 16:16:11 +08:00
entry:
%bf.load.i = load i64, i64* null, align 8
%bf.lshr.i = lshr i64 %bf.load.i, 32
%0 = trunc i64 %bf.lshr.i to i32
%bf.cast.i = and i32 %0, 65535
%cmp.i = icmp ugt i32 %bf.cast.i, %AttrArgNo
br i1 %cmp.i, label %exit, label %cond.false
exit: ; preds = %entry
unreachable
cond.false: ; preds = %entry
unreachable
}
[AArch64][PowerPC] add tests for shift sandwich; NFC
2019-12-13 01:36:10 +08:00
define i32 @sh_trunc_sh(i64 %x) {
; CHECK-LABEL: sh_trunc_sh:
; CHECK: # %bb.0:
[DAGCombiner] fold shift-trunc-shift to shift-mask-trunc (2nd try) The initial attempt (rG89633320) botched the logic by reversing the source/dest types. Added x86 tests for additional coverage. The vector tests show a potential improvement (fold vector load instead of broadcasting), but that's a known/existing problem. This fold is done in IR by instcombine, and we have a special form of it already here in DAGCombiner, but we want the more general transform too: https://rise4fun.com/Alive/3jZm Name: general Pre: (C1 + zext(C2) < 64) %s = lshr i64 %x, C1 %t = trunc i64 %s to i16 %r = lshr i16 %t, C2 => %s2 = lshr i64 %x, C1 + zext(C2) %a = and i64 %s2, zext((1 << (16 - C2)) - 1) %r = trunc %a to i16 Name: special Pre: C1 == 48 %s = lshr i64 %x, C1 %t = trunc i64 %s to i16 %r = lshr i16 %t, C2 => %s2 = lshr i64 %x, C1 + zext(C2) %r = trunc %s2 to i16 ...because D58017 exposes a regression without this fold.
2019-12-13 22:40:33 +08:00
; CHECK-NEXT: rldicl 3, 3, 47, 36
[AArch64][PowerPC] add tests for shift sandwich; NFC
2019-12-13 01:36:10 +08:00
; CHECK-NEXT: blr
%s = lshr i64 %x, 13
%t = trunc i64 %s to i32
%r = lshr i32 %t, 4
ret i32 %r
}