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llvm-project/llvm/test/CodeGen/PowerPC/reg-scavenging.ll

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[PowerPC][NFC] Added tests for prologue and epilogue code gen. Added four test files to check the existing behaviour of prologue and epilogue code generation. This patch was done as a setup for the upcoming patch listed on Phabricator that will change how the prologue and epilogue work. The upcoming patch is: https://reviews.llvm.org/D42590 llvm-svn: 353994
2019-02-14 07:37:23 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
define dso_local signext i32 @caller(i32 signext %a, i32 signext %b) local_unnamed_addr {
; CHECK-LABEL: caller:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -240(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 240
; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset v20, -192
; CHECK-NEXT: li r5, 48
[PowerPC] Fix spilling of vector registers in PEI of EH aware functions On little endian targets prior to Power9, we spill vector registers using a swapping store (i.e. stdxvd2x saves the vector with the two doublewords in big endian order regardless of endianness). This is generally not a problem since we restore them using the corresponding swapping load (lxvd2x). However if the restore is done by the unwinder, the vector register contains data in the incorrect order. This patch fixes that by using Altivec loads/stores for vector saves and restores in PEI (which keep the order correct) under those specific conditions: - EH aware function - Subtarget requires swaps for VSX memops (Little Endian prior to Power9) Differential revision: https://reviews.llvm.org/D73692
2020-02-08 04:26:11 +08:00
; CHECK-NEXT: stvx v20, r1, r5 # 16-byte Folded Spill
[PowerPC][NFC] Added tests for prologue and epilogue code gen. Added four test files to check the existing behaviour of prologue and epilogue code generation. This patch was done as a setup for the upcoming patch listed on Phabricator that will change how the prologue and epilogue work. The upcoming patch is: https://reviews.llvm.org/D42590 llvm-svn: 353994
2019-02-14 07:37:23 +08:00
; CHECK-NEXT: #APP
; CHECK-NEXT: add r3, r3, r4
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: bl callee
; CHECK-NEXT: nop
; CHECK-NEXT: li r4, 48
[PowerPC] Fix spilling of vector registers in PEI of EH aware functions On little endian targets prior to Power9, we spill vector registers using a swapping store (i.e. stdxvd2x saves the vector with the two doublewords in big endian order regardless of endianness). This is generally not a problem since we restore them using the corresponding swapping load (lxvd2x). However if the restore is done by the unwinder, the vector register contains data in the incorrect order. This patch fixes that by using Altivec loads/stores for vector saves and restores in PEI (which keep the order correct) under those specific conditions: - EH aware function - Subtarget requires swaps for VSX memops (Little Endian prior to Power9) Differential revision: https://reviews.llvm.org/D73692
2020-02-08 04:26:11 +08:00
; CHECK-NEXT: lvx v20, r1, r4 # 16-byte Folded Reload
[PowerPC][NFC] Added tests for prologue and epilogue code gen. Added four test files to check the existing behaviour of prologue and epilogue code generation. This patch was done as a setup for the upcoming patch listed on Phabricator that will change how the prologue and epilogue work. The upcoming patch is: https://reviews.llvm.org/D42590 llvm-svn: 353994
2019-02-14 07:37:23 +08:00
; CHECK-NEXT: addi r1, r1, 240
; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr
entry:
%0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{v20}"(i32 %a, i32 %b)
%call = tail call signext i32 @callee(i32 signext %0)
ret i32 %call
}
declare signext i32 @callee(i32 signext) local_unnamed_addr