2017-06-13 01:31:36 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2016-10-13 22:27:08 +08:00
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64
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; RUN: llc < %s -mtriple=i386-unknown-unknown | FileCheck %s --check-prefix=X32
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2016-10-12 04:15:20 +08:00
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define i8 @select_i8_neg1_or_0(i1 %a) {
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2016-10-13 22:27:08 +08:00
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; X64-LABEL: select_i8_neg1_or_0:
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2017-12-05 01:18:51 +08:00
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; X64: # %bb.0:
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2016-10-20 00:58:59 +08:00
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; X64-NEXT: andb $1, %dil
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; X64-NEXT: negb %dil
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2016-10-13 22:27:08 +08:00
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: retq
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;
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; X32-LABEL: select_i8_neg1_or_0:
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2017-12-05 01:18:51 +08:00
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; X32: # %bb.0:
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2016-10-13 22:27:08 +08:00
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; X32-NEXT: movb {{[0-9]+}}(%esp), %al
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2016-10-20 00:58:59 +08:00
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; X32-NEXT: andb $1, %al
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; X32-NEXT: negb %al
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2016-10-13 22:27:08 +08:00
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; X32-NEXT: retl
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2016-10-12 04:15:20 +08:00
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%b = sext i1 %a to i8
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ret i8 %b
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}
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define i8 @select_i8_neg1_or_0_zeroext(i1 zeroext %a) {
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2016-10-13 22:27:08 +08:00
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; X64-LABEL: select_i8_neg1_or_0_zeroext:
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2017-12-05 01:18:51 +08:00
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; X64: # %bb.0:
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2016-10-20 00:58:59 +08:00
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; X64-NEXT: negb %dil
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2016-10-13 22:27:08 +08:00
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: retq
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;
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; X32-LABEL: select_i8_neg1_or_0_zeroext:
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2017-12-05 01:18:51 +08:00
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; X32: # %bb.0:
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2016-10-13 22:27:08 +08:00
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; X32-NEXT: movb {{[0-9]+}}(%esp), %al
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2016-10-20 00:58:59 +08:00
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; X32-NEXT: negb %al
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2016-10-13 22:27:08 +08:00
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; X32-NEXT: retl
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2016-10-12 04:15:20 +08:00
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%b = sext i1 %a to i8
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ret i8 %b
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}
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define i16 @select_i16_neg1_or_0(i1 %a) {
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2016-10-13 22:27:08 +08:00
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; X64-LABEL: select_i16_neg1_or_0:
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2017-12-05 01:18:51 +08:00
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; X64: # %bb.0:
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2016-10-20 00:58:59 +08:00
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; X64-NEXT: andl $1, %edi
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; X64-NEXT: negl %edi
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2016-10-13 22:27:08 +08:00
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: retq
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;
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; X32-LABEL: select_i16_neg1_or_0:
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2017-12-05 01:18:51 +08:00
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; X32: # %bb.0:
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2016-10-20 00:58:59 +08:00
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; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: andl $1, %eax
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; X32-NEXT: negl %eax
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2017-11-29 01:15:09 +08:00
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; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
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2016-10-13 22:27:08 +08:00
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; X32-NEXT: retl
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2016-10-12 04:15:20 +08:00
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%b = sext i1 %a to i16
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ret i16 %b
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}
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define i16 @select_i16_neg1_or_0_zeroext(i1 zeroext %a) {
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2016-10-13 22:27:08 +08:00
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; X64-LABEL: select_i16_neg1_or_0_zeroext:
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2017-12-05 01:18:51 +08:00
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; X64: # %bb.0:
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2017-09-19 06:05:35 +08:00
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; X64-NEXT: negl %edi
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; X64-NEXT: movl %edi, %eax
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2016-10-13 22:27:08 +08:00
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; X64-NEXT: retq
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;
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; X32-LABEL: select_i16_neg1_or_0_zeroext:
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2017-12-05 01:18:51 +08:00
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; X32: # %bb.0:
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2016-10-13 22:27:08 +08:00
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; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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2016-10-20 00:58:59 +08:00
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; X32-NEXT: negl %eax
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2017-11-29 01:15:09 +08:00
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; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
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2016-10-13 22:27:08 +08:00
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; X32-NEXT: retl
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2016-10-12 04:15:20 +08:00
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%b = sext i1 %a to i16
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ret i16 %b
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}
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define i32 @select_i32_neg1_or_0(i1 %a) {
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2016-10-13 22:27:08 +08:00
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; X64-LABEL: select_i32_neg1_or_0:
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2017-12-05 01:18:51 +08:00
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; X64: # %bb.0:
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2016-10-20 00:58:59 +08:00
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; X64-NEXT: andl $1, %edi
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; X64-NEXT: negl %edi
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2016-10-13 22:27:08 +08:00
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: retq
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;
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; X32-LABEL: select_i32_neg1_or_0:
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2017-12-05 01:18:51 +08:00
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; X32: # %bb.0:
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2016-10-20 00:58:59 +08:00
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; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: andl $1, %eax
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; X32-NEXT: negl %eax
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2016-10-13 22:27:08 +08:00
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; X32-NEXT: retl
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2016-10-12 04:15:20 +08:00
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%b = sext i1 %a to i32
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ret i32 %b
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}
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define i32 @select_i32_neg1_or_0_zeroext(i1 zeroext %a) {
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2016-10-13 22:27:08 +08:00
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; X64-LABEL: select_i32_neg1_or_0_zeroext:
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2017-12-05 01:18:51 +08:00
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; X64: # %bb.0:
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2017-09-19 06:05:35 +08:00
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; X64-NEXT: negl %edi
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; X64-NEXT: movl %edi, %eax
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2016-10-13 22:27:08 +08:00
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; X64-NEXT: retq
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;
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; X32-LABEL: select_i32_neg1_or_0_zeroext:
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2017-12-05 01:18:51 +08:00
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; X32: # %bb.0:
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2016-10-13 22:27:08 +08:00
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; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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2016-10-20 00:58:59 +08:00
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; X32-NEXT: negl %eax
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2016-10-13 22:27:08 +08:00
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; X32-NEXT: retl
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2016-10-12 04:15:20 +08:00
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%b = sext i1 %a to i32
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ret i32 %b
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}
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define i64 @select_i64_neg1_or_0(i1 %a) {
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2016-10-13 22:27:08 +08:00
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; X64-LABEL: select_i64_neg1_or_0:
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2017-12-05 01:18:51 +08:00
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; X64: # %bb.0:
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2017-11-29 01:15:09 +08:00
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; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
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2016-10-20 00:58:59 +08:00
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; X64-NEXT: andl $1, %edi
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; X64-NEXT: negq %rdi
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2016-10-13 22:27:08 +08:00
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: retq
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;
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; X32-LABEL: select_i64_neg1_or_0:
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2017-12-05 01:18:51 +08:00
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; X32: # %bb.0:
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2016-10-20 00:58:59 +08:00
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; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: andl $1, %eax
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; X32-NEXT: negl %eax
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2016-10-13 22:27:08 +08:00
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; X32-NEXT: movl %eax, %edx
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; X32-NEXT: retl
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2016-10-12 04:15:20 +08:00
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%b = sext i1 %a to i64
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ret i64 %b
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}
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define i64 @select_i64_neg1_or_0_zeroext(i1 zeroext %a) {
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2016-10-13 22:27:08 +08:00
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; X64-LABEL: select_i64_neg1_or_0_zeroext:
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2017-12-05 01:18:51 +08:00
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; X64: # %bb.0:
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2017-09-19 06:05:35 +08:00
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; X64-NEXT: movl %edi, %eax
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2016-10-20 00:58:59 +08:00
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; X64-NEXT: negq %rax
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2016-10-13 22:27:08 +08:00
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; X64-NEXT: retq
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;
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; X32-LABEL: select_i64_neg1_or_0_zeroext:
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2017-12-05 01:18:51 +08:00
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; X32: # %bb.0:
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2016-10-13 22:27:08 +08:00
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; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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2016-10-20 00:58:59 +08:00
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; X32-NEXT: negl %eax
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2016-10-13 22:27:08 +08:00
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; X32-NEXT: movl %eax, %edx
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; X32-NEXT: retl
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2016-10-12 04:15:20 +08:00
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%b = sext i1 %a to i64
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ret i64 %b
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}
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