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llvm-project/llvm/test/CodeGen/X86/GlobalISel/select-blsi.mir

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GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 07:33:31 +08:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
[globalisel][tablegen] Add a GIM_CheckIsSameOperand test where OtherInsnID and OtherOpIdx differ llvm-svn: 315972
2017-10-17 13:24:44 +08:00
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+bmi -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
#
# Test that rules where multiple operands must be the same operand successfully
# match. Also test that the rules do not match when they're not the same
# operand.
#
# This test covers the case when OtherInsnID and OtherOpIdx are different in a
# GIM_CheckIsSameOperand.
---
name: test_blsi32rr
alignment: 4
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
- { id: 3, class: gpr }
# G_SUB and G_AND both use %0 so we should match this.
body: |
bb.1:
liveins: %edi
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 07:33:31 +08:00
; CHECK-LABEL: name: test_blsi32rr
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-25 02:04:54 +08:00
; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY %edi
; CHECK: [[BLSI32rr:%[0-9]+]]:gr32 = BLSI32rr [[COPY]], implicit-def %eflags
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 07:33:31 +08:00
; CHECK: %edi = COPY [[BLSI32rr]]
[globalisel][tablegen] Add a GIM_CheckIsSameOperand test where OtherInsnID and OtherOpIdx differ llvm-svn: 315972
2017-10-17 13:24:44 +08:00
%0(s32) = COPY %edi
%1(s32) = G_CONSTANT i32 0
%2(s32) = G_SUB %1, %0
%3(s32) = G_AND %2, %0
%edi = COPY %3
...
---
name: test_blsi32rr_nomatch
alignment: 4
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
- { id: 3, class: gpr }
# G_SUB and G_AND use different operands so we shouldn't match this.
body: |
bb.1:
liveins: %edi
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 07:33:31 +08:00
; CHECK-LABEL: name: test_blsi32rr_nomatch
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-25 02:04:54 +08:00
; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY %edi
; CHECK: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def %eflags
; CHECK: [[SUB32ri:%[0-9]+]]:gr32 = SUB32ri [[MOV32r0_]], 0, implicit-def %eflags
; CHECK: [[AND32rr:%[0-9]+]]:gr32 = AND32rr [[SUB32ri]], [[COPY]], implicit-def %eflags
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 07:33:31 +08:00
; CHECK: %edi = COPY [[AND32rr]]
[globalisel][tablegen] Add a GIM_CheckIsSameOperand test where OtherInsnID and OtherOpIdx differ llvm-svn: 315972
2017-10-17 13:24:44 +08:00
%0(s32) = COPY %edi
%1(s32) = G_CONSTANT i32 0
%2(s32) = G_SUB %1, %1
%3(s32) = G_AND %2, %0
%edi = COPY %3
...