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llvm-project/llvm/test/CodeGen/X86/GlobalISel/select-add-x32.mir

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GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 07:33:31 +08:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
[GlobalISel][X86] Support add i64 in IA32. Summary: support G_UADDE instruction selection. Reviewers: zvi, guyblank Reviewed By: guyblank Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D33096 llvm-svn: 303255
2017-05-17 20:48:08 +08:00
# RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=X32
--- |
define i64 @test_add_i64(i64 %a, i64 %b) {
%r = add i64 %a, %b
ret i64 %r
}
...
---
name: test_add_i64
alignment: 4
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
- { id: 3, class: gpr }
- { id: 4, class: gpr }
- { id: 5, class: gpr }
- { id: 6, class: gpr }
- { id: 7, class: gpr }
- { id: 8, class: gpr }
- { id: 9, class: gpr }
body: |
bb.0 (%ir-block.0):
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 07:33:31 +08:00
; X32-LABEL: name: test_add_i64
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-25 02:04:54 +08:00
; X32: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
; X32: [[DEF1:%[0-9]+]]:gr32 = IMPLICIT_DEF
; X32: [[DEF2:%[0-9]+]]:gr32 = IMPLICIT_DEF
; X32: [[DEF3:%[0-9]+]]:gr32 = IMPLICIT_DEF
; X32: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr [[DEF]], [[DEF2]], implicit-def %eflags
; X32: [[COPY:%[0-9]+]]:gr32 = COPY %eflags
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 07:33:31 +08:00
; X32: %eflags = COPY [[COPY]]
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-25 02:04:54 +08:00
; X32: [[ADC32rr:%[0-9]+]]:gr32 = ADC32rr [[DEF1]], [[DEF3]], implicit-def %eflags, implicit %eflags
; X32: [[COPY1:%[0-9]+]]:gr32 = COPY %eflags
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 07:33:31 +08:00
; X32: %eax = COPY [[ADD32rr]]
; X32: %edx = COPY [[ADC32rr]]
; X32: RET 0, implicit %eax, implicit %edx
[GlobalISel][X86] Support add i64 in IA32. Summary: support G_UADDE instruction selection. Reviewers: zvi, guyblank Reviewed By: guyblank Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D33096 llvm-svn: 303255
2017-05-17 20:48:08 +08:00
%0(s32) = IMPLICIT_DEF
%1(s32) = IMPLICIT_DEF
%2(s32) = IMPLICIT_DEF
%3(s32) = IMPLICIT_DEF
%9(s8) = G_CONSTANT i8 0
%4(s1) = G_TRUNC %9(s8)
%5(s32), %6(s1) = G_UADDE %0, %2, %4
%7(s32), %8(s1) = G_UADDE %1, %3, %6
%eax = COPY %5(s32)
%edx = COPY %7(s32)
RET 0, implicit %eax, implicit %edx
...