2012-02-28 15:46:26 +08:00
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//===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
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2007-06-06 15:42:06 +08:00
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|
//
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|
// The LLVM Compiler Infrastructure
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//
|
2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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|
// License. See LICENSE.TXT for details.
|
2007-06-06 15:42:06 +08:00
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//
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2011-04-16 05:51:11 +08:00
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//===----------------------------------------------------------------------===//
|
2007-06-06 15:42:06 +08:00
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//
|
2011-07-02 05:01:15 +08:00
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// This file declares the Mips specific subclass of TargetSubtargetInfo.
|
2007-06-06 15:42:06 +08:00
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//
|
2011-04-16 05:51:11 +08:00
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//===----------------------------------------------------------------------===//
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2007-06-06 15:42:06 +08:00
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2014-08-14 00:26:38 +08:00
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#ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
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#define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
|
2007-06-06 15:42:06 +08:00
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|
2015-01-14 19:23:27 +08:00
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|
#include "MCTargetDesc/MipsABIInfo.h"
|
2014-07-03 08:10:24 +08:00
|
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|
#include "MipsFrameLowering.h"
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|
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|
#include "MipsISelLowering.h"
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|
|
|
#include "MipsInstrInfo.h"
|
2016-01-28 00:32:26 +08:00
|
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|
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
|
2017-11-17 09:07:10 +08:00
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
|
2014-07-03 05:29:23 +08:00
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|
#include "llvm/IR/DataLayout.h"
|
2011-06-29 09:14:12 +08:00
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#include "llvm/MC/MCInstrItineraries.h"
|
2013-04-10 03:46:01 +08:00
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|
#include "llvm/Support/ErrorHandling.h"
|
2007-06-06 15:42:06 +08:00
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#include <string>
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|
2011-07-02 04:45:01 +08:00
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#define GET_SUBTARGETINFO_HEADER
|
2011-07-02 06:36:09 +08:00
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#include "MipsGenSubtargetInfo.inc"
|
2011-07-02 04:45:01 +08:00
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|
2007-06-06 15:42:06 +08:00
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|
namespace llvm {
|
2011-07-07 15:07:08 +08:00
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class StringRef;
|
2007-06-06 15:42:06 +08:00
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|
2013-04-10 03:46:01 +08:00
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class MipsTargetMachine;
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|
2011-07-02 04:45:01 +08:00
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|
class MipsSubtarget : public MipsGenSubtargetInfo {
|
2011-12-20 10:50:00 +08:00
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|
virtual void anchor();
|
2007-08-18 09:52:27 +08:00
|
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|
2014-05-09 17:46:21 +08:00
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|
enum MipsArchEnum {
|
2014-11-11 19:43:55 +08:00
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MipsDefault,
|
2015-02-19 00:24:50 +08:00
|
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|
Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
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|
|
Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
|
2014-05-09 17:46:21 +08:00
|
|
|
};
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
|
2015-09-29 02:24:08 +08:00
|
|
|
enum class CPU { P5600 };
|
|
|
|
|
2011-03-05 01:51:39 +08:00
|
|
|
// Mips architecture version
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
MipsArchEnum MipsArchVersion;
|
|
|
|
|
2015-09-29 02:24:08 +08:00
|
|
|
// Processor implementation (unused but required to exist by
|
|
|
|
// tablegen-erated code).
|
|
|
|
CPU ProcImpl;
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
// IsLittle - The target is Little Endian
|
2008-06-04 09:45:25 +08:00
|
|
|
bool IsLittle;
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
|
2015-05-07 18:29:52 +08:00
|
|
|
// IsSoftFloat - The target does not support any floating point instructions.
|
|
|
|
bool IsSoftFloat;
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
// IsSingleFloat - The target only supports single precision float
|
|
|
|
// point operations. This enable the target to use all 32 32-bit
|
2008-07-09 12:45:36 +08:00
|
|
|
// floating point registers instead of only using even ones.
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
bool IsSingleFloat;
|
|
|
|
|
2014-07-10 23:36:12 +08:00
|
|
|
// IsFPXX - MIPS O32 modeless ABI.
|
|
|
|
bool IsFPXX;
|
|
|
|
|
2014-08-08 23:47:17 +08:00
|
|
|
// NoABICalls - Disable SVR4-style position-independent code.
|
|
|
|
bool NoABICalls;
|
2014-08-08 18:01:29 +08:00
|
|
|
|
2008-07-09 12:45:36 +08:00
|
|
|
// IsFP64bit - The target processor has 64-bit floating point registers.
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
bool IsFP64bit;
|
|
|
|
|
2014-07-10 21:38:23 +08:00
|
|
|
/// Are odd single-precision registers permitted?
|
|
|
|
/// This corresponds to -modd-spreg and -mno-odd-spreg
|
|
|
|
bool UseOddSPReg;
|
|
|
|
|
2014-04-16 23:48:55 +08:00
|
|
|
// IsNan2008 - IEEE 754-2008 NaN encoding.
|
|
|
|
bool IsNaN2008bit;
|
|
|
|
|
2017-06-16 00:28:28 +08:00
|
|
|
// IsGP64bit - General-purpose registers are 64 bits wide
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
bool IsGP64bit;
|
|
|
|
|
2016-06-14 19:29:28 +08:00
|
|
|
// IsPTR64bit - Pointers are 64 bit wide
|
|
|
|
bool IsPTR64bit;
|
|
|
|
|
2008-07-09 13:32:22 +08:00
|
|
|
// HasVFPU - Processor has a vector floating point unit.
|
|
|
|
bool HasVFPU;
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
|
2014-03-20 19:51:58 +08:00
|
|
|
// CPU supports cnMIPS (Cavium Networks Octeon CPU).
|
|
|
|
bool HasCnMips;
|
|
|
|
|
2008-07-14 22:42:54 +08:00
|
|
|
// isLinux - Target system is Linux. Is false we consider ELFOS for now.
|
|
|
|
bool IsLinux;
|
|
|
|
|
2012-08-22 11:18:13 +08:00
|
|
|
// UseSmallSection - Small section is used.
|
|
|
|
bool UseSmallSection;
|
|
|
|
|
2008-07-31 01:01:06 +08:00
|
|
|
/// Features related to the presence of specific instructions.
|
2011-03-05 01:51:39 +08:00
|
|
|
|
2014-05-09 21:02:27 +08:00
|
|
|
// HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
|
|
|
|
bool HasMips3_32;
|
|
|
|
|
2014-05-13 19:45:36 +08:00
|
|
|
// HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
|
|
|
|
bool HasMips3_32r2;
|
|
|
|
|
2014-05-12 19:56:16 +08:00
|
|
|
// HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
|
2014-05-09 22:06:17 +08:00
|
|
|
bool HasMips4_32;
|
|
|
|
|
2014-05-12 19:56:16 +08:00
|
|
|
// HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
|
|
|
|
bool HasMips4_32r2;
|
|
|
|
|
2014-05-12 20:52:44 +08:00
|
|
|
// HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
|
|
|
|
bool HasMips5_32r2;
|
|
|
|
|
2012-05-17 06:19:56 +08:00
|
|
|
// InMips16 -- can process Mips16 instructions
|
|
|
|
bool InMips16Mode;
|
|
|
|
|
Checkin in of first of several patches to finish implementation of
mips16/mips32 floating point interoperability.
This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.
Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.
This is needed when returning float, double, single complex, double complex
in the Mips ABI.
Helper functions in libc for mips16 are available to do this.
For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.
Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.
This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.
The only register that is modified is ra in this call.
The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).
llvm-svn: 181641
2013-05-11 06:25:39 +08:00
|
|
|
// Mips16 hard float
|
|
|
|
bool InMips16HardFloat;
|
|
|
|
|
2013-02-05 17:30:03 +08:00
|
|
|
// InMicroMips -- can process MicroMips instructions
|
|
|
|
bool InMicroMipsMode;
|
|
|
|
|
2015-10-13 00:07:25 +08:00
|
|
|
// HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE.
|
|
|
|
bool HasDSP, HasDSPR2, HasDSPR3;
|
2012-09-22 07:41:49 +08:00
|
|
|
|
2013-04-10 03:46:01 +08:00
|
|
|
// Allow mixed Mips16 and Mips32 in one source file
|
|
|
|
bool AllowMixed16_32;
|
|
|
|
|
2013-04-11 00:58:04 +08:00
|
|
|
// Optimize for space by compiling all functions as Mips 16 unless
|
|
|
|
// it needs floating point. Functions needing floating point are
|
|
|
|
// compiled as Mips32
|
|
|
|
bool Os16;
|
|
|
|
|
2013-08-14 04:54:07 +08:00
|
|
|
// HasMSA -- supports MSA ASE.
|
|
|
|
bool HasMSA;
|
|
|
|
|
2015-09-03 20:31:22 +08:00
|
|
|
// UseTCCInDIV -- Enables the use of trapping in the assembler.
|
|
|
|
bool UseTCCInDIV;
|
|
|
|
|
2017-01-27 19:36:52 +08:00
|
|
|
// Sym32 -- On Mips64 symbols are 32 bits.
|
|
|
|
bool HasSym32;
|
|
|
|
|
[mips] Added support for various EVA ASE instructions.
Summary:
Added support for the following instructions:
CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE,
SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF
This required adding some infrastructure for the EVA ASE.
Patch by Scott Egerton.
Reviewers: vkalintiris, dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11139
llvm-svn: 247669
2015-09-15 18:02:16 +08:00
|
|
|
// HasEVA -- supports EVA ASE.
|
|
|
|
bool HasEVA;
|
2017-06-09 15:57:05 +08:00
|
|
|
|
2017-06-06 23:33:01 +08:00
|
|
|
// nomadd4 - disables generation of 4-operand madd.s, madd.d and
|
|
|
|
// related instructions.
|
|
|
|
bool DisableMadd4;
|
[mips] Added support for various EVA ASE instructions.
Summary:
Added support for the following instructions:
CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE,
SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF
This required adding some infrastructure for the EVA ASE.
Patch by Scott Egerton.
Reviewers: vkalintiris, dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11139
llvm-svn: 247669
2015-09-15 18:02:16 +08:00
|
|
|
|
2017-07-12 02:03:20 +08:00
|
|
|
// HasMT -- support MT ASE.
|
|
|
|
bool HasMT;
|
|
|
|
|
2017-07-15 15:14:25 +08:00
|
|
|
// Disable use of the `jal` instruction.
|
|
|
|
bool UseLongCalls = false;
|
|
|
|
|
2017-08-15 05:49:38 +08:00
|
|
|
/// The minimum alignment known to hold of the stack frame on
|
|
|
|
/// entry to the function and which must be maintained by every function.
|
|
|
|
unsigned stackAlignment;
|
|
|
|
|
|
|
|
/// The overridden stack alignment.
|
|
|
|
unsigned StackAlignOverride;
|
|
|
|
|
2007-08-18 09:52:27 +08:00
|
|
|
InstrItineraryData InstrItins;
|
|
|
|
|
2013-04-10 03:46:01 +08:00
|
|
|
// We can override the determination of whether we are in mips16 mode
|
|
|
|
// as from the command line
|
|
|
|
enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
|
|
|
|
|
2015-01-09 02:18:57 +08:00
|
|
|
const MipsTargetMachine &TM;
|
2013-04-10 03:46:01 +08:00
|
|
|
|
2014-02-06 01:19:30 +08:00
|
|
|
Triple TargetTriple;
|
2014-07-02 08:54:12 +08:00
|
|
|
|
2016-01-28 00:32:26 +08:00
|
|
|
const SelectionDAGTargetInfo TSInfo;
|
2014-07-03 08:10:24 +08:00
|
|
|
std::unique_ptr<const MipsInstrInfo> InstrInfo;
|
|
|
|
std::unique_ptr<const MipsFrameLowering> FrameLowering;
|
|
|
|
std::unique_ptr<const MipsTargetLowering> TLInfo;
|
2014-07-03 05:29:23 +08:00
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
public:
|
2016-06-28 22:33:28 +08:00
|
|
|
bool isPositionIndependent() const;
|
2014-07-16 06:39:58 +08:00
|
|
|
/// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
|
2015-06-13 11:42:16 +08:00
|
|
|
bool enablePostRAScheduler() const override;
|
2014-07-16 06:39:58 +08:00
|
|
|
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
|
|
|
|
CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override;
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
|
2015-01-27 01:33:46 +08:00
|
|
|
bool isABI_N64() const;
|
|
|
|
bool isABI_N32() const;
|
|
|
|
bool isABI_O32() const;
|
|
|
|
const MipsABIInfo &getABI() const;
|
2014-07-14 17:40:29 +08:00
|
|
|
bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
/// This constructor initializes the data members to match that
|
2009-08-03 06:11:08 +08:00
|
|
|
/// of the specified triple.
|
2017-05-23 23:00:26 +08:00
|
|
|
MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little,
|
2017-08-15 05:49:38 +08:00
|
|
|
const MipsTargetMachine &TM, unsigned StackAlignOverride);
|
2011-03-05 01:51:39 +08:00
|
|
|
|
|
|
|
/// ParseSubtargetFeatures - Parses features string setting specified
|
2007-06-06 15:42:06 +08:00
|
|
|
/// subtarget options. Definition of function is auto generated by tblgen.
|
2011-07-07 15:07:08 +08:00
|
|
|
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
|
2007-06-06 15:42:06 +08:00
|
|
|
|
2014-07-08 16:59:22 +08:00
|
|
|
bool hasMips1() const { return MipsArchVersion >= Mips1; }
|
2014-05-08 20:40:48 +08:00
|
|
|
bool hasMips2() const { return MipsArchVersion >= Mips2; }
|
2014-05-09 21:02:27 +08:00
|
|
|
bool hasMips3() const { return MipsArchVersion >= Mips3; }
|
2014-07-08 16:59:22 +08:00
|
|
|
bool hasMips4() const { return MipsArchVersion >= Mips4; }
|
|
|
|
bool hasMips5() const { return MipsArchVersion >= Mips5; }
|
2014-05-09 22:06:17 +08:00
|
|
|
bool hasMips4_32() const { return HasMips4_32; }
|
2014-05-12 19:56:16 +08:00
|
|
|
bool hasMips4_32r2() const { return HasMips4_32r2; }
|
2014-06-16 21:18:59 +08:00
|
|
|
bool hasMips32() const {
|
2015-02-04 23:18:11 +08:00
|
|
|
return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
|
|
|
|
hasMips64();
|
2014-06-16 21:18:59 +08:00
|
|
|
}
|
2014-06-12 19:55:58 +08:00
|
|
|
bool hasMips32r2() const {
|
2015-02-04 23:18:11 +08:00
|
|
|
return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
|
|
|
|
hasMips64r2();
|
2014-06-12 19:55:58 +08:00
|
|
|
}
|
2015-02-19 00:24:50 +08:00
|
|
|
bool hasMips32r3() const {
|
|
|
|
return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
|
|
|
|
hasMips64r2();
|
|
|
|
}
|
|
|
|
bool hasMips32r5() const {
|
|
|
|
return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
|
2015-07-20 20:28:56 +08:00
|
|
|
hasMips64r5();
|
2015-02-19 00:24:50 +08:00
|
|
|
}
|
2014-06-12 19:55:58 +08:00
|
|
|
bool hasMips32r6() const {
|
2015-02-04 23:18:11 +08:00
|
|
|
return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
|
|
|
|
hasMips64r6();
|
2014-06-12 19:55:58 +08:00
|
|
|
}
|
2011-09-21 10:24:25 +08:00
|
|
|
bool hasMips64() const { return MipsArchVersion >= Mips64; }
|
2015-02-04 23:18:11 +08:00
|
|
|
bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
|
2015-02-19 00:24:50 +08:00
|
|
|
bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
|
|
|
|
bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }
|
2015-02-04 23:18:11 +08:00
|
|
|
bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
|
2008-06-04 09:45:25 +08:00
|
|
|
|
2014-03-20 19:51:58 +08:00
|
|
|
bool hasCnMips() const { return HasCnMips; }
|
|
|
|
|
2008-06-04 09:45:25 +08:00
|
|
|
bool isLittle() const { return IsLittle; }
|
2014-08-08 23:47:17 +08:00
|
|
|
bool isABICalls() const { return !NoABICalls; }
|
2014-07-10 23:36:12 +08:00
|
|
|
bool isFPXX() const { return IsFPXX; }
|
2009-12-19 15:05:23 +08:00
|
|
|
bool isFP64bit() const { return IsFP64bit; }
|
2014-07-10 21:38:23 +08:00
|
|
|
bool useOddSPReg() const { return UseOddSPReg; }
|
2014-07-29 22:39:24 +08:00
|
|
|
bool noOddSPReg() const { return !UseOddSPReg; }
|
2014-04-16 23:48:55 +08:00
|
|
|
bool isNaN2008() const { return IsNaN2008bit; }
|
2009-12-19 15:05:23 +08:00
|
|
|
bool isGP64bit() const { return IsGP64bit; }
|
|
|
|
bool isGP32bit() const { return !IsGP64bit; }
|
2014-09-09 20:11:16 +08:00
|
|
|
unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
|
2016-06-14 19:29:28 +08:00
|
|
|
bool isPTR64bit() const { return IsPTR64bit; }
|
|
|
|
bool isPTR32bit() const { return !IsPTR64bit; }
|
2017-01-27 19:36:52 +08:00
|
|
|
bool hasSym32() const {
|
|
|
|
return (HasSym32 && isABI_N64()) || isABI_N32() || isABI_O32();
|
|
|
|
}
|
2009-12-19 15:05:23 +08:00
|
|
|
bool isSingleFloat() const { return IsSingleFloat; }
|
2017-02-15 18:48:11 +08:00
|
|
|
bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
|
2009-12-19 15:05:23 +08:00
|
|
|
bool hasVFPU() const { return HasVFPU; }
|
2014-07-19 07:41:32 +08:00
|
|
|
bool inMips16Mode() const { return InMips16Mode; }
|
Checkin in of first of several patches to finish implementation of
mips16/mips32 floating point interoperability.
This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.
Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.
This is needed when returning float, double, single complex, double complex
in the Mips ABI.
Helper functions in libc for mips16 are available to do this.
For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.
Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.
This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.
The only register that is modified is ra in this call.
The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).
llvm-svn: 181641
2013-05-11 06:25:39 +08:00
|
|
|
bool inMips16ModeDefault() const {
|
2013-04-10 03:46:01 +08:00
|
|
|
return InMips16Mode;
|
|
|
|
}
|
2014-07-18 08:08:50 +08:00
|
|
|
// Hard float for mips16 means essentially to compile as soft float
|
|
|
|
// but to use a runtime library for soft float that is written with
|
|
|
|
// native mips32 floating point instructions (those runtime routines
|
|
|
|
// run in mips32 hard float mode).
|
Checkin in of first of several patches to finish implementation of
mips16/mips32 floating point interoperability.
This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.
Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.
This is needed when returning float, double, single complex, double complex
in the Mips ABI.
Helper functions in libc for mips16 are available to do this.
For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.
Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.
This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.
The only register that is modified is ra in this call.
The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).
llvm-svn: 181641
2013-05-11 06:25:39 +08:00
|
|
|
bool inMips16HardFloat() const {
|
|
|
|
return inMips16Mode() && InMips16HardFloat;
|
|
|
|
}
|
2013-02-05 17:30:03 +08:00
|
|
|
bool inMicroMipsMode() const { return InMicroMipsMode; }
|
2015-04-20 20:23:06 +08:00
|
|
|
bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); }
|
2015-08-12 20:45:16 +08:00
|
|
|
bool inMicroMips64r6Mode() const { return InMicroMipsMode && hasMips64r6(); }
|
2012-09-22 07:41:49 +08:00
|
|
|
bool hasDSP() const { return HasDSP; }
|
|
|
|
bool hasDSPR2() const { return HasDSPR2; }
|
2015-10-13 00:07:25 +08:00
|
|
|
bool hasDSPR3() const { return HasDSPR3; }
|
2013-08-14 04:54:07 +08:00
|
|
|
bool hasMSA() const { return HasMSA; }
|
2017-06-06 23:33:01 +08:00
|
|
|
bool disableMadd4() const { return DisableMadd4; }
|
[mips] Added support for various EVA ASE instructions.
Summary:
Added support for the following instructions:
CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE,
SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF
This required adding some infrastructure for the EVA ASE.
Patch by Scott Egerton.
Reviewers: vkalintiris, dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11139
llvm-svn: 247669
2015-09-15 18:02:16 +08:00
|
|
|
bool hasEVA() const { return HasEVA; }
|
2017-07-12 02:03:20 +08:00
|
|
|
bool hasMT() const { return HasMT; }
|
2012-08-22 11:18:13 +08:00
|
|
|
bool useSmallSection() const { return UseSmallSection; }
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
|
2012-05-22 11:10:09 +08:00
|
|
|
bool hasStandardEncoding() const { return !inMips16Mode(); }
|
|
|
|
|
2015-05-08 07:10:23 +08:00
|
|
|
bool useSoftFloat() const { return IsSoftFloat; }
|
2013-08-31 03:40:56 +08:00
|
|
|
|
2017-07-15 15:14:25 +08:00
|
|
|
bool useLongCalls() const { return UseLongCalls; }
|
|
|
|
|
2013-10-08 03:06:57 +08:00
|
|
|
bool enableLongBranchPass() const {
|
|
|
|
return hasStandardEncoding() || allowMixed16_32();
|
|
|
|
}
|
|
|
|
|
2008-07-31 01:01:06 +08:00
|
|
|
/// Features related to the presence of specific instructions.
|
2013-10-10 07:36:17 +08:00
|
|
|
bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
|
2014-07-14 17:40:29 +08:00
|
|
|
bool hasMTHC1() const { return hasMips32r2(); }
|
2013-01-19 05:20:38 +08:00
|
|
|
|
Checkin in of first of several patches to finish implementation of
mips16/mips32 floating point interoperability.
This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.
Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.
This is needed when returning float, double, single complex, double complex
in the Mips ABI.
Helper functions in libc for mips16 are available to do this.
For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.
Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.
This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.
The only register that is modified is ra in this call.
The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).
llvm-svn: 181641
2013-05-11 06:25:39 +08:00
|
|
|
bool allowMixed16_32() const { return inMips16ModeDefault() |
|
2015-01-16 18:45:15 +08:00
|
|
|
AllowMixed16_32; }
|
2013-04-10 03:46:01 +08:00
|
|
|
|
2015-01-16 18:45:15 +08:00
|
|
|
bool os16() const { return Os16; }
|
2013-04-11 00:58:04 +08:00
|
|
|
|
2014-02-06 01:19:30 +08:00
|
|
|
bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
|
|
|
|
|
2017-02-15 18:48:11 +08:00
|
|
|
bool isXRaySupported() const override { return true; }
|
|
|
|
|
2014-04-16 22:38:27 +08:00
|
|
|
// for now constant islands are on for the whole compilation unit but we only
|
|
|
|
// really use them if in addition we are in mips16 mode
|
|
|
|
static bool useConstantIslands();
|
2013-10-30 03:29:03 +08:00
|
|
|
|
2017-08-15 05:49:38 +08:00
|
|
|
unsigned getStackAlignment() const { return stackAlignment; }
|
2013-10-30 03:29:03 +08:00
|
|
|
|
2013-01-30 10:16:36 +08:00
|
|
|
// Grab relocation model
|
2014-07-19 06:34:20 +08:00
|
|
|
Reloc::Model getRelocationModel() const;
|
2013-04-10 03:46:01 +08:00
|
|
|
|
2014-07-03 08:10:24 +08:00
|
|
|
MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
|
2015-01-09 02:18:57 +08:00
|
|
|
const TargetMachine &TM);
|
2014-07-02 09:14:43 +08:00
|
|
|
|
2014-05-23 21:18:02 +08:00
|
|
|
/// Does the system support unaligned memory access.
|
|
|
|
///
|
|
|
|
/// MIPS32r6/MIPS64r6 require full unaligned access support but does not
|
|
|
|
/// specify which component of the system provides it. Hardware, software, and
|
|
|
|
/// hybrid implementations are all valid.
|
|
|
|
bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
|
2014-07-02 08:54:12 +08:00
|
|
|
|
2014-07-03 08:10:24 +08:00
|
|
|
// Set helper classes
|
|
|
|
void setHelperClassesMips16();
|
|
|
|
void setHelperClassesMipsSE();
|
|
|
|
|
2016-01-28 00:32:26 +08:00
|
|
|
const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
|
2014-08-05 05:25:23 +08:00
|
|
|
return &TSInfo;
|
|
|
|
}
|
|
|
|
const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
|
|
|
|
const TargetFrameLowering *getFrameLowering() const override {
|
2014-07-03 08:10:24 +08:00
|
|
|
return FrameLowering.get();
|
|
|
|
}
|
2014-08-05 05:25:23 +08:00
|
|
|
const MipsRegisterInfo *getRegisterInfo() const override {
|
2014-07-03 08:10:24 +08:00
|
|
|
return &InstrInfo->getRegisterInfo();
|
|
|
|
}
|
2014-08-05 05:25:23 +08:00
|
|
|
const MipsTargetLowering *getTargetLowering() const override {
|
|
|
|
return TLInfo.get();
|
|
|
|
}
|
|
|
|
const InstrItineraryData *getInstrItineraryData() const override {
|
|
|
|
return &InstrItins;
|
|
|
|
}
|
2007-06-06 15:42:06 +08:00
|
|
|
};
|
2015-06-23 17:49:53 +08:00
|
|
|
} // End llvm namespace
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
#endif
|