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llvm-project/llvm/test/MC/RISCV/rvf-pseudos.s

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[RISCV] Implement pseudo instructions for load/store from a symbol address. Summary: Those pseudo-instructions are making load/store instructions able to load/store from/to a symbol, and its always using PC-relative addressing to generating a symbol address. Reviewers: asb, apazos, rogfer01, jrtc27 Differential Revision: https://reviews.llvm.org/D50496 llvm-svn: 354430
2019-02-20 11:31:32 +08:00
# RUN: llvm-mc %s -triple=riscv32 -mattr=+f | FileCheck %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+f | FileCheck %s
# CHECK: .Lpcrel_hi0:
# CHECK: auipc a2, %pcrel_hi(a_symbol)
# CHECK: flw fa2, %pcrel_lo(.Lpcrel_hi0)(a2)
flw fa2, a_symbol, a2
# CHECK: .Lpcrel_hi1:
# CHECK: auipc a3, %pcrel_hi(a_symbol)
# CHECK: fsw fa2, %pcrel_lo(.Lpcrel_hi1)(a3)
fsw fa2, a_symbol, a3